-- M O T O R O L A S S D T J T A G S O F T W A R E
--
-- Revision History:
-- 1.0, Carmen Vargas, Jan 18, 2002
-- * Original based off of 144 pin BSDL.
entity MMC2114_SIKA256 is
generic (PHYSICAL_PIN_MAP : string := "LQFP");
port (TRST: in bit;
TCK: in bit;
TMS: in bit;
TDI: in bit;
TDO: out bit;
TEST: in bit;
DE: in bit;
ICOC2: inout bit_vector(0 to 3);
ICOC1: inout bit_vector(0 to 3);
RXD2: inout bit;
TXD2: inout bit;
RXD1: inout bit;
TXD1: inout bit;
SS: inout bit;
SCK: inout bit;
MISO: inout bit;
MOSI: inout bit;
INT: inout bit_vector(0 to 7);
PA: inout bit_vector(0 to 7);
PB: inout bit_vector(0 to 7);
PC: inout bit_vector(0 to 7);
PD: inout bit_vector(0 to 7);
PE: inout bit_vector(5 to 7);
RSTOUT: inout bit;
RESET: inout bit;
CLKOUT: inout bit;
VSS: linkage bit_vector(0 to 5);
VDD: linkage bit_vector(0 to 4);
VSSF: linkage bit;
VDDF: linkage bit;
VPP: linkage bit;
VSTBY: linkage bit;
VDDH: linkage bit;
PQB3: linkage bit;
PQB2: linkage bit;
PQB1: linkage bit;
PQB0: linkage bit;
PQA4: linkage bit;
PQA3: linkage bit;
PQA1: linkage bit;
PQA0: linkage bit;
VRL: linkage bit;
VRH: linkage bit;
VSSA: linkage bit;
VDDA: linkage bit;
PLL_ENABLE: linkage bit;
XTAL: linkage bit;
EXTAL: linkage bit);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of MMC2114_SIKA256 : entity is "STD_1149_1_1993";
attribute PIN_MAP of MMC2114_SIKA256 : entity is PHYSICAL_PIN_MAP;
constant LQFP : PIN_MAP_STRING :=
"PA: (7, 6, 5, 4, 3, 2, 1, 100), " &
"PB: (17, 16, 15, 14, 11, 10, 9, 8), " &
"PC: (27, 26, 25, 24, 23, 20, 19, 18), " &
"PD: (35, 34, 33, 32, 31, 30, 29, 28), " &
"PE: (69, 68, 67), " &
"VSS: (12, 21, 54, 88, 89, 96), " &
"VDD: (13, 22, 55, 91, 97), " &
"ICOC2: (39, 38, 37, 36), " &
"ICOC1: (43, 42, 41, 40), " &
"TEST: 44, " &
"TXD2: 45, " &
"RXD2: 46, " &
"TXD1: 47, " &
"RXD1: 48, " &
"INT: (49, 50, 53, 56, 57, 58, 60, 61), " &
"VSSF: 51, " &
"VDDF: 52, " &
"VPP: 59, " &
"MOSI: 62, " &
"MISO: 63, " &
"VSTBY: 64, " &
"SCK: 65, " &
"SS: 66, " &
"VDDH: 70, " &
"PQB3: 71, " &
"PQB2: 72, " &
"PQB1: 73, " &
"PQB0: 74, " &
"PQA4: 75, " &
"PQA3: 76, " &
"PQA1: 77, " &
"PQA0: 78, " &
"VRL: 79, " &
"VRH: 80, " &
"VSSA: 81, " &
"VDDA: 82, " &
"RESET: 83, " &
"RSTOUT: 84, " &
"PLL_ENABLE: 85, " &
"XTAL: 86, " &
"EXTAL: 87, " &
"CLKOUT: 90, " &
"TCK: 92, " &
"TDI: 93, " &
"TDO: 94, " &
"TMS: 95, " &
"TRST: 98, " &
"DE: 99 ";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_RESET of TRST : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH);
attribute COMPLIANCE_PATTERNS of MMC2114_SIKA256 : entity is
"(TEST, DE) (01)";
attribute INSTRUCTION_LENGTH of MMC2114_SIKA256 : entity is 4;
attribute INSTRUCTION_OPCODE of MMC2114_SIKA256 : entity is
"EXTEST (0000)," &
"SAMPLE (0010)," &
"IDCODE (0001)," &
"CLAMP (1100)," &
"HIGHZ (1001)," &
"ENABLE_MCU_ONCE (0011)," &
"ENTER_SCAN (0100)," &
"TEST_LEAKAGE (0101)," &
"LOCKOUT_RECOVERY (1011)," &
"BYPASS (1111)";
attribute INSTRUCTION_CAPTURE of MMC2114_SIKA256 : entity is "0001";
attribute INSTRUCTION_PRIVATE of MMC2114_SIKA256 : entity is
"ENTER_SCAN, TEST_LEAKAGE ";
attribute IDCODE_REGISTER of MMC2114_SIKA256 : entity is
"0000" & -- version
"010111" & -- manufacturer's use
"0000011110" & -- sequence number
"00000001110" & -- manufacturer identity
"1"; -- 1149.1 requirement
attribute REGISTER_ACCESS of MMC2114_SIKA256 : entity is
"BYPASS (ENABLE_MCU_ONCE,ENTER_SCAN,TEST_LEAKAGE)" ;
attribute REGISTER_ACCESS of MMC2114_SIKA256 : entity is
"JTAG_TFM_CLKDIV[7] (LOCKOUT_RECOVERY)" ;
attribute BOUNDARY_LENGTH of MMC2114_SIKA256 : entity is 200;
attribute BOUNDARY_REGISTER of MMC2114_SIKA256 : entity is
-- num cell port func safe [ccell dis rslt]
"0 (BC_7, PA(7), bidir, X, 1, 1, Z)," &
"1 (BC_2, *, control, 1)," &
"2 (BC_2, *, internal, 0)," &
"3 (BC_2, *, internal, 0)," &
"4 (BC_2, *, internal, 0)," &
"5 (BC_2, *, internal, 0)," &
"6 (BC_2, *, internal, 0)," &
"7 (BC_2, *, internal, 0)," &
"8 (BC_2, *, internal, 0)," &
"9 (BC_2, *, internal, 0)," &
"10 (BC_2, *, internal, 0)," &
"11 (BC_2, *, internal, 0)," &
"12 (BC_2, *, internal, 0)," &
"13 (BC_2, *, internal, 0)," &
"14 (BC_7, CLKOUT, bidir, X, 15, 1, Z)," &
"15 (BC_2, *, control, 1)," &
"16 (BC_2, *, internal, 0)," &
"17 (BC_2, *, internal, 0)," &
"18 (BC_2, *, internal, 0)," &
"19 (BC_2, *, internal, 0)," &
-- num cell port func safe [ccell dis rslt]
"20 (BC_7, RSTOUT, bidir, X, 21, 1, Z)," &
"21 (BC_2, *, control, 1)," &
"22 (BC_2, *, internal, 0)," &
"23 (BC_2, *, internal, 0)," &
"24 (BC_7, RESET, bidir, X, 25, 1, Z)," &
"25 (BC_2, *, control, 1)," &
"26 (BC_2, *, internal, 0)," &
"27 (BC_2, *, internal, 0)," &
"28 (BC_2, *, internal, 0)," &
"29 (BC_2, *, internal, 0)," &
"30 (BC_7, PE(5), bidir, X, 31, 1, Z)," &
"31 (BC_2, *, control, 1)," &
"32 (BC_2, *, internal, 0)," &
"33 (BC_2, *, internal, 0)," &
"34 (BC_2, *, internal, 0)," &
"35 (BC_2, *, internal, 0)," &
"36 (BC_7, PE(6), bidir, X, 37, 1, Z)," &
"37 (BC_2, *, control, 1)," &
"38 (BC_2, *, internal, 0)," &
"39 (BC_2, *, internal, 0)," &
-- num cell port func safe [ccell dis rslt]
"40 (BC_7, PE(7), bidir, X, 41, 1, Z)," &
"41 (BC_2, *, control, 1)," &
"42 (BC_2, *, internal, 0)," &
"43 (BC_2, *, internal, 0)," &
"44 (BC_2, *, internal, 0)," &
"45 (BC_2, *, internal, 0)," &
"46 (BC_7, SS, bidir, X, 47, 1, Z)," &
"47 (BC_2, *, control, 1)," &
"48 (BC_7, SCK, bidir, X, 49, 1, Z)," &
"49 (BC_2, *, control, 1)," &
"50 (BC_7, MISO, bidir, X, 51, 1, Z)," &
"51 (BC_2, *, control, 1)," &
"52 (BC_7, MOSI, bidir, X, 53, 1, Z)," &
"53 (BC_2, *, control, 1)," &
"54 (BC_7, INT(7), bidir, X, 55, 1, Z)," &
"55 (BC_2, *, control, 1)," &
"56 (BC_7, INT(6), bidir, X, 57, 1, Z)," &
"57 (BC_2, *, control, 1)," &
"58 (BC_2, *, internal, 0)," &
"59 (BC_2, *, internal, 0)," &
-- num cell port func safe [ccell dis rslt]
"60 (BC_2, *, internal, 0)," &
"61 (BC_2, *, internal, 0)," &
"62 (BC_7, INT(5), bidir, X, 63, 1, Z)," &
"63 (BC_2, *, control, 1)," &
"64 (BC_2, *, internal, 0)," &
"65 (BC_2, *, internal, 0)," &
"66 (BC_7, INT(4), bidir, X, 67, 1, Z)," &
"67 (BC_2, *, control, 1)," &
"68 (BC_2, *, internal, 0)," &
"69 (BC_2, *, internal, 0)," &
"70 (BC_2, *, internal, 0)," &
"71 (BC_2, *, internal, 0)," &
"72 (BC_7, INT(3), bidir, X, 73, 1, Z)," &
"73 (BC_2, *, control, 1)," &
"74 (BC_2, *, internal, 0)," &
"75 (BC_2, *, internal, 0)," &
"76 (BC_7, INT(2), bidir, X, 77, 1, Z)," &
"77 (BC_2, *, control, 1)," &
"78 (BC_7, INT(1), bidir, X, 79, 1, Z)," &
"79 (BC_2, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"80 (BC_7, INT(0), bidir, X, 81, 1, Z)," &
"81 (BC_2, *, control, 1)," &
"82 (BC_7, RXD1, bidir, X, 83, 1, Z)," &
"83 (BC_2, *, control, 1)," &
"84 (BC_7, TXD1, bidir, X, 85, 1, Z)," &
"85 (BC_2, *, control, 1)," &
"86 (BC_7, RXD2, bidir, X, 87, 1, Z)," &
"87 (BC_2, *, control, 1)," &
"88 (BC_2, *, internal, 0)," &
"89 (BC_2, *, internal, 0)," &
"90 (BC_7, TXD2, bidir, X, 91, 1, Z)," &
"91 (BC_2, *, control, 1)," &
"92 (BC_2, *, internal, 0)," &
"93 (BC_2, *, internal, 0)," &
"94 (BC_7, ICOC1(0), bidir, X, 95, 1, Z)," &
"95 (BC_2, *, control, 1)," &
"96 (BC_2, *, internal, 0)," &
"97 (BC_2, *, internal, 0)," &
"98 (BC_2, *, internal, 0)," &
"99 (BC_2, *, internal, 0)," &
-- num cell port func safe [ccell dis rslt]
"100 (BC_7, ICOC1(1), bidir, X, 101, 1, Z)," &
"101 (BC_2, *, control, 1)," &
"102 (BC_7, ICOC1(2), bidir, X, 103, 1, Z)," &
"103 (BC_2, *, control, 1)," &
"104 (BC_7, ICOC1(3), bidir, X, 105, 1, Z)," &
"105 (BC_2, *, control, 1)," &
"106 (BC_7, ICOC2(0), bidir, X, 107, 1, Z)," &
"107 (BC_2, *, control, 1)," &
"108 (BC_7, ICOC2(1), bidir, X, 109, 1, Z)," &
"109 (BC_2, *, control, 1)," &
"110 (BC_7, ICOC2(2), bidir, X, 111, 1, Z)," &
"111 (BC_2, *, control, 1)," &
"112 (BC_7, ICOC2(3), bidir, X, 113, 1, Z)," &
"113 (BC_2, *, control, 1)," &
"114 (BC_7, PD(0), bidir, X, 115, 1, Z)," &
"115 (BC_2, *, control, 1)," &
"116 (BC_2, *, internal, 0)," &
"117 (BC_2, *, internal, 0)," &
"118 (BC_2, *, internal, 0)," &
"119 (BC_2, *, internal, 0)," &
-- num cell port func safe [ccell dis rslt]
"120 (BC_7, PD(1), bidir, X, 121, 1, Z)," &
"121 (BC_2, *, control, 1)," &
"122 (BC_2, *, internal, 0)," &
"123 (BC_2, *, internal, 0)," &
"124 (BC_7, PD(2), bidir, X, 125, 1, Z)," &
"125 (BC_2, *, control, 1)," &
"126 (BC_7, PD(3), bidir, X, 127, 1, Z)," &
"127 (BC_2, *, control, 1)," &
"128 (BC_7, PD(4), bidir, X, 129, 1, Z)," &
"129 (BC_2, *, control, 1)," &
"130 (BC_7, PD(5), bidir, X, 131, 1, Z)," &
"131 (BC_2, *, control, 1)," &
"132 (BC_7, PD(6), bidir, X, 133, 1, Z)," &
"133 (BC_2, *, control, 1)," &
"134 (BC_7, PD(7), bidir, X, 135, 1, Z)," &
"135 (BC_2, *, control, 1)," &
"136 (BC_7, PC(0), bidir, X, 137, 1, Z)," &
"137 (BC_2, *, control, 1)," &
"138 (BC_7, PC(1), bidir, X, 139, 1, Z)," &
"139 (BC_2, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"140 (BC_7, PC(2), bidir, X, 141, 1, Z)," &
"141 (BC_2, *, control, 1)," &
"142 (BC_7, PC(3), bidir, X, 143, 1, Z)," &
"143 (BC_2, *, control, 1)," &
"144 (BC_7, PC(4), bidir, X, 145, 1, Z)," &
"145 (BC_2, *, control, 1)," &
"146 (BC_7, PC(5), bidir, X, 147, 1, Z)," &
"147 (BC_2, *, control, 1)," &
"148 (BC_7, PC(6), bidir, X, 149, 1, Z)," &
"149 (BC_2, *, control, 1)," &
"150 (BC_2, *, internal, 0)," &
"151 (BC_2, *, internal, 0)," &
"152 (BC_2, *, internal, 0)," &
"153 (BC_2, *, internal, 0)," &
"154 (BC_7, PC(7), bidir, X, 155, 1, Z)," &
"155 (BC_2, *, control, 1)," &
"156 (BC_2, *, internal, 0)," &
"157 (BC_2, *, internal, 0)," &
"158 (BC_7, PB(0), bidir, X, 159, 1, Z)," &
"159 (BC_2, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"160 (BC_2, *, internal, 0)," &
"161 (BC_2, *, internal, 0)," &
"162 (BC_2, *, internal, 0)," &
"163 (BC_2, *, internal, 0)," &
"164 (BC_7, PB(1), bidir, X, 165, 1, Z)," &
"165 (BC_2, *, control, 1)," &
"166 (BC_7, PB(2), bidir, X, 167, 1, Z)," &
"167 (BC_2, *, control, 1)," &
"168 (BC_7, PB(3), bidir, X, 169, 1, Z)," &
"169 (BC_2, *, control, 1)," &
"170 (BC_7, PB(4), bidir, X, 171, 1, Z)," &
"171 (BC_2, *, control, 1)," &
"172 (BC_7, PB(5), bidir, X, 173, 1, Z)," &
"173 (BC_2, *, control, 1)," &
"174 (BC_7, PB(6), bidir, X, 175, 1, Z)," &
"175 (BC_2, *, control, 1)," &
"176 (BC_2, *, internal, 0)," &
"177 (BC_2, *, internal, 0)," &
"178 (BC_2, *, internal, 0)," &
"179 (BC_2, *, internal, 0)," &
-- num cell port func safe [ccell dis rslt]
"180 (BC_7, PB(7), bidir, X, 181, 1, Z)," &
"181 (BC_2, *, control, 1)," &
"182 (BC_2, *, internal, 0)," &
"183 (BC_2, *, internal, 0)," &
"184 (BC_7, PA(0), bidir, X, 185, 1, Z)," &
"185 (BC_2, *, control, 1)," &
"186 (BC_7, PA(1), bidir, X, 187, 1, Z)," &
"187 (BC_2, *, control, 1)," &
"188 (BC_2, *, internal, 0)," &
"189 (BC_2, *, internal, 0)," &
"190 (BC_7, PA(2), bidir, X, 191, 1, Z)," &
"191 (BC_2, *, control, 1)," &
"192 (BC_7, PA(3), bidir, X, 193, 1, Z)," &
"193 (BC_2, *, control, 1)," &
"194 (BC_7, PA(4), bidir, X, 195, 1, Z)," &
"195 (BC_2, *, control, 1)," &
"196 (BC_7, PA(5), bidir, X, 197, 1, Z)," &
"197 (BC_2, *, control, 1)," &
"198 (BC_7, PA(6), bidir, X, 199, 1, Z)," &
"199 (BC_2, *, control, 1)";
end MMC2114_SIKA256;