-- TI TMS320VC5402A 16-Bit 144-pin Fixed-Point DSP's with Boundary Scan --
-------------------------------------------------------------------------------
-- Supported Devices: TMS320VC5402AGGU 144-pin Revision 1.0 --
-------------------------------------------------------------------------------
-- Created by : Texas Instruments Incorporated --
-- Documentation : TMS320VC54x Users Guide --
-- BSDL Revision : 1.0 --
-- BSDL status : Preliminary --
-- Date created : 01/27/2003 --
-- --
-- Initialization Requirements for Boundary Scan Test --
-- -------------------------------------------------- --
-- --
-- The 5410A uses the JTAG port for boundary scan tests, emulation --
-- capability and factory test purposes. To use boundary scan test, --
-- the EMU0 and EMU1/OFF pins must be held high through a rising edge --
-- of the TRST- signal prior to the first scan. This operation --
-- selects the appropriate TAP control for boundary scan. If at any --
-- time during a boundary scan test a rising edge of TRST occurs when --
-- EMU0 or EMU1 are not high, a factory test mode may be selected --
-- preventing boundary scan test from being completed. For this reason, --
-- it is recommended that EMU0 and EMU1/OFF be pulled or driven high at --
-- all times during boundary scan test. --
-- --
-- --
-- Device Pins not Covered by Boundary Scan --
-- ---------------------------------------- --
-- The following pins do not have cells in the boundary register: --
-- EMU0, EMU1/OFF --
-------------------------------------------------------------------------------
-- IMPORTANT NOTICE --
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-- to its products or to discontinue any semiconductor product or service --
-- without notice, and advises its customers to obtain the latest version --
-- of the relevant information to verify, before placing orders, that the --
-- information being relied on is current. --
-- --
-- TI warrants performance of its semiconductor products and related --
-- software to the specifications applicable at the time of sale in --
-- accordance with TI's standard warranty. Testing and other quality control--
-- techniques are utilized to the extent TI deems necessary to support this --
-- warranty. Specific testing of all parameters of each device is not --
-- necessarily performed, except those mandated by government requirements. --
-- --
-- Certain applications using semiconductor devices may involve potential --
-- risks of death, personal injury, or severe property or environmental --
-- damage ("Critical Applications"). --
-- --
-- TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, --
-- OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, --
-- DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. --
-- --
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-- requires the written approval of an appropriate TI officer. Questions --
-- concerning potential risk applications should be directed to TI through --
-- a local SC sales office. --
-- --
-- In order to minimize risks associated with the customer's applications, --
-- adequate design and operating safeguards should be provided by the --
-- customer to minimize inherent or procedural hazards. --
-- --
-- TI assumes no liability for applications assistance, customer product --
-- design, software performance, or infringement of patents or services --
-- described herein. Nor does TI warrant or represent that any license, --
-- either express or implied, is granted under any patent right, copyright, --
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-- relating to any combination, machine, or process in which such --
-- semiconductor products or services might be or are used. --
-- --
-- Copyright (c) 1996, Texas Instruments Incorporated --
-------------------------------------------------------------------------------
entity TMS320VC5402A is
generic (PHYSICAL_PIN_MAP : string := "GGU");
port (HCSN : in bit;
HPI16 : in bit;
HPIENA : in bit;
HBIL : in bit;
HRNW : in bit;
HASN : in bit;
HCNTL : in bit_vector(0 to 1);
HDS1N : in bit;
HDS2N : in bit;
HD : inout bit_vector(0 to 7);
HINTN : out bit;
HRDY : out bit;
BFSX : inout bit_vector(0 to 2);
BDX : out bit_vector(0 to 2);
BFSR : inout bit_vector(0 to 2);
BDR : in bit_vector(0 to 2);
BCLKR : inout bit_vector(0 to 2);
BCLKX : inout bit_vector(0 to 2);
CLKMD : in bit_vector(1 to 3);
NMIN : in bit;
INTN : in bit_vector(0 to 3);
READY : in bit;
RSN : in bit;
MPNMC : in bit;
BION : in bit;
HOLDN : in bit;
A : inout bit_vector(0 to 15);
A16 : out bit;
A17 : out bit;
A18 : out bit;
A19 : out bit;
A20 : out bit;
A21 : out bit;
A22 : out bit;
D : inout bit_vector(0 to 15);
TOUT : out bit;
CLKOUT : out bit;
IAQN : out bit;
MSCN : out bit;
HOLDAN : out bit;
IOSTRBN : out bit;
RNW : out bit;
MSTRBN : out bit;
ISN : out bit;
PSN : out bit;
DSN : out bit;
XF : out bit;
IACKN : out bit;
X2_CLKIN : in bit;
X1 : linkage bit;
EMU1_OFF_NEG : inout bit;
EMU0 : inout bit;
CGND : linkage bit_vector(1 to 10);
DGND : linkage bit_vector(1 to 9);
CVDD : linkage bit_vector(1 to 7);
DVDD : linkage bit_vector(1 to 6);
TCK : in bit;
TDI : in bit;
TDO : out bit;
TMS : in bit;
TRST_NEG : in bit);
use STD_1149_1_1990.all; -- Get standard attributes and definitions
use TI_BIDIR.all; -- Get C54X BIDIR cell attributes
----------------------------------------------------------------------
-- This package type TI_BIDIR must be available to your toolset. --
-- In most cases this text should be placed in a separate file --
-- named 'TI_BIDIR' that can be referenced via the previous --
-- 'use TI_BIDIR.all' statement. --
--
-- package TI_BIDIR is
-- use STD_1149_1_1990.all;
-- constant BC_BIDIR : CELL_INFO;
-- end TI_BIDIR;
--
-- package body TI_BIDIR is
-- constant BC_BIDIR : CELL_INFO :=
-- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PI),
-- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
-- (BIDIR_IN, INTEST, PI), (BIDIR_OUT, INTEST, PI));
-- end TI_BIDIR;
----------------------------------------------------------------------
attribute PIN_MAP of TMS320VC5402A : entity is PHYSICAL_PIN_MAP;
constant GGU : PIN_MAP_STRING :=
--Address and Data
" A:(C6,D6,A5,B5,D5,A4,B4,C4,A3,B3,D4,D2, " &
" D1,E4,E3,E2), " &
" A16:C12, " &
" A17:B13, " &
" A18:B12, " &
" A19:A13, " &
" A20:A12, " &
" A21:A2, " &
" A22:B1, " &
" D:(E11,E10,D13,D12,D11,C13,D10,C10, " &
" B10,A10,D9,C9,B9,D8,C8,B8), " &
--Control Signals
" DSN:H1, PSN:G4, ISN:H2, " &
" READY:G3, RNW:H3, " &
" MSTRBN:H4, IOSTRBN:J1, " &
" HOLDN:K2, HOLDAN:J4, " &
" IAQN:K1, MSCN:J2, " &
--General Purpose I/O
" BION:K3, XF:J3, " &
--Init., Int. and Reset
" IACKN:N9, " &
" NMIN:L9, INTN:(K9,N10,M10,L10), " &
" RSN:E12, MPNMC:L1, " &
--Ocillator Signals
" X1:F10, X2_CLKIN:E13, " &
" CLKOUT:F12, CLKMD:(K10,K11,K12), " &
--Timer Signal
" TOUT:J11, " &
--Buffered Serial Port
" BCLKR:(K4,N2, L4),BCLKX:(N5,N12, K6), " &
" BDR:(K5,M1, M5), BDX:(L8,M13, K8), " &
" BFSR:(M4,M2, N4), BFSX:(M7,N13, N7), " &
--Host Port Interface
" HPIENA:G10, " &
" HD:(M8,M11,J10,F11,A9,A8,C5,D3), " &
" HINTN:M6, HCNTL:(M3,L5), HRNW:G1, " &
" HCSN:G2, HASN:F4, HBIL:M9, " &
" HDS1N:C7, HDS2N:A6, HRDY:L7, " &
" HPI16:K13, " &
--JTAG Signals
" TCK:H13, TDI:H11, TDO:H10, " &
" TMS:G12, TRST_NEG:H12, " &
--Emulation Signals
" EMU0:J12, EMU1_OFF_NEG:J13, " &
--Power and Ground
" CGND:(A1,C2,F2,L3,G13,N1,L6,L11,B11,A7), " &
" DGND:(F3,L13,F13,C11,N3,N8,M12,D7,B2), " &
" CVDD:(E1,F1,G11,N6,N11,B7,C3), " &
" DVDD:(C1,L2,L12,K7,A11,B6) " ;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRST_NEG : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (25.00e6, BOTH);
attribute INSTRUCTION_LENGTH of TMS320VC5402A : entity is 8;
attribute INSTRUCTION_OPCODE of TMS320VC5402A : entity is
"EXTEST (00000000), " &
"BYPASS (11111111), " &
"SAMPLE (00000010), " &
"HIGHZ (00000110) " ;
attribute INSTRUCTION_CAPTURE of TMS320VC5402A : entity is "XXXXXX01";
attribute REGISTER_ACCESS of TMS320VC5402A : entity is
"BOUNDARY (EXTEST, SAMPLE)," &
"BYPASS (BYPASS, HIGHZ) " ;
attribute BOUNDARY_CELLS of TMS320VC5402A : entity is
"BC_1, BC_2, BC_4, BC_BIDIR";
attribute BOUNDARY_LENGTH of TMS320VC5402A : entity is 131;
attribute BOUNDARY_REGISTER of TMS320VC5402A : entity is
"0 (BC_1 ,HCSN ,INPUT ,X ), " &
"1 (BC_1 ,HPI16 ,INPUT ,X ), " &
"2 (BC_1 ,HPIENA ,INPUT ,X ), " &
"3 (BC_1 ,HBIL ,INPUT ,X ), " &
"4 (BC_1 ,HRNW ,INPUT ,X ), " &
"5 (BC_1 ,HASN ,INPUT ,X ), " &
"6 (BC_1 ,HCNTL(0) ,INPUT ,X ), " &
"7 (BC_1 ,HCNTL(1) ,INPUT ,X ), " &
"8 (BC_1 ,HDS1N ,INPUT ,X ), " &
"9 (BC_1 ,HDS2N ,INPUT ,X ), " &
"10 (BC_1 ,* ,CONTROL ,1 ), " &
"11 (BC_1 ,* ,CONTROL ,1 ), " &
"12 (BC_1 ,* ,CONTROL ,1 ), " &
"13 (BC_1 ,* ,CONTROL ,1 ), " &
"14 (BC_1 ,* ,CONTROL ,1 ), " &
"15 (BC_1 ,* ,CONTROL ,1 ), " &
"16 (BC_1 ,* ,CONTROL ,1 ), " &
"17 (BC_1 ,* ,CONTROL ,1 ), " &
"18 (BC_BIDIR ,HD(0) ,BIDIR ,X ,10 ,1 ,Z), " &
"19 (BC_BIDIR ,HD(1) ,BIDIR ,X ,11 ,1 ,Z), " &
"20 (BC_BIDIR ,HD(2) ,BIDIR ,X ,12 ,1 ,Z), " &
"21 (BC_BIDIR ,HD(3) ,BIDIR ,X ,13 ,1 ,Z), " &
"22 (BC_BIDIR ,HD(4) ,BIDIR ,X ,14 ,1 ,Z), " &
"23 (BC_BIDIR ,HD(5) ,BIDIR ,X ,15 ,1 ,Z), " &
"24 (BC_BIDIR ,HD(6) ,BIDIR ,X ,16 ,1 ,Z), " &
"25 (BC_BIDIR ,HD(7) ,BIDIR ,X ,17 ,1 ,Z), " &
"26 (BC_1 ,HINTN ,OUTPUT3 ,X ,76 ,1 ,Z), " &
"27 (BC_1 ,HRDY ,OUTPUT3 ,X ,76 ,1 ,Z), " &
"28 (BC_1 ,* ,CONTROL ,1 ), " &
"29 (BC_1 ,* ,CONTROL ,1 ), " &
"30 (BC_1 ,* ,CONTROL ,1 ), " &
"31 (BC_1 ,* ,CONTROL ,1 ), " &
"32 (BC_1 ,* ,CONTROL ,1 ), " &
"33 (BC_BIDIR ,BFSX(2) ,BIDIR ,X ,30 ,1 ,Z), " &
"34 (BC_1 ,BDX(2) ,OUTPUT3 ,X ,29 ,1 ,Z), " &
"35 (BC_BIDIR ,BFSR(2) ,BIDIR ,X ,32 ,1 ,Z), " &
"36 (BC_1 ,BDR(2) ,INPUT ,X ), " &
"37 (BC_BIDIR ,BCLKR(2) ,BIDIR ,X ,28 ,1 ,Z), " &
"38 (BC_BIDIR ,BCLKX(2) ,BIDIR ,X ,31 ,1 ,Z), " &
"39 (BC_1 ,* ,CONTROL ,1 ), " &
"40 (BC_1 ,* ,CONTROL ,1 ), " &
"41 (BC_1 ,* ,CONTROL ,1 ), " &
"42 (BC_1 ,* ,CONTROL ,1 ), " &
"43 (BC_1 ,* ,CONTROL ,1 ), " &
"44 (BC_BIDIR ,BFSX(1) ,BIDIR ,X ,41 ,1 ,Z), " &
"45 (BC_1 ,BDX(1) ,OUTPUT3 ,X ,40 ,1 ,Z), " &
"46 (BC_BIDIR ,BFSR(1) ,BIDIR ,X ,43 ,1 ,Z), " &
"47 (BC_1 ,BDR(1) ,INPUT ,X ), " &
"48 (BC_BIDIR ,BCLKR(1) ,BIDIR ,X ,39 ,1 ,Z), " &
"49 (BC_BIDIR ,BCLKX(1) ,BIDIR ,X ,42 ,1 ,Z), " &
"50 (BC_1 ,* ,CONTROL ,1 ), " &
"51 (BC_1 ,* ,CONTROL ,1 ), " &
"52 (BC_1 ,* ,CONTROL ,1 ), " &
"53 (BC_1 ,* ,CONTROL ,1 ), " &
"54 (BC_1 ,* ,CONTROL ,1 ), " &
"55 (BC_BIDIR ,BFSX(0) ,BIDIR ,X ,52 ,1 ,Z), " &
"56 (BC_1 ,BDX(0) ,OUTPUT3 ,X ,51 ,1 ,Z), " &
"57 (BC_BIDIR ,BFSR(0) ,BIDIR ,X ,54 ,1 ,Z), " &
"58 (BC_1 ,BDR(0) ,INPUT ,X ), " &
"59 (BC_BIDIR ,BCLKR(0) ,BIDIR ,X ,50 ,1 ,Z), " &
"60 (BC_BIDIR ,BCLKX(0) ,BIDIR ,X ,53 ,1 ,Z), " &
"61 (BC_1 ,CLKMD(3) ,INPUT ,X ), " &
"62 (BC_1 ,CLKMD(2) ,INPUT ,X ), " &
"63 (BC_1 ,CLKMD(1) ,INPUT ,X ), " &
"64 (BC_1 ,NMIN ,INPUT ,X ), " &
"65 (BC_1 ,INTN(3) ,INPUT ,X ), " &
"66 (BC_1 ,INTN(2) ,INPUT ,X ), " &
"67 (BC_1 ,INTN(1) ,INPUT ,X ), " &
"68 (BC_1 ,INTN(0) ,INPUT ,X ), " &
"69 (BC_1 ,READY ,INPUT ,X ), " &
"70 (BC_1 ,RSN ,INPUT ,X ), " &
"71 (BC_1 ,MPNMC ,INPUT ,X ), " &
"72 (BC_1 ,BION ,INPUT ,X ), " &
"73 (BC_1 ,* ,CONTROL ,1 ), " &
"74 (BC_1 ,* ,CONTROL ,1 ), " &
"75 (BC_1 ,HOLDN ,INPUT ,X ), " &
"76 (BC_1 ,* ,CONTROL ,1 ), " &
"77 (BC_1 ,* ,CONTROL ,1 ), " &
"78 (BC_1 ,A16 ,OUTPUT3 ,X ,74 ,1 ,Z), " &
"79 (BC_1 ,A17 ,OUTPUT3 ,X ,74 ,1 ,Z), " &
"80 (BC_1 ,A18 ,OUTPUT3 ,X ,74 ,1 ,Z), " &
"81 (BC_1 ,A19 ,OUTPUT3 ,X ,74 ,1 ,Z), " &
"82 (BC_1 ,A20 ,OUTPUT3 ,X ,74 ,1 ,Z), " &
"83 (BC_1 ,A21 ,OUTPUT3 ,X ,74 ,1 ,Z), " &
"84 (BC_1 ,A22 ,OUTPUT3 ,X ,74 ,1 ,Z), " &
"85 (BC_BIDIR ,D(0) ,BIDIR ,X ,77 ,1 ,Z), " &
"86 (BC_BIDIR ,D(1) ,BIDIR ,X ,77 ,1 ,Z), " &
"87 (BC_BIDIR ,D(2) ,BIDIR ,X ,77 ,1 ,Z), " &
"88 (BC_BIDIR ,D(3) ,BIDIR ,X ,77 ,1 ,Z), " &
"89 (BC_BIDIR ,D(4) ,BIDIR ,X ,77 ,1 ,Z), " &
"90 (BC_BIDIR ,D(5) ,BIDIR ,X ,77 ,1 ,Z), " &
"91 (BC_BIDIR ,D(6) ,BIDIR ,X ,77 ,1 ,Z), " &
"92 (BC_BIDIR ,D(7) ,BIDIR ,X ,77 ,1 ,Z), " &
"93 (BC_BIDIR ,D(8) ,BIDIR ,X ,77 ,1 ,Z), " &
"94 (BC_BIDIR ,D(9) ,BIDIR ,X ,77 ,1 ,Z), " &
"95 (BC_BIDIR ,D(10) ,BIDIR ,X ,77 ,1 ,Z), " &
"96 (BC_BIDIR ,D(11) ,BIDIR ,X ,77 ,1 ,Z), " &
"97 (BC_BIDIR ,D(12) ,BIDIR ,X ,77 ,1 ,Z), " &
"98 (BC_BIDIR ,D(13) ,BIDIR ,X ,77 ,1 ,Z), " &
"99 (BC_BIDIR ,D(14) ,BIDIR ,X ,77 ,1 ,Z), " &
"100 (BC_BIDIR ,D(15) ,BIDIR ,X ,77 ,1 ,Z), " &
"101 (BC_1 ,TOUT ,OUTPUT3 ,X ,76 ,1 ,Z), " &
"102 (BC_1 ,CLKOUT ,OUTPUT3 ,X ,76 ,1 ,Z), " &
"103 (BC_1 ,X2_CLKIN ,INPUT ,X ), " &
"104 (BC_1 ,IAQN ,OUTPUT3 ,X ,76 ,1 ,Z), " &
"105 (BC_1 ,MSCN ,OUTPUT3 ,X ,76 ,1 ,Z), " &
"106 (BC_1 ,HOLDAN ,OUTPUT3 ,X ,76 ,1 ,Z), " &
"107 (BC_1 ,IOSTRBN ,OUTPUT3 ,X ,74 ,1 ,Z), " &
"108 (BC_1 ,RNW ,OUTPUT3 ,X ,74 ,1 ,Z), " &
"109 (BC_1 ,MSTRBN ,OUTPUT3 ,X ,74 ,1 ,Z), " &
"110 (BC_1 ,ISN ,OUTPUT3 ,X ,74 ,1 ,Z), " &
"111 (BC_1 ,PSN ,OUTPUT3 ,X ,74 ,1 ,Z), " &
"112 (BC_1 ,DSN ,OUTPUT3 ,X ,74 ,1 ,Z), " &
"113 (BC_1 ,XF ,OUTPUT3 ,X ,76 ,1 ,Z), " &
"114 (BC_1 ,IACKN ,OUTPUT3 ,X ,76 ,1 ,Z), " &
"115 (BC_BIDIR ,A(0) ,BIDIR ,X ,73 ,1 ,Z), " &
"116 (BC_BIDIR ,A(1) ,BIDIR ,X ,73 ,1 ,Z), " &
"117 (BC_BIDIR ,A(2) ,BIDIR ,X ,73 ,1 ,Z), " &
"118 (BC_BIDIR ,A(3) ,BIDIR ,X ,73 ,1 ,Z), " &
"119 (BC_BIDIR ,A(4) ,BIDIR ,X ,73 ,1 ,Z), " &
"120 (BC_BIDIR ,A(5) ,BIDIR ,X ,73 ,1 ,Z), " &
"121 (BC_BIDIR ,A(6) ,BIDIR ,X ,73 ,1 ,Z), " &
"122 (BC_BIDIR ,A(7) ,BIDIR ,X ,73 ,1 ,Z), " &
"123 (BC_BIDIR ,A(8) ,BIDIR ,X ,73 ,1 ,Z), " &
"124 (BC_BIDIR ,A(9) ,BIDIR ,X ,73 ,1 ,Z), " &
"125 (BC_BIDIR ,A(10) ,BIDIR ,X ,73 ,1 ,Z), " &
"126 (BC_BIDIR ,A(11) ,BIDIR ,X ,73 ,1 ,Z), " &
"127 (BC_BIDIR ,A(12) ,BIDIR ,X ,73 ,1 ,Z), " &
"128 (BC_BIDIR ,A(13) ,BIDIR ,X ,73 ,1 ,Z), " &
"129 (BC_BIDIR ,A(14) ,BIDIR ,X ,73 ,1 ,Z), " &
"130 (BC_BIDIR ,A(15) ,BIDIR ,X ,73 ,1 ,Z) " ;
end TMS320VC5402A;