----------------------------------------------------------------------------------
--
-- BSDL file for design DS26522
--
-- File Name : DS26522_D1_SCT_BSDL.TXT
--
-- Created by Synopsys Version 2000.11 (Nov 27, 2000)
-- Modified by Maxim Integrated Products (T. Zagumny)
--
-- Company : Maxim Integrated Products
-- Documentation : DS26521 datasheet
-- BSDL Revision : 1.1
-- Date : 4/2/2009 Thursday April 2, 2009
--
-- Device : DS26522 RevA
-- Package : 144-pin CSBGA
--
-- IMPORTANT NOTICE
-- Maxim Integrated Products customers are advised to obtain the latest version
-- of device specifications before relying on any published information contained
-- herein. Maxim Integrated Products assumes no responsibility or liability
-- arising out of the application of any information described herein.
--
-- IMPORTANT NOTICE ABOUT THE REVISION
--
-- Maxim Integrated Products customers are advised to check the revision of the
-- device they will be using. All the codes for the device revisions are
-- herein this BSDL file.
--
-- The characters "/", "(", ")" and "*" have been removed from signal names for
-- compatibility with BSDL file format.
--
-- --------------------------------------------------------------------------------
entity DS26522_D1 is
-- This section identifies the default device package selected.
generic (PHYSICAL_Pin_MAP: string:= "CSBGA_144");
-- This section declares all the ports in the design.
port (
A0 : in bit;
A1 : in bit;
A12 : in bit;
A2 : in bit;
A3 : in bit;
A4 : in bit;
A5 : in bit;
A6 : in bit;
A7 : in bit;
A8 : in bit;
BTS : in bit;
CSB1_B : in bit;
JTCLK : in bit;
JTDI1 : in bit;
JTMS : in bit;
JTRST : in bit;
MCLK : in bit;
RDB_DSB : in bit;
RESET_B : in bit;
RSYSCLK1 : in bit;
SPI_SEL : in bit;
TCLK1 : in bit;
TSER1 : in bit;
TSYSCLK1 : in bit;
TXEN1_B : in bit;
WRB_RWB : in bit;
D0 : inout bit;
D1 : inout bit;
D2 : inout bit;
D3 : inout bit;
D4 : inout bit;
D5 : inout bit;
D6 : inout bit;
D7 : inout bit;
RCHBLK_CLK1 : inout bit;
RCLK1 : inout bit;
REFCLKIO1 : inout bit;
RM_RFSYNC1 : inout bit;
RSIG1 : inout bit;
RSYNC1 : inout bit;
TCHBLK_CLK1 : inout bit;
TSIG1 : inout bit;
TSSYNCIO1 : inout bit;
TSYNC1 : inout bit;
AL_RSIGF_FLOS1 : out bit;
BPCLK1 : out bit;
INT_B : out bit;
JTDO1 : out bit;
RLF_LTC1 : out bit;
RSER1 : out bit;
RRING1 : linkage bit_vector (0 to 1);
RTIP1 : linkage bit_vector (0 to 1);
TRING1 : linkage bit_vector (0 to 1);
TTIP1 : linkage bit_vector (0 to 1);
VDD1 : linkage bit_vector (1 to 4);
VDD1C : linkage bit;
VDD1R : linkage bit_vector (1 to 5);
VDD1T : linkage bit_vector (1 to 2);
VSS1 : linkage bit_vector (1 to 6);
VSS1C : linkage bit_vector (1 to 2);
VSS1R : linkage bit_vector (1 to 5);
VSS1T : linkage bit_vector (1 to 2)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of DS26522_D1: entity is "STD_1149_1_1993";
attribute Pin_MAP of DS26522_D1: entity is PHYSICAL_Pin_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant CSBGA_144: Pin_MAP_STRinG :=
"A0 : J2," &
"A1 : J1," &
"A12 : E1," &
"A2 : H2," &
"A3 : H1," &
"A4 : G2," &
"A5 : G1," &
"A6 : F2," &
"A7 : F1," &
"A8 : E2," &
"BTS : E5," &
"CSB1_B : L4," &
"JTCLK : M6," &
"JTDI1 : L5," &
"JTMS : M5," &
"JTRST : L6," &
"MCLK : M9," &
"RDB_DSB : H3," &
"RESET_B : K3," &
"RSYSCLK1 : J8," &
"SPI_SEL : D7," &
"TCLK1 : G8," &
"TSER1 : F8," &
"TSYSCLK1 : H8," &
"TXEN1_B : E6," &
"WRB_RWB : J3," &
"D0 : M3," &
"D1 : L3," &
"D2 : M2," &
"D3 : M1," &
"D4 : L2," &
"D5 : L1," &
"D6 : K2," &
"D7 : K1," &
"RCHBLK_CLK1 : J6," &
"RCLK1 : L8," &
"REFCLKIO1 : K8," &
"RM_RFSYNC1 : G6," &
"RSIG1 : H6," &
"RSYNC1 : K7," &
"TCHBLK_CLK1 : F7," &
"TSIG1 : H7," &
"TSSYNCIO1 : G7," &
"TSYNC1 : J7," &
"AL_RSIGF_FLOS1 : F6," &
"BPCLK1 : K6," &
"INT_B : K4," &
"JTDO1 : M7," &
"RLF_LTC1 : J5," &
"RSER1 : K5," &
"RRING1 : (A1, B1)," &
"RTIP1 : (A2, B2)," &
"TRING1 : (A4, B4)," &
"TTIP1 : (A5, B5)," &
"VDD1 : (G3, G4, H4, J4)," &
"VDD1C : H5," &
"VDD1R : (D1, D2, D3, D4, D5)," &
"VDD1T : (A6, B6)," &
"VSS1 : (C6, D6, E3, E4, F3, F4)," &
"VSS1C : (F5, G5)," &
"VSS1R : (C1, C2, C3, C4, C5)," &
"VSS1T : (A3, B3)";
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of JTCLK: signal is (10.0e6, BOTH);
attribute TAP_SCAN_in of JTDI1: signal is true;
attribute TAP_SCAN_MODE of JTMS : signal is true;
attribute TAP_SCAN_OUT of JTDO1: signal is true;
attribute TAP_SCAN_RESET of JTRST: signal is true;
-- Specifies the number of bits in the instruction register.
attribute inSTRUCTION_LENGTH of DS26522_D1: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute inSTRUCTION_OPCODE of DS26522_D1: entity is
"BYPASS (111)," &
"EXTEST (000)," &
"SAMPLE (010)," &
"CLAMP (011)," &
"USER1 (100)," &
"USER2 (101)," &
"USER3 (110)," &
"IDCODE (001)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute inSTRUCTION_CAPTURE of DS26522_D1: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of DS26522_D1: entity is
"0000" & -- 4-bit version number
"0000000010001000" & -- 16-bit part number
"00010100001" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of DS26522_D1: entity is
"BYPASS (BYPASS, CLAMP, USER1, USER2, USER3)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"DEVICE_ID (IDCODE)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of DS26522_D1: entity is 86;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of DS26522_D1: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"85 (BC_4, SPI_SEL, observe_only, X), " &
"84 (BC_4, BTS, observe_only, X), " &
"83 (BC_4, TXEN1_B, observe_only, X), " &
"82 (BC_4, A12, observe_only, X), " &
"81 (BC_4, A8, observe_only, X), " &
"80 (BC_4, A7, observe_only, X), " &
"79 (BC_4, A6, observe_only, X), " &
"78 (BC_4, A5, observe_only, X), " &
"77 (BC_4, A4, observe_only, X), " &
"76 (BC_4, A3, observe_only, X), " &
"75 (BC_4, A2, observe_only, X), " &
"74 (BC_4, A1, observe_only, X), " &
"73 (BC_4, A0, observe_only, X), " &
"72 (BC_4, D7, observe_only, X), " &
"71 (BC_2, D7, output3, X, 70, 1, Z), " &
"70 (BC_2, *, controlr, 1), " &
"69 (BC_4, D6, observe_only, X), " &
"68 (BC_2, D6, output3, X, 67, 1, Z), " &
"67 (BC_2, *, controlr, 1), " &
"66 (BC_4, D5, observe_only, X), " &
"65 (BC_2, D5, output3, X, 64, 1, Z), " &
"64 (BC_2, *, controlr, 1), " &
"63 (BC_4, D4, observe_only, X), " &
"62 (BC_2, D4, output3, X, 61, 1, Z), " &
"61 (BC_2, *, controlr, 1), " &
"60 (BC_4, D3, observe_only, X), " &
"59 (BC_2, D3, output3, X, 58, 1, Z), " &
"58 (BC_2, *, controlr, 1), " &
"57 (BC_4, D2, observe_only, X), " &
"56 (BC_2, D2, output3, X, 55, 1, Z), " &
"55 (BC_2, *, controlr, 1), " &
"54 (BC_4, D1, observe_only, X), " &
"53 (BC_2, D1, output3, X, 52, 1, Z), " &
"52 (BC_2, *, controlr, 1), " &
"51 (BC_4, D0, observe_only, X), " &
"50 (BC_2, D0, output3, X, 49, 1, Z), " &
"49 (BC_2, *, controlr, 1), " &
"48 (BC_4, CSB1_B, observe_only, X), " &
"47 (BC_4, RDB_DSB, observe_only, X), " &
"46 (BC_4, WRB_RWB, observe_only, X), " &
"45 (BC_2, INT_B, output3, X, 44, 1, PULL1)," &
"44 (BC_2, *, controlr, 1), " &
"43 (BC_4, RESET_B, observe_only, X), " &
"42 (BC_4, MCLK, observe_only, X), " &
"41 (BC_4, REFCLKIO1, observe_only, X), " &
"40 (BC_2, REFCLKIO1, output3, X, 39, 1, Z), " &
"39 (BC_2, *, controlr, 1), " &
"38 (BC_2, BPCLK1, output3, X, 37, 1, Z), " &
"37 (BC_2, *, controlr, 1), " &
"36 (BC_4, RCHBLK_CLK1, observe_only, X), " &
"35 (BC_2, RCHBLK_CLK1, output3, X, 34, 1, Z), " &
"34 (BC_2, *, controlr, 1), " &
"33 (BC_2, RLF_LTC1, output3, X, 32, 1, Z), " &
"32 (BC_2, *, controlr, 1), " &
"31 (BC_2, AL_RSIGF_FLOS1, output3, X, 30, 1, Z), " &
"30 (BC_2, *, controlr, 1), " &
"29 (BC_4, RSIG1, observe_only, X), " &
"28 (BC_2, RSIG1, output3, X, 27, 1, Z), " &
"27 (BC_2, *, controlr, 1), " &
"26 (BC_4, RM_RFSYNC1, observe_only, X), " &
"25 (BC_2, RM_RFSYNC1, output3, X, 24, 1, Z), " &
"24 (BC_2, *, controlr, 1), " &
"23 (BC_4, RSYNC1, observe_only, X), " &
"22 (BC_2, RSYNC1, output3, X, 21, 1, Z), " &
"21 (BC_2, *, controlr, 1), " &
"20 (BC_4, RSYSCLK1, observe_only, X), " &
"19 (BC_4, RCLK1, observe_only, X), " &
"18 (BC_2, RCLK1, output3, X, 17, 1, Z), " &
"17 (BC_2, *, controlr, 1), " &
"16 (BC_2, RSER1, output3, X, 15, 1, Z), " &
"15 (BC_2, *, controlr, 1), " &
"14 (BC_4, TCHBLK_CLK1, observe_only, X), " &
"13 (BC_2, TCHBLK_CLK1, output3, X, 12, 1, Z), " &
"12 (BC_2, *, controlr, 1), " &
"11 (BC_4, TSIG1, observe_only, X), " &
"10 (BC_2, TSIG1, output3, X, 9, 1, Z), " &
"9 (BC_2, *, controlr, 1), " &
"8 (BC_4, TSSYNCIO1, observe_only, X), " &
"7 (BC_2, TSSYNCIO1, output3, X, 6, 1, Z), " &
"6 (BC_2, *, controlr, 1), " &
"5 (BC_4, TSYNC1, observe_only, X), " &
"4 (BC_2, TSYNC1, output3, X, 3, 1, Z), " &
"3 (BC_2, *, controlr, 1), " &
"2 (BC_4, TSYSCLK1, observe_only, X), " &
"1 (BC_4, TCLK1, observe_only, X), " &
"0 (BC_4, TSER1, observe_only, X) ";
end DS26522_D1;
