-------------------------------------------------------------------------------
-- TI TMS320VC5420 16-Bit 144-pin Fixed-Point DSP's with Boundary Scan --
-------------------------------------------------------------------------------
-- Supported Devices: TMS320VC5420 144-pin Revision 1.5 and higher --
-------------------------------------------------------------------------------
-- --
-- This file contains the boundary scan description --
-- of CPU A of the 5420 only. --
-- --
-------------------------------------------------------------------------------
-- Created by : Texas Instruments Incorporated --
-- Documentation : TMS320VC54x Users Guide --
-- BSDL Revision : 3.0 - BSDL split by core to implement bypass properly --
-- 2.0 - EXTEST support added --
-- - XIO pin added to boundary register --
-- - Pin name A_TDO changed to TDO --
-- - Pin name B_TDO changed to TEST --
-- - EMU0/1 compliance condition changed --
-- - Pin name HCORE changed to SELA_B --
-- 1.0 - Original --
-- --
-- BSDL status : Preliminary --
-- Date created : 09/01/99 --
-------------------------------------------------------------------------------
-- *** NOTICE *** --
-- --
-- See the Design Warning located at the end of this file. --
-- --
-------------------------------------------------------------------------------
-- --
-- IMPORTANT NOTICE --
-- Texas Instruments Incorporated (TI) reserves the right to make changes --
-- to its products or to discontinue any semiconductor product or service --
-- without notice, and advises its customers to obtain the latest version --
-- of the relevant information to verify, before placing orders, that the --
-- information being relied on is current. --
-- --
-- TI warrants performance of its semiconductor products and related --
-- software to the specifications applicable at the time of sale in --
-- accordance with TI's standard warranty. Testing and other quality control--
-- techniques are utilized to the extent TI deems necessary to support this --
-- warranty. Specific testing of all parameters of each device is not --
-- necessarily performed, except those mandated by government requirements. --
-- --
-- Certain applications using semiconductor devices may involve potential --
-- risks of death, personal injury, or severe property or environmental --
-- damage ("Critical Applications"). --
-- --
-- TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, --
-- OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, --
-- DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. --
-- --
-- Inclusion of TI products in such applications is understood to be fully --
-- at the risk of the customer. Use of TI products in such applications --
-- requires the written approval of an appropriate TI officer. Questions --
-- concerning potential risk applications should be directed to TI through --
-- a local SC sales office. --
-- --
-- In order to minimize risks associated with the customer's applications, --
-- adequate design and operating safeguards should be provided by the --
-- customer to minimize inherent or procedural hazards. --
-- --
-- TI assumes no liability for applications assistance, customer product --
-- design, software performance, or infringement of patents or services --
-- described herein. Nor does TI warrant or represent that any license, --
-- either express or implied, is granted under any patent right, copyright, --
-- mask work right, or other intellectual property right of TI covering or --
-- relating to any combination, machine, or process in which such --
-- semiconductor products or services might be or are used. --
-- --
-- Copyright (c) 1996, Texas Instruments Incorporated --
-------------------------------------------------------------------------------
entity TMS320VC5420_cpu_A is
generic (PHYSICAL_PIN_MAP : string := "PGE");
port (HA : in bit_vector(0 to 17); -- muxed parallel/HPI address bus
HD : in bit_vector(0 to 15); -- muxed parallel/HPI data bus
A_BCLKR0 : in bit;
A_BCLKR1 : in bit;
A_BCLKR2 : in bit;
A_BCLKX0 : in bit;
A_BCLKX1 : in bit;
A_BCLKX2 : in bit;
A_BDR0 : in bit;
A_BDR1 : in bit;
A_BDR2 : in bit;
A_BDX0 : in bit;
A_BDX1 : in bit;
A_BDX2 : in bit;
A_BFSR0 : in bit;
A_BFSR1 : in bit;
A_BFSR2 : in bit;
A_BFSX0 : in bit;
A_BFSX1 : in bit;
A_BFSX2 : in bit;
A_CLKOUT : in bit;
A_GPIO0 : in bit;
A_GPIO1 : in bit;
A_GPIO2 : in bit;
A_GPIO3 : in bit;
A_INT0 : in bit;
A_INT1 : in bit;
A_NMI : in bit;
A_RS : in bit;
A_XF : in bit;
XIO : in bit;
SELA_B : in bit;
HCS : in bit;
HDS1 : in bit;
HDS2 : in bit;
HMODE : in bit;
HPIRS : in bit;
HRDY : in bit;
HRNW : in bit;
TMS : in bit;
TCK : in bit;
TDI : in bit;
TDO : out bit;
TRST : in bit;
EMU0 : in bit;
EMU1 : in bit;
CLKIN : in bit;
TEST : linkage bit;
NC : linkage bit;
VCO : linkage bit;
CVDD : linkage bit_vector(1 to 4);
DVDD : linkage bit_vector(1 to 3);
VSS : linkage bit_vector(1 to 9);
AVDD : linkage bit;
VSSA : linkage bit);
use STD_1149_1_1994.all; -- Get standard attributes and definitions
attribute COMPONENT_CONFORMANCE of TMS320VC5420_cpu_A: entity is "STD_1149_1_1993";
attribute PIN_MAP of TMS320VC5420_cpu_A : entity is PHYSICAL_PIN_MAP;
constant GGU : PIN_MAP_STRING :=
" HA:(C02,C10,N10,M10,B11,D10,A12,A13, "&
" B01,D04,N13,M13,K10,K11,B12,B13,C12,C13), "&
" HD:(A02,D03,A10,B10,B03,C03,A03,A01, "&
" N11,M11,L11,N12,L04,K04,M03,N02), "&
" A_BFSR2 : A04, " &
" CLKIN : A06, " &
" AVDD : A07, " &
" A_BDX2 : B04, " &
" A_BFSX2 : C04, " &
" A_BCLKR2 : C05, " &
" HRDY : C06, " &
" VSSA : C07, " &
" A_NMI : D01, " &
" A_INT1 : D02, " &
" A_BDR2 : D05, " &
" A_BCLKX2 : D06, " &
" NC : D07, " &
" A_RS : E01, " &
" A_GPIO1 : E02, " &
" A_GPIO2 : E03, " &
" A_GPIO3 : E04, " &
" A_GPIO0 : F04, " &
" A_BDR1 : G01, " &
" A_BFSR1 : G02, " &
" A_BCLKR1 : G03, " &
" A_BFSX1 : G04, " &
" A_BDX1 : H03, " &
" A_BCLKX1 : H04, " &
" TEST : H10, " &
" A_XF : J01, " &
" A_CLKOUT : J02, " &
" VCO : J03, " &
" TCK : J04, " &
" XIO : J13, " &
" TMS : K01, " &
" TDI : K02, " &
" TRST : K03, " &
" A_BCLKR0 : K05, " &
" A_BDX0 : K06, " &
" HRNW : K09, " &
" HPIRS : K12, " &
" HMODE : K13, " &
" EMU1 : L01, " &
" A_INT0 : L03, " &
" A_BFSX0 : L05, " &
" A_BCLKX0 : L06, " &
" SELA_B : L10, " &
" EMU0 : M01, " &
" TDO : M02, " &
" A_BFSR0 : M04, " &
" HCS : M06, " &
" HDS1 : M07, " &
" A_BDR0 : N04, " &
" HDS2 : N06, " &
" VSS: (B02,B05,B07,B09,C11,F02,F03,F13,G13), "&
" CVDD:(A05,A09,F01,F12), "&
" DVDD:(A11,B06,C01)" ;
-- *********************************************************
constant PGE : PIN_MAP_STRING :=
" HA:(3,114,65,66,111,113,110,109, "&
" 2,5,73,74,77,78,108,107,105,104), "&
" HD:(143,6,116,115,141,142,140,1, "&
" 68,69,70,71,42,41,39,38), "&
" A_BFSR2 :137, " &
" CLKIN :129, " &
" AVDD :126, " &
" A_BDX2 :138, " &
" A_BFSX2 :139, " &
" A_BCLKR2 :135, " &
" HRDY :131, " &
" VSSA :127, " &
" A_NMI :8, " &
" A_INT1 :7, " &
" A_BDR2 :136, " &
" A_BCLKX2 :132, " &
" NC :128, " &
" A_RS :12, " &
" A_GPIO1 :11, " &
" A_GPIO2 :10, " &
" A_GPIO3 :9, " &
" A_GPIO0 :13, " &
" A_BDR1 :18, " &
" A_BFSR1 :17, " &
" A_BCLKR1 :19, " &
" A_BFSX1 :20, " &
" A_BDX1 :23, " &
" A_BCLKX1 :24, " &
" TEST :85, " &
" A_XF :25, " &
" A_CLKOUT :26, " &
" VCO :27, " &
" TCK :28, " &
" XIO :84, " &
" TMS :29, " &
" TDI :30, " &
" TRST :31, " &
" A_BCLKR0 :45, " &
" A_BDX0 :49, " &
" HRNW :64, " &
" HPIRS :79, " &
" HMODE :80, " &
" EMU1 :32, " &
" A_INT0 :34, " &
" A_BFSX0 :46, " &
" A_BCLKX0 :50, " &
" SELA_B :67, " &
" EMU0 :35, " &
" TDO :36, " &
" A_BFSR0 :43, " &
" HCS :51, " &
" HDS1 :53, " &
" A_BDR0 :44, " &
" HDS2 :52, " &
" VSS: (14,15,22,37,40,47,57,62,72), "&
" CVDD:(16,21,48,61), "&
" DVDD:(4,33,56)";
-- *********************************************************
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRST : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (25.00e6, BOTH);
attribute COMPLIANCE_PATTERNS of TMS320VC5420_cpu_A : entity is "(EMU1,EMU0)(11)";
attribute INSTRUCTION_LENGTH of TMS320VC5420_cpu_A : entity is 8;
attribute INSTRUCTION_OPCODE of TMS320VC5420_cpu_A : entity is
"EXTEST (00000000), " &
"BYPASS (11111111), " &
"SAMPLE (00000011) " ;
attribute INSTRUCTION_CAPTURE of TMS320VC5420_cpu_A : entity is "XXXXXX01";
attribute REGISTER_ACCESS of TMS320VC5420_cpu_A : entity is
"BOUNDARY (EXTEST, SAMPLE)," &
"BYPASS (BYPASS) " ;
attribute BOUNDARY_LENGTH of TMS320VC5420_cpu_A: entity is 72;
attribute BOUNDARY_REGISTER of TMS320VC5420_cpu_A: entity is
"0 (BC_2, A_GPIO0 ,INPUT, X), " &
"1 (BC_2, A_GPIO1 ,INPUT, X), " &
"2 (BC_2, A_GPIO2 ,INPUT, X), " &
"3 (BC_2, A_GPIO3 ,INPUT, X), " &
"4 (BC_2, A_INT1 ,INPUT, X), " &
"5 (BC_2, A_INT0 ,INPUT, X), " &
"6 (BC_2, A_XF ,INPUT, X), " &
"7 (BC_2, A_NMI ,INPUT, X), " &
"8 (BC_2, A_RS ,INPUT, X), " &
"9 (BC_2, A_CLKOUT ,INPUT, X), " &
"10 (BC_2, A_BFSX2 ,INPUT, X), " &
"11 (BC_2, A_BFSR2 ,INPUT, X), " &
"12 (BC_2, A_BDX2 ,INPUT, X), " &
"13 (BC_2, A_BDR2 ,INPUT, X), " &
"14 (BC_2, A_BCLKX2 ,INPUT, X), " &
"15 (BC_2, A_BCLKR2 ,INPUT, X), " &
"16 (BC_2, A_BFSX1 ,INPUT, X), " &
"17 (BC_2, A_BFSR1 ,INPUT, X), " &
"18 (BC_2, A_BDX1 ,INPUT, X), " &
"19 (BC_2, A_BDR1 ,INPUT, X), " &
"20 (BC_2, A_BCLKX1 ,INPUT, X), " &
"21 (BC_2, A_BCLKR1 ,INPUT, X), " &
"22 (BC_2, A_BFSX0 ,INPUT, X), " &
"23 (BC_2, A_BFSR0 ,INPUT, X), " &
"24 (BC_2, A_BDX0 ,INPUT, X), " &
"25 (BC_2, A_BDR0 ,INPUT, X), " &
"26 (BC_2, A_BCLKX0 ,INPUT, X), " &
"27 (BC_2, A_BCLKR0 ,INPUT, X), " &
"28 (BC_2, CLKIN ,INPUT, X), " &
"29 (BC_2, XIO ,INPUT, X), " &
"30 (BC_2, SELA_B ,INPUT, X), " &
"31 (BC_2, HMODE ,INPUT, X), " &
"32 (BC_2, HD(0) ,INPUT, X), " &
"33 (BC_2, HD(1) ,INPUT, X), " &
"34 (BC_2, HD(2) ,INPUT, X), " &
"35 (BC_2, HD(3) ,INPUT, X), " &
"36 (BC_2, HD(4) ,INPUT, X), " &
"37 (BC_2, HD(5) ,INPUT, X), " &
"38 (BC_2, HD(6) ,INPUT, X), " &
"39 (BC_2, HD(7) ,INPUT, X), " &
"40 (BC_2, HD(8) ,INPUT, X), " &
"41 (BC_2, HD(9) ,INPUT, X), " &
"42 (BC_2, HD(10) ,INPUT, X), " &
"43 (BC_2, HD(11) ,INPUT, X), " &
"44 (BC_2, HD(12) ,INPUT, X), " &
"45 (BC_2, HD(13) ,INPUT, X), " &
"46 (BC_2, HD(14) ,INPUT, X), " &
"47 (BC_2, HD(15) ,INPUT, X), " &
"48 (BC_2, HA(0) ,INPUT, X), " &
"49 (BC_2, HA(1) ,INPUT, X), " &
"50 (BC_2, HA(2) ,INPUT, X), " &
"51 (BC_2, HA(3) ,INPUT, X), " &
"52 (BC_2, HA(4) ,INPUT, X), " &
"53 (BC_2, HA(5) ,INPUT, X), " &
"54 (BC_2, HA(6) ,INPUT, X), " &
"55 (BC_2, HA(7) ,INPUT, X), " &
"56 (BC_2, HA(8) ,INPUT, X), " &
"57 (BC_2, HA(9) ,INPUT, X), " &
"58 (BC_2, HA(10) ,INPUT, X), " &
"59 (BC_2, HA(11) ,INPUT, X), " &
"60 (BC_2, HA(12) ,INPUT, X), " &
"61 (BC_2, HA(13) ,INPUT, X), " &
"62 (BC_2, HA(14) ,INPUT, X), " &
"63 (BC_2, HA(15) ,INPUT, X), " &
"64 (BC_2, HA(16) ,INPUT, X), " &
"65 (BC_2, HA(17) ,INPUT, X), " &
"66 (BC_2, HDS1 ,INPUT, X), " &
"67 (BC_2, HDS2 ,INPUT, X), " &
"68 (BC_2, HCS ,INPUT, X), " &
"69 (BC_2, HRNW ,INPUT, X), " &
"70 (BC_2, HRDY ,INPUT, X), " &
"71 (BC_2, HPIRS ,INPUT, X) " ;
attribute DESIGN_WARNING of TMS320VC5420_cpu_A: entity is
"Technical Note for Texas Instruments TMS320VC5420 Device " &
" " &
"Boundary Scan Cell and Instruction Support Limitations " &
" " &
"Overview: " &
" " &
"The TMS320VC5420 has implemented a limited boundary scan capability " &
"with respect to boundary scan cells. The user should be aware " &
"that this design is NOT compliant to IEEE standard 1149.1. " &
" " &
" " &
"Observe-only Boundary Scan Cell Implementation " &
" " &
"The device implements observe-only boundary scan cells on all " &
"testable pins. Use of observe-only pins may limit interconnect " &
"test coverage to output pins and input/output pins if another " &
"boundary scan cell with control capability is not available to " &
"control the node. This BSDL file describes all pins as inputs to " &
"facilitate a BSDL description of the observe-only cells. " &
" " &
" " &
"Work Around: " &
" " &
"Boundary Scan Cell Implementation " &
" " &
"The use of observe only boundary scan cells may limit test " &
"coverage but does not require any specific work around. " &
"Interconnect test on nodes with no boundary scan control " &
"capability must be tested by other means. " &
" " &
" ";
end TMS320VC5420_cpu_A;
