-- ***********************************************************************
-- BSDL file for design ds3152
-- Created by Synopsys Version 2000.11 (Nov 27, 2000)
-- Designer:
-- Company: Dallas Semiconductor
-- Date: Tue Feb 24 15:56:29 2004
-- ***********************************************************************
entity ds3152 is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "CSBGA_144");
-- This section declares all the ports in the design.
port (
A0 : in bit;
A1 : in bit;
A2 : in bit;
A3 : in bit;
ALE : in bit;
CS_N : in bit;
E3M2 : in bit;
HIZ_N : in bit;
HW : in bit;
JTCLK : in bit;
JTDI : in bit;
JTMS : in bit;
JTRST_N : in bit;
LLB1 : in bit;
LLB2 : in bit;
MOT : in bit;
RBIN : in bit;
RCINV : in bit;
RD_N : in bit;
RJA1 : in bit;
RJA2 : in bit;
RLB2 : in bit;
RMON1 : in bit;
RMON2 : in bit;
RST_N : in bit;
RTS1_N : in bit;
RTS2_N : in bit;
STS2 : in bit;
TBIN : in bit;
TCINV : in bit;
TCLK1 : in bit;
TCLK2 : in bit;
TDSA2 : in bit;
TDSB2 : in bit;
TEST_N : in bit;
TJA1 : in bit;
TJA2 : in bit;
TLBO2 : in bit;
TNEG1 : in bit;
TNEG2 : in bit;
TPOS1 : in bit;
TPOS2 : in bit;
TTS1_N : in bit;
TTS2_N : in bit;
D5 : inout bit;
D6 : inout bit;
D7 : inout bit;
E3M1 : inout bit;
E3MCLK : inout bit;
RLB1 : inout bit;
STMCLK : inout bit;
STS1 : inout bit;
T3MCLK : inout bit;
TDSA1 : inout bit;
TDSB1 : inout bit;
TLBO1 : inout bit;
JTDO : out bit;
PRBS1 : out bit;
PRBS2 : out bit;
RCLK1 : out bit;
RCLK2 : out bit;
RLOS1_N : out bit;
RLOS2_N : out bit;
RNEG1 : out bit;
RNEG2 : out bit;
RPOS1 : out bit;
RPOS2 : out bit;
TDM1_N : out bit;
TDM2_N : out bit;
RXN1 : linkage bit;
RXN2 : linkage bit;
RXP1 : linkage bit;
RXP2 : linkage bit;
TXN1 : linkage bit;
TXN2 : linkage bit;
TXP1 : linkage bit;
TXP2 : linkage bit;
NC : linkage bit_vector (1 to 43);
VDD : linkage bit_vector (1 to 12);
VSS : linkage bit_vector (1 to 12)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of ds3152: entity is "STD_1149_1_1993";
attribute PIN_MAP of ds3152: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant CSBGA_144: PIN_MAP_STRING :=
"A0 : K6," &
"A1 : L6," &
"A2 : K7," &
"A3 : L7," &
"ALE : C7," &
"CS_N : B7," &
"E3M2 : G10," &
"HIZ_N : J8," &
"HW : E9," &
"JTCLK : E4," &
"JTDI : H4," &
"JTMS : D5," &
"JTRST_N : D4," &
"LLB1 : B5," &
"LLB2 : L8," &
"MOT : C6," &
"RBIN : D9," &
"RCINV : J9," &
"RD_N : B6," &
"RJA1 : B4," &
"RJA2 : L9," &
"RLB2 : K8," &
"RMON1 : A4," &
"RMON2 : M9," &
"RST_N : H1," &
"RTS1_N : B2," &
"RTS2_N : L11," &
"STS2 : G11," &
"TBIN : D8," &
"TCINV : H9," &
"TCLK1 : E1," &
"TCLK2 : H12," &
"TDSA2 : F11," &
"TDSB2 : F10," &
"TEST_N : J5," &
"TJA1 : C4," &
"TJA2 : K9," &
"TLBO2 : H10," &
"TNEG1 : D2," &
"TNEG2 : J11," &
"TPOS1 : D1," &
"TPOS2 : J12," &
"TTS1_N : E2," &
"TTS2_N : H11," &
"D5 : H2," &
"D6 : H3," &
"D7 : J3," &
"E3M1 : F3," &
"E3MCLK : E12," &
"RLB1 : C5," &
"STMCLK : M8," &
"STS1 : F2," &
"T3MCLK : A5," &
"TDSA1 : G2," &
"TDSB1 : G3," &
"TLBO1 : E3," &
"JTDO : J4," &
"PRBS1 : B1," &
"PRBS2 : L12," &
"RCLK1 : C1," &
"RCLK2 : K12," &
"RLOS1_N : A1," &
"RLOS2_N : M12," &
"RNEG1 : C3," &
"RNEG2 : K10," &
"RPOS1 : C2," &
"RPOS2 : K11," &
"TDM1_N : D3," &
"TDM2_N : J10," &
"RXN1 : A2," &
"RXN2 : M11," &
"RXP1 : A3," &
"RXP2 : M10," &
"TXN1 : G1," &
"TXN2 : F12," &
"TXP1 : F1," &
"TXP2 : G12," &
"NC : (A6, A7, A8, A9, A10, A11, A12, B3, B8, B9, B10, B11, B12" &
", C8, C9, C10, C11, C12, D10, D11, D12, E10, E11, J1, J2, K1, K2, " &
"K3, K4, K5, L1, L2, L3, L4, L5, L10, M1, M2, M3, M4, M5, M6, M7)," &
"VDD : (D6, E5, E6, F4, F5, F6, G7, G8, G9, H7, H8, J7)," &
"VSS : (D7, E7, E8, F7, F8, F9, G4, G5, G6, H5, H6, J6)";
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of JTCLK : signal is (1.000000e+07, BOTH);
attribute TAP_SCAN_IN of JTDI : signal is true;
attribute TAP_SCAN_MODE of JTMS : signal is true;
attribute TAP_SCAN_OUT of JTDO : signal is true;
attribute TAP_SCAN_RESET of JTRST_N: signal is true;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of ds3152: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of ds3152: entity is
"BYPASS (111)," &
"EXTEST (000)," &
"SAMPLE (010)," &
"CLAMP (011)," &
"HIGHZ (100)," &
"USER1 (101)," &
"USER2 (110)," &
"IDCODE (001)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of ds3152: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of ds3152: entity is
"XXXX" & -- 4-bit version number
"0000000000110000" & -- 16-bit part number
"00010100001" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of ds3152: entity is
"BYPASS (BYPASS, CLAMP, HIGHZ, USER1, USER2)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"DEVICE_ID (IDCODE)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of ds3152: entity is 127;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of ds3152: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"126 (BC_4, TCLK1, observe_only, X), " &
"125 (BC_4, TPOS1, observe_only, X), " &
"124 (BC_4, TNEG1, observe_only, X), " &
"123 (BC_4, TDSA1, observe_only, X), " &
"122 (BC_2, TDSA1, output3, X, 121, 1, Z), " &
"121 (BC_2, *, controlr, 1), " &
"120 (BC_4, TDSB1, observe_only, X), " &
"119 (BC_2, TDSB1, output3, X, 118, 1, Z), " &
"118 (BC_2, *, controlr, 1), " &
"117 (BC_4, TLBO1, observe_only, X), " &
"116 (BC_2, TLBO1, output3, X, 115, 1, Z), " &
"115 (BC_2, *, controlr, 1), " &
"114 (BC_4, TTS1_N, observe_only, X), " &
"113 (BC_4, TJA1, observe_only, X), " &
"112 (BC_4, RMON1, observe_only, X), " &
"111 (BC_4, RTS1_N, observe_only, X), " &
"110 (BC_4, RJA1, observe_only, X), " &
"109 (BC_4, LLB1, observe_only, X), " &
"108 (BC_4, RLB1, observe_only, X), " &
"107 (BC_0, *, internal, X), " &
"106 (BC_2, RLB1, output2, 1, 106, 1, WEAK1)," &
"105 (BC_4, E3M1, observe_only, X), " &
"104 (BC_2, E3M1, output3, X, 103, 1, Z), " &
"103 (BC_2, *, controlr, 1), " &
"102 (BC_4, STS1, observe_only, X), " &
"101 (BC_2, STS1, output3, X, 100, 1, Z), " &
"100 (BC_2, *, controlr, 1), " &
"99 (BC_2, TDM1_N, output2, 1, 99, 1, WEAK1)," &
"98 (BC_2, RLOS1_N, output2, 1, 98, 1, WEAK1)," &
"97 (BC_2, PRBS1, output3, X, 96, 1, Z), " &
"96 (BC_2, *, controlr, 1), " &
"95 (BC_2, RCLK1, output3, X, 92, 1, Z), " &
"94 (BC_2, RPOS1, output3, X, 92, 1, Z), " &
"93 (BC_2, RNEG1, output3, X, 92, 1, Z), " &
"92 (BC_2, *, controlr, 1), " &
"91 (BC_4, TCLK2, observe_only, X), " &
"90 (BC_4, TPOS2, observe_only, X), " &
"89 (BC_4, TNEG2, observe_only, X), " &
"88 (BC_4, TDSA2, observe_only, X), " &
"87 (BC_4, TDSB2, observe_only, X), " &
"86 (BC_4, TLBO2, observe_only, X), " &
"85 (BC_4, TTS2_N, observe_only, X), " &
"84 (BC_4, TJA2, observe_only, X), " &
"83 (BC_4, RMON2, observe_only, X), " &
"82 (BC_4, RTS2_N, observe_only, X), " &
"81 (BC_4, RJA2, observe_only, X), " &
"80 (BC_4, LLB2, observe_only, X), " &
"79 (BC_4, RLB2, observe_only, X), " &
"78 (BC_4, E3M2, observe_only, X), " &
"77 (BC_4, STS2, observe_only, X), " &
"76 (BC_2, TDM2_N, output2, 1, 76, 1, WEAK1)," &
"75 (BC_2, RLOS2_N, output2, 1, 75, 1, WEAK1)," &
"74 (BC_2, PRBS2, output3, X, 73, 1, Z), " &
"73 (BC_2, *, controlr, 1), " &
"72 (BC_2, RCLK2, output3, X, 69, 1, Z), " &
"71 (BC_2, RPOS2, output3, X, 69, 1, Z), " &
"70 (BC_2, RNEG2, output3, X, 69, 1, Z), " &
"69 (BC_2, *, controlr, 1), " &
"68 (BC_0, *, internal, X), " &
"67 (BC_0, *, internal, X), " &
"66 (BC_0, *, internal, X), " &
"65 (BC_4, RD_N, observe_only, X), " &
"64 (BC_4, MOT, observe_only, X), " &
"63 (BC_0, *, internal, X), " &
"62 (BC_0, *, internal, X), " &
"61 (BC_0, *, internal, X), " &
"60 (BC_0, *, internal, X), " &
"59 (BC_0, *, internal, X), " &
"58 (BC_0, *, internal, X), " &
"57 (BC_0, *, internal, X), " &
"56 (BC_0, *, internal, X), " &
"55 (BC_4, ALE, observe_only, X), " &
"54 (BC_4, CS_N, observe_only, X), " &
"53 (BC_0, *, internal, X), " &
"52 (BC_0, *, internal, X), " &
"51 (BC_0, *, internal, X), " &
"50 (BC_0, *, internal, X), " &
"49 (BC_0, *, internal, X), " &
"48 (BC_0, *, internal, X), " &
"47 (BC_0, *, internal, X), " &
"46 (BC_0, *, internal, X), " &
"45 (BC_0, *, internal, X), " &
"44 (BC_0, *, internal, X), " &
"43 (BC_0, *, internal, X), " &
"42 (BC_4, A3, observe_only, X), " &
"41 (BC_4, A2, observe_only, X), " &
"40 (BC_0, *, internal, X), " &
"39 (BC_0, *, internal, X), " &
"38 (BC_4, D7, observe_only, X), " &
"37 (BC_2, D7, output3, X, 36, 1, Z), " &
"36 (BC_2, *, controlr, 1), " &
"35 (BC_0, *, internal, X), " &
"34 (BC_0, *, internal, X), " &
"33 (BC_0, *, internal, X), " &
"32 (BC_4, D5, observe_only, X), " &
"31 (BC_2, D5, output3, X, 30, 1, Z), " &
"30 (BC_2, *, controlr, 1), " &
"29 (BC_4, D6, observe_only, X), " &
"28 (BC_2, D6, output3, X, 27, 1, Z), " &
"27 (BC_2, *, controlr, 1), " &
"26 (BC_4, A0, observe_only, X), " &
"25 (BC_4, A1, observe_only, X), " &
"24 (BC_0, *, internal, X), " &
"23 (BC_0, *, internal, X), " &
"22 (BC_0, *, internal, X), " &
"21 (BC_0, *, internal, X), " &
"20 (BC_0, *, internal, X), " &
"19 (BC_0, *, internal, X), " &
"18 (BC_0, *, internal, X), " &
"17 (BC_0, *, internal, X), " &
"16 (BC_4, T3MCLK, observe_only, X), " &
"15 (BC_2, T3MCLK, output3, X, 14, 1, Z), " &
"14 (BC_2, *, controlr, 1), " &
"13 (BC_4, E3MCLK, observe_only, X), " &
"12 (BC_2, E3MCLK, output3, X, 11, 1, Z), " &
"11 (BC_2, *, controlr, 1), " &
"10 (BC_4, STMCLK, observe_only, X), " &
"9 (BC_2, STMCLK, output3, X, 8, 1, Z), " &
"8 (BC_2, *, controlr, 1), " &
"7 (BC_4, RST_N, observe_only, X), " &
"6 (BC_4, HIZ_N, observe_only, X), " &
"5 (BC_4, TEST_N, observe_only, X), " &
"4 (BC_4, HW, observe_only, X), " &
"3 (BC_4, RBIN, observe_only, X), " &
"2 (BC_4, TBIN, observe_only, X), " &
"1 (BC_4, RCINV, observe_only, X), " &
"0 (BC_4, TCINV, observe_only, X) ";
end ds3152;