--$ XILINX$RCSfile: xc4005xl_pq160.bsd,v $
--$ XILINX$Revision: 1.3 $
--
-- BSDL file for device XC4005XL, package PQ160
-- Xilinx, Inc. $State: FINAL $ $Date: 1997-10-17 01:32:26+00 $
-- Generated by createBSDL 2.6
--
-- For technical support, contact Xilinx as follows:
-- North America 1-800-255-7778 hotline@xilinx.com
-- United Kingdom (44) 1932 820821 ukhelp@xilinx.com
-- France (33) 1 3463 0100 frhelp@xilinx.com
-- Germany (49) 89 991 54930 dlhelp@xilinx.com
-- Japan (81) 3-3297-9163 jhotline@xilinx.com
--
-- BSDL verified to conform to 1149.1b-1994 syntax. This device has been
-- tested by the Intellitech 1149.1 Verification Lab using the Intellitech
-- Eclipse(TM) Scan Diagnostic Tool and the Intellitech RCT(TM). This
-- device has been verified to operate according to the BSDL provided,
-- and is compatible with the IEEE 1149.1 standard when the operating
-- instructions in the BSDL are followed.
-- PH: 603-868-7116 or email: scansupport@intellitech.com
--
-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect
-- the post-configuration JTAG behavior (if any), edit this file as described
-- below. Many of these changes are demonstrated by commented-out template
-- lines preceeding the lines they would replace:
--
-- 1. Enable USER instructions as appropriate (see below).
-- 2. For inputs using uncontrolled paths (e.g. PGCK, SGCK), change
-- boundary cell function from 'input' to 'clock' or 'observe_only'.
-- 3. Set disable result of all pads as configured.
-- 4. Set safe state of boundary cells as necessary.
-- 5. Set safe state of INIT output to X, or as necessary (see below).
-- 6. Rename entity if necessary to avoid name collisions.
-- 7. Change INIT port direction from "in" to "inout" (see below).
-- 8. Change COMPLIANCE_PATTERNS to "(PROGRAM) (1)" (see below).
-- 9. Change INIT boundary cells from internal to controlr, output3,
-- and input, respectively (see below).
-- 10. Remove the design warning regarding keeping INIT low.
--
-- NOTE: Post-configuration JTAG is available only if the BSCAN symbol
-- is instantiated in the FPGA design.
-- NOTE: PULLUP symbols must be instantiated on the TMS and TDI pins
-- in the FPGA design to comply with IEEE Std. 1149.1-1993.
entity XC4005XL_PQ160 is
generic (PHYSICAL_PIN_MAP : string := "PQ160" );
port (
CCLK: linkage bit;
DONE: linkage bit;
GND: linkage bit_vector (1 to 16);
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the following line so
-- that INIT is of type inout.
-- INIT: inout bit;
INIT: in bit;
IO2: inout bit;
IO3: inout bit;
IO4: inout bit;
IO5: inout bit;
IO6: inout bit;
IO7: inout bit;
IO8: inout bit;
IO9: inout bit;
IO11: inout bit;
IO12: inout bit;
IO13: inout bit;
IO14: inout bit;
IO15: inout bit;
IO16: inout bit;
IO20: inout bit;
IO21: inout bit;
IO22: inout bit;
IO23: inout bit;
IO27: inout bit;
IO28: inout bit;
IO30: inout bit;
IO31: inout bit;
IO32: inout bit;
IO33: inout bit;
IO35: inout bit;
IO39: inout bit;
IO40: inout bit;
IO41: inout bit;
IO42: inout bit;
IO43: inout bit;
IO44: inout bit;
IO45: inout bit;
IO46: inout bit;
IO48: inout bit;
IO49: inout bit;
IO50: inout bit;
IO51: inout bit;
IO52: inout bit;
IO53: inout bit;
IO60: inout bit;
IO61: inout bit;
IO62: inout bit;
IO63: inout bit;
IO64: inout bit;
IO65: inout bit;
IO67: inout bit;
IO68: inout bit;
IO69: inout bit;
IO70: inout bit;
IO71: inout bit;
IO72: inout bit;
IO73: inout bit;
IO77: inout bit;
IO78: inout bit;
IO79: inout bit;
IO80: inout bit;
IO81: inout bit;
IO82: inout bit;
IO83: inout bit;
IO84: inout bit;
IO86: inout bit;
IO87: inout bit;
IO88: inout bit;
IO89: inout bit;
IO90: inout bit;
IO91: inout bit;
IO97: inout bit;
IO98: inout bit;
IO99: inout bit;
IO100: inout bit;
IO101: inout bit;
IO102: inout bit;
IO104: inout bit;
IO105: inout bit;
IO106: inout bit;
IO107: inout bit;
IO108: inout bit;
IO109: inout bit;
IO110: inout bit;
IO111: inout bit;
IO114: inout bit;
IO115: inout bit;
IO116: inout bit;
IO117: inout bit;
IO118: inout bit;
IO119: inout bit;
IO120: inout bit;
IO121: inout bit;
IO123: inout bit;
IO124: inout bit;
IO125: inout bit;
IO126: inout bit;
IO127: inout bit;
IO128: inout bit;
IO134: inout bit;
IO135: inout bit;
IO136: inout bit;
IO137: inout bit;
IO138: inout bit;
IO139: inout bit;
IO141: inout bit;
IO142: inout bit;
IO143: inout bit;
IO144: inout bit;
IO145: inout bit;
IO146: inout bit;
IO147: inout bit;
IO148: inout bit;
M0: in bit;
M1: inout bit;
M2: in bit;
PROGRAM: in bit;
TCK: in bit;
TDI: in bit;
TDO: out bit;
TMS: in bit;
VDD: linkage bit_vector (1 to 8)
); --end port list
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of XC4005XL_PQ160 : entity is
"STD_1149_1_1993";
attribute PIN_MAP of XC4005XL_PQ160 : entity is PHYSICAL_PIN_MAP;
constant PQ160: PIN_MAP_STRING:=
"CCLK:P119," &
"DONE:P80," &
"GND:(P151,P1,P10,P19,P29,P39,P51,P61,P70,P79," &
"P91,P101,P110,P122,P131,P141)," &
"INIT:P59," &
"IO2:P143," &
"IO3:P144," &
"IO4:P145," &
"IO5:P146," &
"IO6:P147," &
"IO7:P148," &
"IO8:P149," &
"IO9:P150," &
"IO11:P154," &
"IO12:P155," &
"IO13:P156," &
"IO14:P157," &
"IO15:P158," &
"IO16:P159," &
"IO20:P2," &
"IO21:P3," &
"IO22:P4," &
"IO23:P5," &
"IO27:P11," &
"IO28:P12," &
"IO30:P14," &
"IO31:P15," &
"IO32:P16," &
"IO33:P17," &
"IO35:P18," &
"IO39:P21," &
"IO40:P22," &
"IO41:P23," &
"IO42:P24," &
"IO43:P25," &
"IO44:P26," &
"IO45:P27," &
"IO46:P28," &
"IO48:P32," &
"IO49:P33," &
"IO50:P34," &
"IO51:P35," &
"IO52:P36," &
"IO53:P37," &
"IO60:P43," &
"IO61:P44," &
"IO62:P45," &
"IO63:P46," &
"IO64:P47," &
"IO65:P48," &
"IO67:P52," &
"IO68:P53," &
"IO69:P54," &
"IO70:P55," &
"IO71:P56," &
"IO72:P57," &
"IO73:P58," &
"IO77:P62," &
"IO78:P63," &
"IO79:P64," &
"IO80:P65," &
"IO81:P66," &
"IO82:P67," &
"IO83:P68," &
"IO84:P69," &
"IO86:P73," &
"IO87:P74," &
"IO88:P75," &
"IO89:P76," &
"IO90:P77," &
"IO91:P78," &
"IO97:P83," &
"IO98:P84," &
"IO99:P85," &
"IO100:P86," &
"IO101:P87," &
"IO102:P88," &
"IO104:P92," &
"IO105:P93," &
"IO106:P94," &
"IO107:P95," &
"IO108:P96," &
"IO109:P97," &
"IO110:P98," &
"IO111:P99," &
"IO114:P102," &
"IO115:P103," &
"IO116:P104," &
"IO117:P105," &
"IO118:P106," &
"IO119:P107," &
"IO120:P108," &
"IO121:P109," &
"IO123:P113," &
"IO124:P114," &
"IO125:P115," &
"IO126:P116," &
"IO127:P117," &
"IO128:P118," &
"IO134:P123," &
"IO135:P124," &
"IO136:P125," &
"IO137:P126," &
"IO138:P127," &
"IO139:P128," &
"IO141:P132," &
"IO142:P133," &
"IO143:P134," &
"IO144:P135," &
"IO145:P137," &
"IO146:P138," &
"IO147:P139," &
"IO148:P140," &
"M0:P40," &
"M1:P38," &
"M2:P42," &
"PROGRAM:P82," &
"TCK:P7," &
"TDI:P6," &
"TDO:P121," &
"TMS:P13," &
"VDD:(P142,P160,P20,P41,P60,P81,P100,P120)";
--end pin map
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (2.0e6, LOW);
-- This is conservative. Real max is expected to be (~5MHz, BOTH).
attribute COMPLIANCE_PATTERNS of XC4005XL_PQ160 : entity is
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the corresponding line
-- below.
-- "(PROGRAM) (1)";
--
-- NOTE: If INIT has been high or floating since the later of power-on
-- and the last rising transition of PROGRAM, then the device may
-- be in configuration mode in which case some JTAG instructions
-- will not be available.
"(INIT,PROGRAM) (01)";
attribute INSTRUCTION_LENGTH of XC4005XL_PQ160 : entity is 3;
attribute INSTRUCTION_OPCODE of XC4005XL_PQ160 : entity is
"SAMPLE (001)," & -- Internal capture not valid until after config
"RESERVED (110)," &
"READBACK (100)," & -- Not available during configuration
"CONFIGURE (101)," & -- Not available during configuration
"USER2 (011)," & -- Not available until after configuration
"USER1 (010)," & -- Not available until after configuration
"EXTEST (000)," & -- Not available during configuration
"BYPASS (111)";
attribute INSTRUCTION_CAPTURE of XC4005XL_PQ160 : entity is "X01";
-- MSB of instruction capture is low during configuration.
-- If the device is configured, and a USER instruction is implemented
-- and not private to the FPGA designer, then it should be removed
-- from INSTRUCTION_PRIVATE, and the target register should be defined
-- in REGISTER_ACCESS.
attribute INSTRUCTION_PRIVATE of XC4005XL_PQ160 : entity is
"USER1," &
"USER2," &
"READBACK," &
"RESERVED," &
"CONFIGURE";
attribute REGISTER_ACCESS of XC4005XL_PQ160 : entity is
-- "<reg_name>[<length>] (USER1)," &
-- "<reg_name>[<length>] (USER2)," &
"BYPASS (BYPASS)," &
"BOUNDARY (SAMPLE,EXTEST)";
attribute BOUNDARY_LENGTH of XC4005XL_PQ160 : entity is 344;
attribute BOUNDARY_REGISTER of XC4005XL_PQ160 : entity is
-- cellnum (type, port, function, safe[, ccell, disval, disrslt])
" 0 (BC_1, *, internal, X)," &
" 1 (BC_1, *, internal, X)," &
" 2 (BC_1, *, controlr, 1)," &
" 3 (BC_1, IO134, output3, X, 2, 1, PULL1)," &
" 4 (BC_1, IO134, input, X)," &
" 5 (BC_1, *, controlr, 1)," &
" 6 (BC_1, IO135, output3, X, 5, 1, PULL1)," &
" 7 (BC_1, IO135, input, X)," &
" 8 (BC_1, *, controlr, 1)," &
" 9 (BC_1, IO136, output3, X, 8, 1, PULL1)," &
" 10 (BC_1, IO136, input, X)," &
" 11 (BC_1, *, controlr, 1)," &
" 12 (BC_1, IO137, output3, X, 11, 1, PULL1)," &
" 13 (BC_1, IO137, input, X)," &
" 14 (BC_1, *, controlr, 1)," &
" 15 (BC_1, IO138, output3, X, 14, 1, PULL1)," &
" 16 (BC_1, IO138, input, X)," &
" 17 (BC_1, *, controlr, 1)," &
" 18 (BC_1, IO139, output3, X, 17, 1, PULL1)," &
" 19 (BC_1, IO139, input, X)," &
" 20 (BC_1, *, controlr, 1)," &
" 21 (BC_1, IO141, output3, X, 20, 1, PULL1)," &
" 22 (BC_1, IO141, input, X)," &
" 23 (BC_1, *, controlr, 1)," &
" 24 (BC_1, IO142, output3, X, 23, 1, PULL1)," &
" 25 (BC_1, IO142, input, X)," &
" 26 (BC_1, *, controlr, 1)," &
" 27 (BC_1, IO143, output3, X, 26, 1, PULL1)," &
" 28 (BC_1, IO143, input, X)," &
" 29 (BC_1, *, controlr, 1)," &
" 30 (BC_1, IO144, output3, X, 29, 1, PULL1)," &
" 31 (BC_1, IO144, input, X)," &
" 32 (BC_1, *, controlr, 1)," &
" 33 (BC_1, IO145, output3, X, 32, 1, PULL1)," &
" 34 (BC_1, IO145, input, X)," &
" 35 (BC_1, *, controlr, 1)," &
" 36 (BC_1, IO146, output3, X, 35, 1, PULL1)," &
" 37 (BC_1, IO146, input, X)," &
" 38 (BC_1, *, controlr, 1)," &
" 39 (BC_1, IO147, output3, X, 38, 1, PULL1)," &
" 40 (BC_1, IO147, input, X)," &
" 41 (BC_1, *, controlr, 1)," &
" 42 (BC_1, IO148, output3, X, 41, 1, PULL1)," &
" 43 (BC_1, IO148, input, X)," &
" 44 (BC_1, *, controlr, 1)," &
" 45 (BC_1, IO2, output3, X, 44, 1, PULL1)," &
" 46 (BC_1, IO2, input, X)," &
" 47 (BC_1, *, controlr, 1)," &
" 48 (BC_1, IO3, output3, X, 47, 1, PULL1)," &
" 49 (BC_1, IO3, input, X)," &
" 50 (BC_1, *, controlr, 1)," &
" 51 (BC_1, IO4, output3, X, 50, 1, PULL1)," &
" 52 (BC_1, IO4, input, X)," &
" 53 (BC_1, *, controlr, 1)," &
" 54 (BC_1, IO5, output3, X, 53, 1, PULL1)," &
" 55 (BC_1, IO5, input, X)," &
" 56 (BC_1, *, controlr, 1)," &
" 57 (BC_1, IO6, output3, X, 56, 1, PULL1)," &
" 58 (BC_1, IO6, input, X)," &
" 59 (BC_1, *, controlr, 1)," &
" 60 (BC_1, IO7, output3, X, 59, 1, PULL1)," &
" 61 (BC_1, IO7, input, X)," &
" 62 (BC_1, *, controlr, 1)," &
" 63 (BC_1, IO8, output3, X, 62, 1, PULL1)," &
" 64 (BC_1, IO8, input, X)," &
" 65 (BC_1, *, controlr, 1)," &
" 66 (BC_1, IO9, output3, X, 65, 1, PULL1)," &
" 67 (BC_1, IO9, input, X)," &
" 68 (BC_1, *, controlr, 1)," &
" 69 (BC_1, IO11, output3, X, 68, 1, PULL1)," &
" 70 (BC_1, IO11, input, X)," &
" 71 (BC_1, *, controlr, 1)," &
" 72 (BC_1, IO12, output3, X, 71, 1, PULL1)," &
" 73 (BC_1, IO12, input, X)," &
" 74 (BC_1, *, controlr, 1)," &
" 75 (BC_1, IO13, output3, X, 74, 1, PULL1)," &
" 76 (BC_1, IO13, input, X)," &
" 77 (BC_1, *, controlr, 1)," &
" 78 (BC_1, IO14, output3, X, 77, 1, PULL1)," &
" 79 (BC_1, IO14, input, X)," &
" 80 (BC_1, *, controlr, 1)," &
" 81 (BC_1, IO15, output3, X, 80, 1, PULL1)," &
" 82 (BC_1, IO15, input, X)," &
" 83 (BC_1, *, controlr, 1)," &
" 84 (BC_1, IO16, output3, X, 83, 1, PULL1)," &
" 85 (BC_1, IO16, input, X)," &
" 86 (BC_1, *, controlr, 1)," &
" 87 (BC_1, IO20, output3, X, 86, 1, PULL1)," &
" 88 (BC_1, IO20, input, X)," &
" 89 (BC_1, *, controlr, 1)," &
" 90 (BC_1, IO21, output3, X, 89, 1, PULL1)," &
" 91 (BC_1, IO21, input, X)," &
" 92 (BC_1, *, controlr, 1)," &
" 93 (BC_1, IO22, output3, X, 92, 1, PULL1)," &
" 94 (BC_1, IO22, input, X)," &
" 95 (BC_1, *, controlr, 1)," &
" 96 (BC_1, IO23, output3, X, 95, 1, PULL1)," &
" 97 (BC_1, IO23, input, X)," &
" 98 (BC_1, *, internal, X)," &
" 99 (BC_1, *, internal, X)," &
" 100 (BC_1, *, internal, X)," &
" 101 (BC_1, *, internal, X)," &
" 102 (BC_1, *, internal, X)," &
" 103 (BC_1, *, internal, X)," &
" 104 (BC_1, *, controlr, 1)," &
" 105 (BC_1, IO27, output3, X, 104, 1, PULL1)," &
" 106 (BC_1, IO27, input, X)," &
" 107 (BC_1, *, controlr, 1)," &
" 108 (BC_1, IO28, output3, X, 107, 1, PULL1)," &
" 109 (BC_1, IO28, input, X)," &
" 110 (BC_1, *, internal, X)," &
" 111 (BC_1, *, internal, X)," &
" 112 (BC_1, *, internal, X)," &
" 113 (BC_1, *, controlr, 1)," &
" 114 (BC_1, IO30, output3, X, 113, 1, PULL1)," &
" 115 (BC_1, IO30, input, X)," &
" 116 (BC_1, *, controlr, 1)," &
" 117 (BC_1, IO31, output3, X, 116, 1, PULL1)," &
" 118 (BC_1, IO31, input, X)," &
" 119 (BC_1, *, controlr, 1)," &
" 120 (BC_1, IO32, output3, X, 119, 1, PULL1)," &
" 121 (BC_1, IO32, input, X)," &
" 122 (BC_1, *, controlr, 1)," &
" 123 (BC_1, IO33, output3, X, 122, 1, PULL1)," &
" 124 (BC_1, IO33, input, X)," &
" 125 (BC_1, *, controlr, 1)," &
" 126 (BC_1, IO35, output3, X, 125, 1, PULL1)," &
" 127 (BC_1, IO35, input, X)," &
" 128 (BC_1, *, controlr, 1)," &
" 129 (BC_1, IO39, output3, X, 128, 1, PULL1)," &
" 130 (BC_1, IO39, input, X)," &
" 131 (BC_1, *, controlr, 1)," &
" 132 (BC_1, IO40, output3, X, 131, 1, PULL1)," &
" 133 (BC_1, IO40, input, X)," &
" 134 (BC_1, *, controlr, 1)," &
" 135 (BC_1, IO41, output3, X, 134, 1, PULL1)," &
" 136 (BC_1, IO41, input, X)," &
" 137 (BC_1, *, controlr, 1)," &
" 138 (BC_1, IO42, output3, X, 137, 1, PULL1)," &
" 139 (BC_1, IO42, input, X)," &
" 140 (BC_1, *, controlr, 1)," &
" 141 (BC_1, IO43, output3, X, 140, 1, PULL1)," &
" 142 (BC_1, IO43, input, X)," &
" 143 (BC_1, *, controlr, 1)," &
" 144 (BC_1, IO44, output3, X, 143, 1, PULL1)," &
" 145 (BC_1, IO44, input, X)," &
" 146 (BC_1, *, controlr, 1)," &
" 147 (BC_1, IO45, output3, X, 146, 1, PULL1)," &
" 148 (BC_1, IO45, input, X)," &
" 149 (BC_1, *, controlr, 1)," &
" 150 (BC_1, IO46, output3, X, 149, 1, PULL1)," &
" 151 (BC_1, IO46, input, X)," &
" 152 (BC_1, *, controlr, 1)," &
" 153 (BC_1, IO48, output3, X, 152, 1, PULL1)," &
" 154 (BC_1, IO48, input, X)," &
" 155 (BC_1, *, controlr, 1)," &
" 156 (BC_1, IO49, output3, X, 155, 1, PULL1)," &
" 157 (BC_1, IO49, input, X)," &
" 158 (BC_1, *, controlr, 1)," &
" 159 (BC_1, IO50, output3, X, 158, 1, PULL1)," &
" 160 (BC_1, IO50, input, X)," &
" 161 (BC_1, *, controlr, 1)," &
" 162 (BC_1, IO51, output3, X, 161, 1, PULL1)," &
" 163 (BC_1, IO51, input, X)," &
" 164 (BC_1, *, controlr, 1)," &
" 165 (BC_1, IO52, output3, X, 164, 1, PULL1)," &
" 166 (BC_1, IO52, input, X)," &
" 167 (BC_1, *, controlr, 1)," &
" 168 (BC_1, IO53, output3, X, 167, 1, PULL1)," &
" 169 (BC_1, IO53, input, X)," &
" 170 (BC_1, *, controlr, 1)," &
" 171 (BC_1, M1, output3, X, 170, 1, PULL1)," &
" 172 (BC_1, M1, input, X)," &
" 173 (BC_1, M0, input, X)," &
" 174 (BC_1, M2, input, X)," &
" 175 (BC_1, *, controlr, 1)," &
" 176 (BC_1, IO60, output3, X, 175, 1, PULL1)," &
" 177 (BC_1, IO60, input, X)," &
" 178 (BC_1, *, controlr, 1)," &
" 179 (BC_1, IO61, output3, X, 178, 1, PULL1)," &
" 180 (BC_1, IO61, input, X)," &
" 181 (BC_1, *, controlr, 1)," &
" 182 (BC_1, IO62, output3, X, 181, 1, PULL1)," &
" 183 (BC_1, IO62, input, X)," &
" 184 (BC_1, *, controlr, 1)," &
" 185 (BC_1, IO63, output3, X, 184, 1, PULL1)," &
" 186 (BC_1, IO63, input, X)," &
" 187 (BC_1, *, controlr, 1)," &
" 188 (BC_1, IO64, output3, X, 187, 1, PULL1)," &
" 189 (BC_1, IO64, input, X)," &
" 190 (BC_1, *, controlr, 1)," &
" 191 (BC_1, IO65, output3, X, 190, 1, PULL1)," &
" 192 (BC_1, IO65, input, X)," &
" 193 (BC_1, *, controlr, 1)," &
" 194 (BC_1, IO67, output3, X, 193, 1, PULL1)," &
" 195 (BC_1, IO67, input, X)," &
" 196 (BC_1, *, controlr, 1)," &
" 197 (BC_1, IO68, output3, X, 196, 1, PULL1)," &
" 198 (BC_1, IO68, input, X)," &
" 199 (BC_1, *, controlr, 1)," &
" 200 (BC_1, IO69, output3, X, 199, 1, PULL1)," &
" 201 (BC_1, IO69, input, X)," &
" 202 (BC_1, *, controlr, 1)," &
" 203 (BC_1, IO70, output3, X, 202, 1, PULL1)," &
" 204 (BC_1, IO70, input, X)," &
" 205 (BC_1, *, controlr, 1)," &
" 206 (BC_1, IO71, output3, X, 205, 1, PULL1)," &
" 207 (BC_1, IO71, input, X)," &
" 208 (BC_1, *, controlr, 1)," &
" 209 (BC_1, IO72, output3, X, 208, 1, PULL1)," &
" 210 (BC_1, IO72, input, X)," &
" 211 (BC_1, *, controlr, 1)," &
" 212 (BC_1, IO73, output3, X, 211, 1, PULL1)," &
" 213 (BC_1, IO73, input, X)," &
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the following line.
-- Repeat for registers 214 through 216.
-- " 214 (BC_1, *, controlr, 1)," &
" 214 (BC_1, *, internal, 1)," &
-- " 215 (BC_1, INIT, output3, X, 214, 1, PULL1)," &
" 215 (BC_1, *, internal, 0)," &
-- " 216 (BC_1, INIT, input, X)," &
" 216 (BC_1, *, internal, X)," &
" 217 (BC_1, *, controlr, 1)," &
" 218 (BC_1, IO77, output3, X, 217, 1, PULL1)," &
" 219 (BC_1, IO77, input, X)," &
" 220 (BC_1, *, controlr, 1)," &
" 221 (BC_1, IO78, output3, X, 220, 1, PULL1)," &
" 222 (BC_1, IO78, input, X)," &
" 223 (BC_1, *, controlr, 1)," &
" 224 (BC_1, IO79, output3, X, 223, 1, PULL1)," &
" 225 (BC_1, IO79, input, X)," &
" 226 (BC_1, *, controlr, 1)," &
" 227 (BC_1, IO80, output3, X, 226, 1, PULL1)," &
" 228 (BC_1, IO80, input, X)," &
" 229 (BC_1, *, controlr, 1)," &
" 230 (BC_1, IO81, output3, X, 229, 1, PULL1)," &
" 231 (BC_1, IO81, input, X)," &
" 232 (BC_1, *, controlr, 1)," &
" 233 (BC_1, IO82, output3, X, 232, 1, PULL1)," &
" 234 (BC_1, IO82, input, X)," &
" 235 (BC_1, *, controlr, 1)," &
" 236 (BC_1, IO83, output3, X, 235, 1, PULL1)," &
" 237 (BC_1, IO83, input, X)," &
" 238 (BC_1, *, controlr, 1)," &
" 239 (BC_1, IO84, output3, X, 238, 1, PULL1)," &
" 240 (BC_1, IO84, input, X)," &
" 241 (BC_1, *, controlr, 1)," &
" 242 (BC_1, IO86, output3, X, 241, 1, PULL1)," &
" 243 (BC_1, IO86, input, X)," &
" 244 (BC_1, *, controlr, 1)," &
" 245 (BC_1, IO87, output3, X, 244, 1, PULL1)," &
" 246 (BC_1, IO87, input, X)," &
" 247 (BC_1, *, controlr, 1)," &
" 248 (BC_1, IO88, output3, X, 247, 1, PULL1)," &
" 249 (BC_1, IO88, input, X)," &
" 250 (BC_1, *, controlr, 1)," &
" 251 (BC_1, IO89, output3, X, 250, 1, PULL1)," &
" 252 (BC_1, IO89, input, X)," &
" 253 (BC_1, *, controlr, 1)," &
" 254 (BC_1, IO90, output3, X, 253, 1, PULL1)," &
" 255 (BC_1, IO90, input, X)," &
" 256 (BC_1, *, controlr, 1)," &
" 257 (BC_1, IO91, output3, X, 256, 1, PULL1)," &
" 258 (BC_1, IO91, input, X)," &
" 259 (BC_1, *, controlr, 1)," &
" 260 (BC_1, IO97, output3, X, 259, 1, PULL1)," &
" 261 (BC_1, IO97, input, X)," &
" 262 (BC_1, *, controlr, 1)," &
" 263 (BC_1, IO98, output3, X, 262, 1, PULL1)," &
" 264 (BC_1, IO98, input, X)," &
" 265 (BC_1, *, controlr, 1)," &
" 266 (BC_1, IO99, output3, X, 265, 1, PULL1)," &
" 267 (BC_1, IO99, input, X)," &
" 268 (BC_1, *, controlr, 1)," &
" 269 (BC_1, IO100, output3, X, 268, 1, PULL1)," &
" 270 (BC_1, IO100, input, X)," &
" 271 (BC_1, *, controlr, 1)," &
" 272 (BC_1, IO101, output3, X, 271, 1, PULL1)," &
" 273 (BC_1, IO101, input, X)," &
" 274 (BC_1, *, controlr, 1)," &
" 275 (BC_1, IO102, output3, X, 274, 1, PULL1)," &
" 276 (BC_1, IO102, input, X)," &
" 277 (BC_1, *, controlr, 1)," &
" 278 (BC_1, IO104, output3, X, 277, 1, PULL1)," &
" 279 (BC_1, IO104, input, X)," &
" 280 (BC_1, *, controlr, 1)," &
" 281 (BC_1, IO105, output3, X, 280, 1, PULL1)," &
" 282 (BC_1, IO105, input, X)," &
" 283 (BC_1, *, controlr, 1)," &
" 284 (BC_1, IO106, output3, X, 283, 1, PULL1)," &
" 285 (BC_1, IO106, input, X)," &
" 286 (BC_1, *, controlr, 1)," &
" 287 (BC_1, IO107, output3, X, 286, 1, PULL1)," &
" 288 (BC_1, IO107, input, X)," &
" 289 (BC_1, *, controlr, 1)," &
" 290 (BC_1, IO108, output3, X, 289, 1, PULL1)," &
" 291 (BC_1, IO108, input, X)," &
" 292 (BC_1, *, controlr, 1)," &
" 293 (BC_1, IO109, output3, X, 292, 1, PULL1)," &
" 294 (BC_1, IO109, input, X)," &
" 295 (BC_1, *, controlr, 1)," &
" 296 (BC_1, IO110, output3, X, 295, 1, PULL1)," &
" 297 (BC_1, IO110, input, X)," &
" 298 (BC_1, *, controlr, 1)," &
" 299 (BC_1, IO111, output3, X, 298, 1, PULL1)," &
" 300 (BC_1, IO111, input, X)," &
" 301 (BC_1, *, controlr, 1)," &
" 302 (BC_1, IO114, output3, X, 301, 1, PULL1)," &
" 303 (BC_1, IO114, input, X)," &
" 304 (BC_1, *, controlr, 1)," &
" 305 (BC_1, IO115, output3, X, 304, 1, PULL1)," &
" 306 (BC_1, IO115, input, X)," &
" 307 (BC_1, *, controlr, 1)," &
" 308 (BC_1, IO116, output3, X, 307, 1, PULL1)," &
" 309 (BC_1, IO116, input, X)," &
" 310 (BC_1, *, controlr, 1)," &
" 311 (BC_1, IO117, output3, X, 310, 1, PULL1)," &
" 312 (BC_1, IO117, input, X)," &
" 313 (BC_1, *, controlr, 1)," &
" 314 (BC_1, IO118, output3, X, 313, 1, PULL1)," &
" 315 (BC_1, IO118, input, X)," &
" 316 (BC_1, *, controlr, 1)," &
" 317 (BC_1, IO119, output3, X, 316, 1, PULL1)," &
" 318 (BC_1, IO119, input, X)," &
" 319 (BC_1, *, controlr, 1)," &
" 320 (BC_1, IO120, output3, X, 319, 1, PULL1)," &
" 321 (BC_1, IO120, input, X)," &
" 322 (BC_1, *, controlr, 1)," &
" 323 (BC_1, IO121, output3, X, 322, 1, PULL1)," &
" 324 (BC_1, IO121, input, X)," &
" 325 (BC_1, *, controlr, 1)," &
" 326 (BC_1, IO123, output3, X, 325, 1, PULL1)," &
" 327 (BC_1, IO123, input, X)," &
" 328 (BC_1, *, controlr, 1)," &
" 329 (BC_1, IO124, output3, X, 328, 1, PULL1)," &
" 330 (BC_1, IO124, input, X)," &
" 331 (BC_1, *, controlr, 1)," &
" 332 (BC_1, IO125, output3, X, 331, 1, PULL1)," &
" 333 (BC_1, IO125, input, X)," &
" 334 (BC_1, *, controlr, 1)," &
" 335 (BC_1, IO126, output3, X, 334, 1, PULL1)," &
" 336 (BC_1, IO126, input, X)," &
" 337 (BC_1, *, controlr, 1)," &
" 338 (BC_1, IO127, output3, X, 337, 1, PULL1)," &
" 339 (BC_1, IO127, input, X)," &
" 340 (BC_1, *, controlr, 1)," &
" 341 (BC_1, IO128, output3, X, 340, 1, PULL1)," &
" 342 (BC_1, IO128, input, X)," &
" 343 (BC_1, *, internal, X)";
--end boundary register
attribute DESIGN_WARNING of XC4005XL_PQ160 : entity is
"CCLK and DONE are not represented in BOUNDARY_REGISTER." &
"This BSDL file must be modified by the FPGA designer in order to" &
"reflect post-configuration behavior (if any)." &
"If INIT has been high or floating since power-on or the last" &
"rising edge of PROGRAM, then the device may be in" &
"configuration mode in which case this file is not valid." &
"The output and tristate capture values are not valid until after" &
"the device is configured." &
"The fast output mux (where used) is not captured properly." &
"The tristate control is not captured properly when GTS is activated." &
"Some pins have both controlled and uncontrolled input paths.";
end XC4005XL_PQ160;