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BSDL File: RM41L232PZ Download View details  


----------------------------------------------------------------------
-- BSDL Description for RM41L232PZ                                  --          
-- Revised 14 May 2013                                              --
----------------------------------------------------------------------
--  Supported Devices: RM41L232PZ Revision 0.1                      --
----------------------------------------------------------------------
--  Created by    : Texas Instruments Incorporated                  --
--                : Chuck Davenport                                 --
--  BSDL Revision : 0.1 originally created                          --
--                                                                  --
--  BSDL Status   : Created                                         --
--  Date Created  : 06 October 2014                                 --
--  Revision      : 0.1                                             --
----------------------------------------------------------------------
--                                                                  --
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--             Copyright (c) 2012, Texas Instruments Incorporated            --
-------------------------------------------------------------------


entity RM41L232PZ is

-- This section identifies the default device package selected.

  generic (PHYSICAL_PIN_MAP: string:= "pkg_lead_100PZA");   
  
-- This section declares all the ports in the design.

  port (
         GIOA_0               : inout     bit;      
         GIOA_1               : inout     bit;      
         GIOA_2               : inout     bit;      
         GIOA_3               : inout     bit;      
         GIOA_4               : inout     bit;      
         GIOA_5               : inout     bit;      
         NHET_22              : inout     bit;      
         GIOA_6               : inout     bit;           
         GIOA_7               : inout     bit;      
         NHET_0               : inout     bit;      
         NHET_2               : inout     bit;      
         SPI2nCS_0            : inout     bit;      
         TEST                 : in        bit;      
         NHET_4               : inout     bit;      
         NHET_6               : inout     bit;      
         MIBSPI1nCS_2         : inout     bit;      
         nPORRST              : in        bit;
         SPI3SOMI             : inout     bit; 
         SPI3SIMO             : inout     bit;
         SPI3CLK              : inout     bit;
         SPI3nENA             : inout     bit;
         SPI3nCS0             : inout     bit;    
         MIBSPI1nCS_3         : inout     bit;      
         ADEVT                : inout     bit;      
         CAN1TX               : inout     bit;      
         CAN1RX               : inout     bit;      
         NHET_24              : inout     bit;      
         MIBSPI1SIMO          : inout     bit;      
         MIBSPI1SOMI          : inout     bit;      
         MIBSPI1CLK           : inout     bit;      
         MIBSPI1nENA          : inout     bit;      
         SPI2SOMI             : inout     bit;      
         SPI2SIMO             : inout     bit;      
         SPI2CLK              : inout     bit;      
         MIBSPI1nCS_0         : inout     bit;      
         NHET_8               : inout     bit;      
         TMS                  : in        bit;      
         nTRST                : in        bit;      
         TDI                  : in        bit;      
         TDO                  : out       bit;      
         TCK                  : in        bit;            
         nRST                 : inout     bit;      
         nERROR               : inout     bit;      
         NHET_10              : inout     bit;      
         ECLK                 : inout     bit;      
         NHET_12              : inout     bit;      
         NHET_14              : inout     bit;      
         CAN2TX               : inout     bit;      
         CAN2RX               : inout     bit;      
         MIBSPI1nCS_1         : inout     bit;      
         LINRX                : inout     bit;      
         LINTX                : inout     bit;
         NHET_16              : inout     bit;
         NHET_18              : inout     bit;       
         VCC_4                : linkage   bit;      
         VCCAD_1              : linkage   bit;             
         ADIN_4               : linkage   bit;      
         ADIN_1               : linkage   bit;      
         ADIN_2               : linkage   bit;          
         VSS_11               : linkage   bit;      
         KELVIN_GND           : linkage   bit;            
         VCC_5                : linkage   bit;      
         VCC_3                : linkage   bit;      
         VSS_17               : linkage   bit;      
         ADIN_21              : linkage   bit;        
         VSS_14               : linkage   bit;      
         ADIN_5               : linkage   bit;      
         ADIN_16              : linkage   bit;        
         VCC_14               : linkage   bit;      
         ADIN_8               : linkage   bit;      
         ADIN_20              : linkage   bit;         
         ADIN_7               : linkage   bit;       
         VSS_3                : linkage   bit;          
         VCC_12               : linkage   bit;      
         VCCIO_6              : linkage   bit;      
         VCCIO_4              : linkage   bit;           
         ADIN_10              : linkage   bit;      
         ADIN_9               : linkage   bit;        
         VCCP_1               : linkage   bit;      
         VSS_8                : linkage   bit;      
         FLTP1                : linkage   bit;      
         VCC_6                : linkage   bit;            
         ADIN_3               : linkage   bit;            
         VSS_4                : linkage   bit;           
         VSS_6                : linkage   bit;      
         ADIN_6               : linkage   bit;             
         VSS_5                : linkage   bit;
         OSCIN                : linkage   bit;       
         OSCOUT               : linkage   bit;      
         VSS_18               : linkage   bit;      
         ADIN_17              : linkage   bit;      
         ADIN_11              : linkage   bit;      
         VCCIO_3              : linkage   bit;            
         VSSAD_1              : linkage   bit;       
         VCC_10               : linkage   bit;           
         VCCIO_0              : linkage   bit;        
         FLTP2                : linkage   bit; 
         RTCK                 : linkage   bit;        
         ADIN_0               : linkage   bit;      
         VSS_21               : linkage   bit    
	);
   use STD_1149_1_2001.all;

   attribute COMPONENT_CONFORMANCE of RM41L232PZ: entity is "STD_1149_1_2001";

   attribute PIN_MAP of RM41L232PZ: entity is PHYSICAL_PIN_MAP;

-- This section specifies the pin map for each port.
    
    constant pkg_lead_100: PIN_MAP_STRING :=
     
             
         "GIOA_0                : 1," &               
         "GIOA_1                : 2," &               
         "FLTP1                 : 3," &               
         "FLTP2                 : 4," &               
         "GIOA_2                : 5," &
         "VCCIO_0               : 6," &                
         "VSS_4                 : 7," &               
         "GIOA_3                : 8," &               
         "GIOA_4                : 9," &               
         "GIOA_5                : 10," &              
         "NHET_22               : 11," &              
         "GIOA_6                : 12," &              
         "VCC_3                 : 13," &              
         "OSCIN                 : 14," &              
         "KELVIN_GND            : 15," &              
         "OSCOUT                : 16," &              
         "VSS_5                 : 17," &              
         "GIOA_7                : 18," &              
         "NHET_0                : 19," &              
         "VSS_6                 : 20," &              
         "VCC_4                 : 21," &              
         "NHET_2                : 22," &              
         "SPI2nCS_0             : 23," &              
         "TEST                  : 24," &              
         "NHET_4                : 25," &              
         "NHET_6                : 26," &              
         "MIBSPI1nCS_2          : 27," &              
         "VCCIO_4               : 28," &              
         "VSS_8                 : 29," &              
         "VCC_5                 : 30," &              
         "nPORRST               : 31," &              
         "VCC_6                 : 32," &              
         "VSS_11                : 33," &              
         "SPI3SOMI              : 34," &              
         "SPI3SIMO              : 35," &              
         "SPI3CLK               : 36," &
         "SPI3nENA              : 37," &
         "SPI3nCS0              : 38," &               
         "MIBSPI1nCS_3          : 39," &  
         "ADIN_16               : 40," &
         "ADIN_17               : 41," &
         "ADIN_0                : 42," &              
         "ADIN_7                : 43," &              
         "ADIN_20               : 44," &              
         "ADIN_21               : 45," &              
         "VCCAD_1               : 46," &              
         "VSSAD_1               : 47," &              
         "ADIN_9                : 48," &              
         "ADIN_1                : 49," &              
         "ADIN_10               : 50," &              
         "ADIN_2                : 51," &              
         "ADIN_3                : 52," &              
         "ADIN_11               : 53," &              
         "ADIN_4                : 54," &              
         "ADIN_5                : 55," &              
         "ADIN_6                : 56," &
         "ADIN_8                : 57," &              
         "ADEVT                 : 58," &               
         "VSS_3                 : 59," &              
         "VCCIO_3               : 60," &              
         "VCC_10                : 61," &              
         "CAN1TX                : 62," &              
         "CAN1RX                : 63," &              
         "NHET_24               : 64," &              
         "MIBSPI1SIMO           : 65," &              
         "MIBSPI1SOMI           : 66," &              
         "MIBSPI1CLK            : 67," &              
         "MIBSPI1nENA           : 68," &              
         "SPI2SOMI              : 69," &              
         "SPI2SIMO              : 70," &              
         "SPI2CLK               : 71," &              
         "VSS_14                : 72," &              
         "MIBSPI1nCS_0          : 73," &              
         "NHET_8                : 74," &              
         "TMS                   : 75," &              
         "nTRST                 : 76," &              
         "TDI                   : 77," &              
         "TDO                   : 78," &              
         "TCK                   : 79," &              
         "RTCK                  : 80," &              
         "nRST                  : 81," &              
         "nERROR                : 82," &              
         "NHET_10               : 83," &              
         "ECLK                  : 84," &              
         "VCCIO_6               : 85," &              
         "VSS_17                : 86," &              
         "VSS_18                : 87," &              
         "VCC_12                : 88," &              
         "NHET_12               : 89," &              
         "NHET_14               : 90," &              
         "CAN2TX                : 91," &              
         "CAN2RX                : 92," &              
         "MIBSPI1nCS_1          : 93," &              
         "LINRX                 : 94," &              
         "LINTX                 : 95," &              
         "VCCP_1                : 96," &              
         "NHET_16               : 97," &              
         "NHET_18               : 98," &              
         "VCC_14                : 99," &              
         "VSS_21                : 100";               

-- This section specifies the TAP ports. For the TAP TCK port, the parameters in
-- the brackets are:
--        First Field : Maximum  TCK frequency.
--        Second Field: Allowable states TCK may be stopped in.
   attribute TAP_SCAN_CLOCK of TCK  : signal is (10.0e6, BOTH);
   attribute TAP_SCAN_IN    of TDI  : signal is true;
   attribute TAP_SCAN_MODE  of TMS  : signal is true;
   attribute TAP_SCAN_OUT   of TDO  : signal is true;
   attribute TAP_SCAN_RESET of nTRST: signal is true;

-- Specifies the compliance enable patterns for the design. It lists a set of
-- design ports and the values that they should be set to, in order to enable
-- compliance to IEEE Std 1149.1
   attribute COMPLIANCE_PATTERNS of RM41L232PZ: entity is
        "(nPORRST, TEST) (10)";

-- Specifies the number of bits in the instruction register.

   attribute INSTRUCTION_LENGTH of RM41L232PZ: entity is 6;

-- Specifies the boundary-scan instructions implemented in the design and their
-- opcodes.

   attribute INSTRUCTION_OPCODE of RM41L232PZ: entity is
     "IDCODE  (000100),"&
     "BYPASS  (111111)," &
     "EXTEST  (011000)," &
     "SAMPLE  (011011)," &
     "PRELOAD (011011)," &
     "HIGHZ   (011110)";
    
-- Specifies the bit pattern that is loaded into the instruction register when
-- the TAP controller passes through the Capture-IR state. The standard mandates
-- that the two LSBs must be "01". The remaining bits are design specific.

   attribute INSTRUCTION_CAPTURE of RM41L232PZ : entity is "000001";

   attribute IDCODE_REGISTER     of RM41L232PZ  : entity is
      "XXXX" &                  -- Version
      "1011100101110001" &      -- Part Number
      "00000010111" &           -- Manufacturer ID
      "1";                      -- Required by the IEEE Std 1149.1 - 1990

-- This section specifies the test data register placed between TDI and TDO for
-- each implemented instruction.

   attribute REGISTER_ACCESS of RM41L232PZ: entity is
        "BYPASS   (BYPASS, HIGHZ)," &
        "DEVICE_ID (IDCODE),       " &
        "BOUNDARY (EXTEST, SAMPLE, PRELOAD)";

-- Specifies the length of the boundary scan register.

   attribute BOUNDARY_LENGTH of RM41L232PZ: entity is 137;

-- The following list specifies the characteristics of each cell in the boundary
-- scan register from TDI to TDO. The following is a description of the label
-- fields:
--      num     : Is the cell number.
--      cell    : Is the cell type as defined by the standard.
--      port    : Is the design port name. Control cells do not have a port
--                name.
--      function: Is the function of the cell as defined by the standard. Is one
--                of input, output2, output3, bidir, control or controlr.
--      safe    : Specifies the value that the BSR cell should be loaded with
--                for safe operation when the software might otherwise choose a
--                random value.
--      ccell   : The control cell number. Specifies the control cell that
--                drives the output enable for this port.
--      disval  : Specifies the value that is loaded into the control cell to
--                disable the output enable for the corresponding port.
--      rslt    : Resulting state. Shows the state of the driver when it is
--                disabled.

   attribute BOUNDARY_REGISTER of RM41L232PZ: entity is
--
--    num   cell     port       	   function    safe    [ccell  disval  rslt]
--
     "136   ( BC_2,  *,                    internal,    X),                         " &              
     "135   ( BC_2,  *,                    internal,    X),                         " &              
     "134   ( BC_2,  *,                    control,     1),                         " &              
     "133   ( BC_7,  GIOA_0,               bidir,       X,      134,    1,     Z),  " &            
     "132   ( BC_2,  *,                    internal,    X),                         " &              
     "131   ( BC_2,  *,                    internal,    X),                         " &              
     "130   ( BC_2,  *,                    internal,    X),                         " &              
     "129   ( BC_2,  *,                    internal,    X),                         " &              
     "128   ( BC_2,  *,                    control,     1),                         " &              
     "127   ( BC_7,  GIOA_1,               bidir,       X,      128,    1,     Z),  " &            
     "126   ( BC_2,  *,                    internal,    X),                         " &              
     "125   ( BC_2,  *,                    internal,    X),                         " &              
     "124   ( BC_2,  *,                    control,     1),                         " &              
     "123   ( BC_7,  GIOA_2,               bidir,       X,      124,    1,     Z),  " &            
     "122   ( BC_2,  *,                    control,     1),                         " &              
     "121   ( BC_7,  GIOA_3,               bidir,       X,      122,    1,     Z),  " &            
     "120   ( BC_2,  *,                    control,     1),                         " &              
     "119   ( BC_7,  GIOA_4,               bidir,       X,      120,    1,     Z),  " &            
     "118   ( BC_2,  *,                    control,     1),                         " &              
     "117   ( BC_7,  GIOA_5,               bidir,       X,      118,    1,     Z),  " &            
     "116   ( BC_2,  *,                    control,     1),                         " &              
     "115   ( BC_7,  NHET_22,              bidir,       X,      116,    1,     Z),  " &            
     "114   ( BC_2,  *,                    control,     1),                         " &              
     "113   ( BC_7,  GIOA_6,               bidir,       X,      114,    1,     Z),  " &            
     "112   ( BC_2,  *,                    control,     1),                         " &              
     "111   ( BC_7,  GIOA_7,               bidir,       X,      112,    1,     Z),  " &            
     "110   ( BC_2,  *,                    internal,    X),                         " &              
     "109   ( BC_2,  *,                    internal,    X),                         " &              
     "108   ( BC_2,  *,                    internal,    X),                         " &              
     "107   ( BC_2,  *,                    internal,    X),                         " &              
     "106   ( BC_2,  *,                    control,     1),                         " &              
     "105   ( BC_7,  NHET_0,               bidir,       X,      106,    1,     Z),  " &            
     "104   ( BC_2,  *,                    control,     1),                         " &              
     "103   ( BC_7,  NHET_2,               bidir,       X,      104,    1,     Z),  " &            
     "102   ( BC_2,  *,                    internal,    X),                         " &              
     "101   ( BC_2,  *,                    internal,    X),                         " &              
     "100   ( BC_2,  *,                    control,     1),                         " &              
     "99    ( BC_7,  SPI2NCS_0,            bidir,       X,      100,    1,     Z),  " &            
     "98    ( BC_2,  *,                    internal,    X),                         " &              
     "97    ( BC_2,  *,                    internal,    X),                         " &              
     "96    ( BC_2,  *,                    internal,    X),                         " &              
     "95    ( BC_2,  *,                    internal,    X),                         " &              
     "94    ( BC_2,  *,                    control,     1),                         " &              
     "93    ( BC_7,  NHET_4,               bidir,       X,      94,     1,     Z),  " &            
     "92    ( BC_2,  *,                    internal,    X),                         " &              
     "91    ( BC_2,  *,                    internal,    X),                         " &              
     "90    ( BC_2,  *,                    control,     1),                         " &              
     "89    ( BC_7,  NHET_6,               bidir,       X,      90,     1,     Z),  " &            
     "88    ( BC_2,  *,                    internal,    X),                         " &              
     "87    ( BC_2,  *,                    internal,    X),                         " &              
     "86    ( BC_2,  *,                    control,     1),                         " &              
     "85    ( BC_7,  MIBSPI1NCS_2,         bidir,       X,      86,     1,     Z),  " &            
     "84    ( BC_2,  *,                    internal,    X),                         " &              
     "83    ( BC_2,  *,                    internal,    X),                         " &              
     "82    ( BC_2,  *,                    control,     1),                         " &              
     "81    ( BC_7,  SPI3SOMI,             bidir,       X,      82,     1,     Z),  " &            
     "80    ( BC_2,  *,                    control,     1),                         " &              
     "79    ( BC_7,  SPI3SIMO,             bidir,       X,      80,     1,     Z),  " &            
     "78    ( BC_2,  *,                    control,     1),                         " &              
     "77    ( BC_7,  SPI3CLK,              bidir,       X,      78,     1,     Z),  " &              
     "76    ( BC_2,  *,                    control,     1),                         " &              
     "75    ( BC_7,  SPI3nENA,             bidir,       X,      76,     1,     Z),  " &              
     "74    ( BC_2,  *,                    control,     1),                         " &              
     "73    ( BC_7,  SPI3nCS0,             bidir,       X,      74,     1,     Z),  " &              
     "72    ( BC_2,  *,                    control,     1),                         " &              
     "71    ( BC_7,  MIBSPI1NCS_3,         bidir,       X,      72,     1,     Z),  " &            
     "70    ( BC_2,  *,                    control,     1),                         " &              
     "69    ( BC_7,  ADEVT,                bidir,       X,      70,     1,     Z),  " &            
     "68    ( BC_2,  *,                    control,     1),                         " &              
     "67    ( BC_7,  CAN1TX,               bidir,       X,      68,     1,     Z),  " &            
     "66    ( BC_2,  *,                    control,     1),                         " &              
     "65    ( BC_7,  CAN1RX,               bidir,       X,      66,     1,     Z),  " &            
     "64    ( BC_2,  *,                    control,     1),                         " &              
     "63    ( BC_7,  NHET_24,              bidir,       X,      64,     1,     Z),  " &            
     "62    ( BC_2,  *,                    internal,    X),                         " &              
     "61    ( BC_2,  *,                    internal,    X),                         " &              
     "60    ( BC_2,  *,                    control,     1),                         " &              
     "59    ( BC_7,  MIBSPI1SIMO,          bidir,       X,      60,     1,     Z),  " &            
     "58    ( BC_2,  *,                    control,     1),                         " &              
     "57    ( BC_7,  MIBSPI1SOMI,          bidir,       X,      58,     1,     Z),  " &            
     "56    ( BC_2,  *,                    control,     1),                         " &              
     "55    ( BC_7,  MIBSPI1CLK,           bidir,       X,      56,     1,     Z),  " &            
     "54    ( BC_2,  *,                    control,     1),                         " &              
     "53    ( BC_7,  MIBSPI1NENA,          bidir,       X,      54,     1,     Z),  " &            
     "52    ( BC_2,  *,                    internal,    X),                         " &              
     "51    ( BC_2,  *,                    internal,    X),                         " &              
     "50    ( BC_2,  *,                    control,     1),                         " &              
     "49    ( BC_7,  SPI2SOMI,             bidir,       X,      50,     1,     Z),  " &            
     "48    ( BC_2,  *,                    control,     1),                         " &              
     "47    ( BC_7,  SPI2SIMO,             bidir,       X,      48,     1,     Z),  " &            
     "46    ( BC_2,  *,                    control,     1),                         " &              
     "45    ( BC_7,  SPI2CLK,              bidir,       X,      46,     1,     Z),  " &            
     "44    ( BC_2,  *,                    control,     1),                         " &              
     "43    ( BC_7,  MIBSPI1NCS_0,         bidir,       X,      44,     1,     Z),  " &            
     "42    ( BC_2,  *,                    control,     1),                         " &              
     "41    ( BC_7,  NHET_8,               bidir,       X,      42,     1,     Z),  " &            
     "40    ( BC_2,  *,                    internal,    X),                         " &              
     "39    ( BC_2,  *,                    internal,    X),                         " &            
     "38    ( BC_2,  *,                    control,     1),                         " &              
     "37    ( BC_7,  nRST,                 bidir,       X,      38,     1,     Z),  " &            
     "36    ( BC_2,  *,                    control,     1),                         " &              
     "35    ( BC_7,  nERROR,               bidir,       X,      36,     1,     Z),  " &            
     "34    ( BC_2,  *,                    control,     1),                         " &              
     "33    ( BC_7,  NHET_10,              bidir,       X,      34,     1,     Z),  " &            
     "32    ( BC_2,  *,                    control,     1),                         " &              
     "31    ( BC_7,  ECLK,                 bidir,       X,      32,     1,     Z),  " &            
     "30    ( BC_2,  *,                    control,     1),                         " &              
     "29    ( BC_7,  NHET_12,              bidir,       X,      30,     1,     Z),  " &            
     "28    ( BC_2,  *,                    control,     1),                         " &              
     "27    ( BC_7,  NHET_14,              bidir,       X,      28,     1,     Z),  " &            
     "26    ( BC_2,  *,                    internal,    X),                         " &              
     "25    ( BC_2,  *,                    internal,    X),                         " &              
     "24    ( BC_2,  *,                    internal,    X),                         " &              
     "23    ( BC_2,  *,                    internal,    X),                         " &              
     "22    ( BC_2,  *,                    control,     1),                         " &              
     "21    ( BC_7,  CAN2TX,               bidir,       X,      22,     1,     Z),  " &            
     "20    ( BC_2,  *,                    control,     1),                         " &              
     "19    ( BC_7,  CAN2RX,               bidir,       X,      20,     1,     Z),  " &            
     "18    ( BC_2,  *,                    control,     1),                         " &              
     "17    ( BC_7,  MIBSPI1nCS_1,         bidir,       X,      18,     1,     Z),  " &            
     "16    ( BC_2,  *,                    control,     1),                         " &              
     "15    ( BC_7,  LINRX,                bidir,       X,      16,     1,     Z),  " &            
     "14    ( BC_2,  *,                    control,     1),                         " &              
     "13    ( BC_7,  LINTX,                bidir,       X,      14,     1,     Z),  " &            
     "12    ( BC_2,  *,                    internal,    X),                         " &              
     "11    ( BC_2,  *,                    internal,    X),                         " &              
     "10    ( BC_2,  *,                    internal,    X),                         " &              
     "9     ( BC_2,  *,                    internal,    X),                         " &              
     "8     ( BC_2,  *,                    control,     1),                         " &              
     "7     ( BC_7,  NHET_16,              bidir,       X,       8,    1,      Z),  " &              
     "6     ( BC_2,  *,                    control,     1),                         " &             
     "5     ( BC_7,  NHET_18,              bidir,       X,       6,    1,      Z),  " &               
     "4     ( BC_2,  *,                    internal,    1),                         " &               
     "3     ( BC_2,  *,                    internal,    1),                         " &              
     "2     ( BC_2,  *,                    internal,    1),                         " &              
     "1     ( BC_2,  *,                    internal,    1),                         " &              
     "0     ( BC_2,  *,                    internal,    1)                          ";               

 attribute DESIGN_WARNING of RM41L232PZ : entity is
      "According to simulation, BSD JTAG TAP may not work correctly unless  "&
      " device has completed RESET sequence first.                          "&
      "Forcing PORz low then release (no clock pulses required) would meet  "&
      " the requirement.                                                    "&
      "                                                                     "&
      "In order to enter bscan mode correctly, TMS must be low at the       "&
      "rising edge of TRSTz and at least one cycle after TRSTz is high.     ";

 end RM41L232PZ;

This library contains 10579 BSDL files (for 7657 distinct entities) from 71 vendors
Last BSDL model (CYCLONE_10_10CX220F780) was added on May 21, 2018 13:01
info@bsdl.info