-- ***********************************************************************
-- BSDL file for design i.MX28
-- Designer: michael sang
-- Company: freescale Electronics Pte Ltd
-- Date: TUE April 14 2009
-- Revision: Fix error of Bidir and Control cell reversed order, by Aaron Hao (b04282@freescale.com)
-- ***********************************************************************
entity catskills is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "BGA");
-- This section declares all the ports in the design.
port (
PAD_SSP3_SCK : inout bit;
PAD_SSP2_SCK : inout bit;
PAD_SSP0_CMD : inout bit;
PAD_SSP0_DATA3 : inout bit;
PAD_SSP0_SCK : inout bit;
PAD_SSP1_SCK : inout bit;
PAD_SSP3_MISO : inout bit;
PAD_SSP2_MISO : inout bit;
PAD_SSP0_DATA7 : inout bit;
PAD_SSP0_DATA4 : inout bit;
PAD_SSP0_DATA0 : inout bit;
PAD_SSP1_CMD : inout bit;
PAD_SSP3_MOSI : inout bit;
PAD_SSP2_MOSI : inout bit;
PAD_SSP2_SS0 : inout bit;
PAD_SSP0_DATA5 : inout bit;
PAD_SSP0_DATA1 : inout bit;
PAD_I2C0_SCL : inout bit;
PAD_SSP1_DATA0 : inout bit;
PAD_SSP3_SS0 : inout bit;
PAD_SSP2_SS1 : inout bit;
PAD_SSP2_SS2 : inout bit;
PAD_SSP0_DATA6 : inout bit;
PAD_SSP0_DATA2 : inout bit;
PAD_SPDIF : inout bit;
PAD_I2C0_SDA : inout bit;
PAD_SSP0_DETECT : inout bit;
PAD_JTAG_TMS : in bit;
PAD_JTAG_TRST : in bit;
PAD_SSP1_DATA3 : inout bit;
PAD_ENET_CLK : inout bit;
PAD_ENET0_TX_CLK : inout bit;
PAD_ENET0_RX_EN : inout bit;
PAD_SAIF0_SDATA0 : inout bit;
PAD_SAIF1_SDATA0 : inout bit;
PAD_PWM3 : inout bit;
PAD_PWM4 : inout bit;
PAD_JTAG_TCK : in bit;
PAD_JTAG_TDI : in bit;
PAD_JTAG_TDO : out bit;
PAD_JTAG_RTCK : inout bit;
PAD_ENET0_TXD0 : inout bit;
PAD_ENET0_TXD1 : inout bit;
PAD_ENET0_RX_CLK : inout bit;
PAD_ENET0_TX_EN : inout bit;
PAD_AUART2_TX : inout bit;
PAD_AUART2_RX : inout bit;
PAD_SAIF0_BITCLK : inout bit;
PAD_EMI_D14 : inout bit;
PAD_EMI_DQM1 : inout bit;
PAD_EMI_D15 : inout bit;
PAD_ENET0_TXD2 : inout bit;
PAD_ENET0_TXD3 : inout bit;
PAD_ENET0_MDC : inout bit;
PAD_AUART0_RX : inout bit;
PAD_SAIF0_LRCLK : inout bit;
PAD_SAIF0_MCLK : inout bit;
PAD_EMI_D10 : inout bit;
PAD_EMI_D08 : inout bit;
PAD_ENET0_RXD0 : inout bit;
PAD_ENET0_RXD1 : inout bit;
PAD_ENET0_MDIO : inout bit;
PAD_AUART0_TX : inout bit;
PAD_AUART2_CTS : inout bit;
PAD_AUART2_RTS : inout bit;
PAD_EMI_D12 : inout bit;
PAD_EMI_D09 : inout bit;
PAD_EMI_D13 : inout bit;
PAD_ENET0_RXD2 : inout bit;
PAD_ENET0_RXD3 : inout bit;
PAD_ENET0_CRS : inout bit;
PAD_ENET0_COL : inout bit;
PAD_AUART1_RTS : inout bit;
PAD_AUART0_CTS : inout bit;
PAD_AUART0_RTS : inout bit;
PAD_EMI_D11 : inout bit;
PAD_EMI_DQS1N : inout bit;
PAD_EMI_DQS1 : inout bit;
PAD_LCD_WR_RWN : inout bit;
PAD_LCD_D00 : inout bit;
PAD_LCD_D01 : inout bit;
PAD_AUART1_TX : inout bit;
PAD_AUART1_CTS : inout bit;
PAD_AUART3_RTS : inout bit;
PAD_PWM0 : inout bit;
PAD_PWM2 : inout bit;
PAD_EMI_DDR_OPEN : inout bit;
PAD_EMI_DQS0N : inout bit;
PAD_EMI_DQS0 : inout bit;
PAD_LCD_VSYNC : inout bit;
PAD_LCD_D02 : inout bit;
PAD_LCD_D03 : inout bit;
PAD_AUART1_RX : inout bit;
PAD_AUART3_TX : inout bit;
PAD_AUART3_CTS : inout bit;
PAD_PWM1 : inout bit;
PAD_GPMI_RDY3 : inout bit;
PAD_GPMI_RESETN : inout bit;
PAD_EMI_D06 : inout bit;
PAD_EMI_DDR_OPEN_FB : inout bit;
PAD_EMI_CLKN : inout bit;
PAD_EMI_CLK : inout bit;
PAD_LCD_HSYNC : inout bit;
PAD_LCD_D04 : inout bit;
PAD_LCD_D05 : inout bit;
PAD_LCD_RS : inout bit;
PAD_AUART3_RX : inout bit;
PAD_LCD_RESET : inout bit;
PAD_GPMI_CE2N : inout bit;
PAD_GPMI_RDY2 : inout bit;
PAD_GPMI_CE3N : inout bit;
PAD_EMI_D01 : inout bit;
PAD_EMI_DQM0 : inout bit;
PAD_EMI_D07 : inout bit;
PAD_LCD_DOTCLK : inout bit;
PAD_LCD_D06 : inout bit;
PAD_LCD_ENABLE : inout bit;
PAD_GPMI_RDY0 : inout bit;
PAD_GPMI_CE0N : inout bit;
PAD_GPMI_RDY1 : inout bit;
PAD_GPMI_CE1N : inout bit;
PAD_EMI_A14 : inout bit;
PAD_EMI_A07 : inout bit;
PAD_EMI_BA2 : inout bit;
PAD_EMI_D03 : inout bit;
PAD_EMI_D00 : inout bit;
PAD_LCD_D07 : inout bit;
PAD_LCD_D08 : inout bit;
PAD_LCD_D09 : inout bit;
PAD_LCD_RD_E : inout bit;
PAD_LCD_CS : inout bit;
PAD_GPMI_ALE : inout bit;
PAD_GPMI_CLE : inout bit;
PAD_GPMI_WRN : inout bit;
PAD_EMI_CE1N : inout bit;
PAD_EMI_A09 : inout bit;
PAD_EMI_CE0N : inout bit;
PAD_EMI_D04 : inout bit;
PAD_EMI_D02 : inout bit;
PAD_EMI_D05 : inout bit;
PAD_LCD_D10 : inout bit;
PAD_LCD_D11 : inout bit;
PAD_LCD_D17 : inout bit;
PAD_LCD_D20 : inout bit;
PAD_LCD_D23 : inout bit;
PAD_GPMI_RDN : inout bit;
PAD_GPMI_D05 : inout bit;
PAD_GPMI_D02 : inout bit;
PAD_EMI_A06 : inout bit;
PAD_EMI_A05 : inout bit;
PAD_EMI_RASN : inout bit;
PAD_EMI_ODT0 : inout bit;
PAD_LCD_D12 : inout bit;
PAD_LCD_D13 : inout bit;
PAD_LCD_D16 : inout bit;
PAD_LCD_D19 : inout bit;
PAD_LCD_D22 : inout bit;
PAD_GPMI_D07 : inout bit;
PAD_GPMI_D04 : inout bit;
PAD_GPMI_D01 : inout bit;
PAD_EMI_A13 : inout bit;
PAD_EMI_A11 : inout bit;
PAD_EMI_A03 : inout bit;
PAD_EMI_BA1 : inout bit;
PAD_EMI_CKE : inout bit;
PAD_EMI_WEN : inout bit;
PAD_EMI_BA0 : inout bit;
PAD_EMI_ODT1 : inout bit;
PAD_LCD_D14 : inout bit;
PAD_LCD_D15 : inout bit;
PAD_LCD_D18 : inout bit;
PAD_LCD_D21 : inout bit;
PAD_GPMI_D06 : inout bit;
PAD_GPMI_D03 : inout bit;
PAD_GPMI_D00 : inout bit;
PAD_EMI_A08 : inout bit;
PAD_EMI_A04 : inout bit;
PAD_EMI_A12 : inout bit;
PAD_EMI_A01 : inout bit;
PAD_EMI_A10 : inout bit;
PAD_EMI_A02 : inout bit;
PAD_EMI_A00 : inout bit;
PAD_EMI_CASN : inout bit;
PAD_EMI_VREF1 : linkage bit;
PAD_VDDXTAL : linkage bit;
PAD_LRADC0 : linkage bit;
PAD_VDDD : linkage bit_vector(0 to 6);
PAD_LRADC2 : linkage bit;
PAD_USB1DM : linkage bit;
PAD_VDDIO_EMI : linkage bit_vector(0 to 10);
PAD_VDD5V : linkage bit;
PAD_RESETN : linkage bit;
PAD_VDDIO33 : linkage bit_vector(0 to 8);
PAD_VDDIO_EMIQ : linkage bit_vector(0 to 2);
PAD_DCDC_VDDD : linkage bit;
PAD_EMI_VREF0 : linkage bit;
PAD_LRADC3 : linkage bit;
PAD_XTALO : linkage bit;
PAD_BATTERY : linkage bit;
PAD_VSSIO_EMI : linkage bit_vector(0 to 10);
PAD_VDD1P5 : linkage bit;
PAD_LRADC1 : linkage bit;
PAD_DEBUG : linkage bit;
PAD_DCDC_LP : linkage bit;
PAD_DCDC_BATT : linkage bit;
PAD_VDDIO33_EMI : linkage bit;
PAD_HSADC0 : linkage bit;
PAD_XTALI : linkage bit;
PAD_VSSA1 : linkage bit;
PAD_USB1DP : linkage bit;
PAD_RTC_XTALO : linkage bit;
PAD_VDDA1 : linkage bit;
PAD_LRADC5 : linkage bit;
PAD_VDDIO18 : linkage bit_vector(0 to 3);
PAD_TESTMODE : linkage bit;
PAD_VSSA2 : linkage bit;
PAD_LRADC4 : linkage bit;
PAD_VDD4P2 : linkage bit;
PAD_DCDC_VDDA : linkage bit;
PAD_PSWITCH : linkage bit;
PAD_DCDC_VDDIO : linkage bit;
PAD_LRADC6 : linkage bit;
PAD_USB0DP : linkage bit;
PAD_DCDC_LN1 : linkage bit;
PAD_RTC_XTALI : linkage bit;
PAD_DCDC_GND : linkage bit;
PAD_VSS : linkage bit_vector(0 to 22);
PAD_USB0DM : linkage bit
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of catskills: entity is "STD_1149_1_2001";
attribute PIN_MAP of catskills: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant BGA: PIN_MAP_STRING :=
" PAD_PWM1: L7," &
" PAD_LCD_D11: R2," &
" PAD_ENET0_TXD3: G2," &
" PAD_SAIF0_SDATA0: E7," &
" PAD_ENET0_TX_EN: F4," &
" PAD_EMI_A02: U14," &
" PAD_ENET0_TXD0: F1," &
" PAD_LCD_D17: R3," &
" PAD_EMI_D14: F13," &
" PAD_EMI_CE0N: P12," &
" PAD_SSP0_DATA0: B6," &
" PAD_SSP0_DATA3: A5," &
" PAD_EMI_D01: M13," &
" PAD_AUART0_TX: H5," &
" PAD_SSP1_DATA3: E1," &
" PAD_GPMI_D03: U7," &
" PAD_EMI_D04: P13," &
" PAD_AUART1_CTS: K5," &
" PAD_LCD_RS: M4," &
" PAD_GPMI_WRN: P8," &
" PAD_LCD_ENABLE: N5," &
" PAD_SPDIF: D7," &
" PAD_SSP2_MOSI: C3," &
" PAD_SSP0_DATA5: C5," &
" PAD_EMI_CKE: T13," &
" PAD_ENET0_RXD0: H1," &
" PAD_SSP2_SCK: A3," &
" PAD_EMI_A00: U15," &
" PAD_SSP0_DATA7: B4," &
" PAD_GPMI_CE3N: M9," &
" PAD_LCD_WR_RWN: K1," &
" PAD_SSP0_DATA1: C6," &
" PAD_EMI_DQM0: M15," &
" PAD_EMI_D06: L14," &
" PAD_ENET0_CRS: J3," &
" PAD_LCD_DOTCLK: N1," &
" PAD_I2C0_SDA: D8," &
" PAD_EMI_D11: J14," &
" PAD_EMI_DQS0N: K16," &
" PAD_EMI_A04: U10," &
" PAD_EMI_DDR_OPEN_FB: L15," &
" PAD_LCD_D08: P2," &
" PAD_EMI_CLKN: L16," &
" PAD_GPMI_RDY2: M8," &
" PAD_EMI_BA2: N12," &
" PAD_LCD_D20: R4," &
" PAD_LCD_D01: K3," &
" PAD_LCD_D14: U2," &
" PAD_EMI_ODT1: T17," &
" PAD_LCD_D02: L2," &
" PAD_EMI_CE1N: P9," &
" PAD_JTAG_RTCK: E14," &
" PAD_ENET0_TX_CLK: E3," &
" PAD_LCD_HSYNC: M1," &
" PAD_LCD_D18: U4," &
" PAD_GPMI_D04: T7," &
" PAD_EMI_A14: N10," &
" PAD_ENET0_TXD2: G1," &
" PAD_GPMI_RDY0: N6," &
" PAD_LCD_CS: P5," &
" PAD_ENET0_RX_EN: E4," &
" PAD_SSP1_CMD: C1," &
" PAD_PWM3: E9," &
" PAD_AUART2_CTS: H6," &
" PAD_LCD_D13: T2," &
" PAD_GPMI_RESETN: L9," &
" PAD_EMI_RASN: R16," &
" PAD_EMI_D08: G16," &
" PAD_LCD_D00: K2," &
" PAD_SSP3_SCK: A2," &
" PAD_EMI_D12: H13," &
" PAD_ENET0_RX_CLK: F3," &
" PAD_GPMI_RDN: R6," &
" PAD_EMI_DQS1N: J16," &
" PAD_ENET0_RXD2: J1," &
" PAD_EMI_DDR_OPEN: K14," &
" PAD_SSP1_DATA0: D1," &
" PAD_LCD_D06: N2," &
" PAD_GPMI_D02: R8," &
" PAD_LCD_RD_E: P4," &
" PAD_SSP0_DATA6: D5," &
" PAD_LCD_D05: M3," &
" PAD_SSP0_DATA4: B5," &
" PAD_EMI_A08: U9," &
" PAD_AUART3_RX: M5," &
" PAD_SSP1_SCK: B1," &
" PAD_ENET_CLK: E2," &
" PAD_EMI_D00: N16," &
" PAD_EMI_D07: M17," &
" PAD_SAIF0_MCLK: G7," &
" PAD_ENET0_MDIO: H4," &
" PAD_EMI_WEN: T15," &
" PAD_EMI_A06: R9," &
" PAD_EMI_CASN: U16," &
" PAD_AUART1_RX: L4," &
" PAD_EMI_D02: P15," &
" PAD_EMI_A10: U13," &
" PAD_EMI_DQM1: F15," &
" PAD_EMI_DQS0: K17," &
" PAD_ENET0_COL: J4," &
" PAD_EMI_A01: U12," &
" PAD_ENET0_RXD1: H2," &
" PAD_LCD_D10: R1," &
" PAD_EMI_D05: P17," &
" PAD_SSP3_SS0: D2," &
" PAD_EMI_D10: G14," &
" PAD_SSP0_DETECT: D10," &
" PAD_AUART3_RTS: K6," &
" PAD_GPMI_D07: T6," &
" PAD_AUART3_TX: L5," &
" PAD_LCD_D16: T3," &
" PAD_EMI_BA0: T16," &
" PAD_EMI_D15: F17," &
" PAD_AUART2_RTS: H7," &
" PAD_EMI_ODT0: R17," &
" PAD_GPMI_D05: R7," &
" PAD_SSP3_MISO: B2," &
" PAD_GPMI_CE2N: M7," &
" PAD_SAIF0_BITCLK: F7," &
" PAD_SSP2_SS2: D4," &
" PAD_GPMI_D00: U8," &
" PAD_SSP0_DATA2: D6," &
" PAD_LCD_D03: L3," &
" PAD_ENET0_RXD3: J2," &
" PAD_LCD_RESET: M6," &
" PAD_EMI_CLK: L17," &
" PAD_EMI_A11: T10," &
" PAD_GPMI_RDY1: N8," &
" PAD_SAIF0_LRCLK: G6," &
" PAD_SSP2_SS0: C4," &
" PAD_LCD_D22: T5," &
" PAD_LCD_VSYNC: L1," &
" PAD_EMI_A12: U11," &
" PAD_AUART1_TX: K4," &
" PAD_ENET0_MDC: G4," &
" PAD_LCD_D21: U5," &
" PAD_EMI_A03: T11," &
" PAD_LCD_D07: P1," &
" PAD_EMI_A05: R11," &
" PAD_PWM2: K8," &
" PAD_EMI_A13: T9," &
" PAD_SSP0_CMD: A4," &
" PAD_AUART1_RTS: J5," &
" PAD_AUART2_TX: F5," &
" PAD_GPMI_CE0N: N7," &
" PAD_GPMI_ALE: P6," &
" PAD_PWM4: E10," &
" PAD_LCD_D19: T4," &
" PAD_GPMI_CLE: P7," &
" PAD_AUART2_RX: F6," &
" PAD_SSP2_SS1: D3," &
" PAD_GPMI_CE1N: N9," &
" PAD_GPMI_D06: U6," &
" PAD_PWM0: K7," &
" PAD_AUART0_RTS: J7," &
" PAD_LCD_D09: P3," &
" PAD_LCD_D12: T1," &
" PAD_EMI_D13: H17," &
" PAD_EMI_D09: H15," &
" PAD_AUART0_RX: G5," &
" PAD_SSP2_MISO: B3," &
" PAD_LCD_D15: U3," &
" PAD_SSP3_MOSI: C2," &
" PAD_LCD_D04: M2," &
" PAD_SAIF1_SDATA0: E8," &
" PAD_GPMI_D01: T8," &
" PAD_EMI_DQS1: J17," &
" PAD_AUART3_CTS: L6," &
" PAD_ENET0_TXD1: F2," &
" PAD_EMI_BA1: T12," &
" PAD_EMI_A07: N11," &
" PAD_SSP0_SCK: A6," &
" PAD_AUART0_CTS: J6," &
" PAD_GPMI_RDY3: L8," &
" PAD_EMI_D03: N14," &
" PAD_EMI_A09: P10," &
" PAD_I2C0_SCL: C7," &
" PAD_LCD_D23: R5," &
" PAD_EMI_VREF1: K13," &
" PAD_VDDXTAL: C12," &
" PAD_LRADC0: C15," &
" PAD_VDDD: (F10,F11,F12,G10,G11,G12,K12)," &
" PAD_JTAG_TMS: D12," &
" PAD_LRADC2: C8," &
" PAD_USB1DM: B8," &
" PAD_VDDIO_EMI: (G13,G15,G17,L13,M10,M11,M12,N13,N15,P11,R13)," &
" PAD_JTAG_TCK: E11," &
" PAD_VDD5V: E17," &
" PAD_RESETN: A14," &
" PAD_JTAG_TDI: E12," &
" PAD_VDDIO33: (A7,E6,E16,G3,H8,J8,J9,J10,N3)," &
" PAD_VDDIO_EMIQ: (J13,K15,R15)," &
" PAD_DCDC_VDDD: D17," &
" PAD_EMI_VREF0: R14," &
" PAD_LRADC3: D9," &
" PAD_XTALO: B12," &
" PAD_BATTERY: A15," &
" PAD_VSSIO_EMI: (F14,F16,H14,L12,M16,P14,P16,R10,R12,T14,U17)," &
" PAD_VDD1P5: D16," &
" PAD_LRADC1: C9," &
" PAD_DEBUG: B9," &
" PAD_DCDC_LP: A16," &
" PAD_DCDC_BATT: B15," &
" PAD_VDDIO33_EMI: N17," &
" PAD_HSADC0: B14," &
" PAD_XTALI: A12," &
" PAD_VSSA1: B13," &
" PAD_USB1DP: A8," &
" PAD_RTC_XTALO: C11," &
" PAD_VDDA1: C13," &
" PAD_LRADC5: D15," &
" PAD_VDDIO18: (F8,F9,G8,G9)," &
" PAD_TESTMODE: C10," &
" PAD_VSSA2: B11," &
" PAD_LRADC4: D13," &
" PAD_VDD4P2: A13," &
" PAD_DCDC_VDDA: B16," &
" PAD_PSWITCH: A11," &
" PAD_DCDC_VDDIO: C17," &
" PAD_LRADC6: C14," &
" PAD_USB0DP: B10," &
" PAD_DCDC_LN1: B17," &
" PAD_RTC_XTALI: D11," &
" PAD_JTAG_TRST: D14," &
" PAD_DCDC_GND: A17," &
" PAD_VSS: (A1,A9,B7,C16,E5,E15,H3,H9,H10,H11,H12,H16,J11,J12,J15,K9,K10,K11,L10,L11,M14,N4,U1)," &
" PAD_JTAG_TDO: E13," &
" PAD_USB0DM: A10" ;
attribute PORT_GROUPING of catskills : entity is
"DIFFERENTIAL_VOLTAGE (" &
"(PAD_EMI_DQS1, PAD_EMI_DQS1N)," &
"(PAD_EMI_DQS0, PAD_EMI_DQS0N)," &
"(PAD_EMI_CLK, PAD_EMI_CLKN))" ;
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of PAD_JTAG_TCK : signal is (2.000000e+07, BOTH);
attribute TAP_SCAN_IN of PAD_JTAG_TDI : signal is true;
attribute TAP_SCAN_MODE of PAD_JTAG_TMS : signal is true;
attribute TAP_SCAN_OUT of PAD_JTAG_TDO : signal is true;
attribute TAP_SCAN_RESET of PAD_JTAG_TRST: signal is true;
-- attribute COMPLIANCE_PATTERNS of catskills : entity is "(jtag_ctrl_pad) (0)";
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of catskills: entity is 4;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of catskills: entity is
"BYPASS (1111)," &
"EXTEST (0000)," &
"SAMPLE (0001)," &
"PRELOAD (0001)," &
"HIGHZ (0011)," &
"IDCODE (0010)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of catskills: entity is "0001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of catskills: entity is
--32'h0882401d
"00001000100000100100000000011101";
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of catskills: entity is
"BYPASS (BYPASS, HIGHZ)," &
"BOUNDARY (EXTEST, SAMPLE,PRELOAD)," &
"DEVICE_ID (IDCODE)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of catskills: entity is 350;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of catskills: entity is
--
-- num cell port function safe [ccell disval rslt]
--
" 349 (BC_8, PAD_SSP0_SCK , bidir, X,348 , 1, Z)," &
" 348 (BC_2, *, control, 1)," &
" 347 (BC_8, PAD_SSP0_DATA0 , bidir, X, 346 , 1, Z)," &
" 346 (BC_2, *, control, 1)," &
" 345 (BC_8, PAD_I2C0_SCL , bidir, X, 344 , 1, Z)," &
" 344 (BC_2, *, control, 1)," &
" 343 (BC_8, PAD_SSP0_DATA3 , bidir, X, 342 , 1, Z)," &
" 342 (BC_2, *, control, 1)," &
" 341 (BC_8, PAD_SSP0_DETECT , bidir, X, 340 , 1, Z)," &
" 340 (BC_2, *, control, 1)," &
" 339 (BC_8, PAD_SSP0_CMD , bidir, X, 338 , 1, Z)," &
" 338 (BC_2, *, control, 1)," &
" 337 (BC_8, PAD_SSP0_DATA4 , bidir, X, 336 , 1, Z)," &
" 336 (BC_2, *, control, 1)," &
" 335 (BC_8, PAD_PWM4 , bidir, X, 334 , 1, Z)," &
" 334 (BC_2, *, control, 1)," &
" 333 (BC_8, PAD_SSP2_SCK , bidir, X, 332 , 1, Z)," &
" 332 (BC_2, *, control, 1)," &
" 331 (BC_8, PAD_I2C0_SDA , bidir, X, 330 , 1, Z)," &
" 330 (BC_2, *, control, 1)," &
" 329 (BC_8, PAD_SSP0_DATA7 , bidir, X, 328 , 1, Z)," &
" 328 (BC_2, *, control, 1)," &
" 327 (BC_8, PAD_SSP0_DATA5 , bidir, X, 326 , 1, Z)," &
" 326 (BC_2, *, control, 1)," &
" 325 (BC_8, PAD_SPDIF , bidir, X, 324 , 1, Z)," &
" 324 (BC_2, *, control, 1)," &
" 323 (BC_8, PAD_SSP3_SCK , bidir, X, 322 , 1, Z)," &
" 322 (BC_2, *, control, 1)," &
" 321 (BC_8, PAD_PWM3 , bidir, X, 320 , 1, Z)," &
" 320 (BC_2, *, control, 1)," &
" 319 (BC_8, PAD_SSP2_MISO , bidir, X, 318 , 1, Z)," &
" 318 (BC_2, *, control, 1)," &
" 317 (BC_8, PAD_SSP0_DATA1 , bidir, X, 316 , 1, Z)," &
" 316 (BC_2, *, control, 1)," &
" 315 (BC_8, PAD_SSP2_MOSI , bidir, X, 314 , 1, Z)," &
" 314 (BC_2, *, control, 1)," &
" 313 (BC_8, PAD_SSP0_DATA2 , bidir, X, 312 , 1, Z)," &
" 312 (BC_2, *, control, 1)," &
" 311 (BC_8, PAD_SSP3_MISO , bidir, X, 310 , 1, Z)," &
" 310 (BC_2, *, control, 1)," &
" 309 (BC_8, PAD_SSP2_SS0 , bidir, X, 308 , 1, Z)," &
" 308 (BC_2, *, control, 1)," &
" 307 (BC_8, PAD_SSP0_DATA6 , bidir, X, 306 , 1, Z)," &
" 306 (BC_2, *, control, 1)," &
" 305 (BC_8, PAD_SSP2_SS1 , bidir, X, 304 , 1, Z)," &
" 304 (BC_2, *, control, 1)," &
" 303 (BC_8, PAD_SAIF1_SDATA0 , bidir, X, 302 , 1, Z)," &
" 302 (BC_2, *, control, 1)," &
" 301 (BC_8, PAD_SSP3_MOSI , bidir, X, 300 , 1, Z)," &
" 300 (BC_2, *, control, 1)," &
" 299 (BC_8, PAD_SSP1_SCK , bidir, X, 298 , 1, Z)," &
" 298 (BC_2, *, control, 1)," &
" 297 (BC_8, PAD_SAIF0_SDATA0 , bidir, X, 296 , 1, Z)," &
" 296 (BC_2, *, control, 1)," &
" 295 (BC_8, PAD_ENET0_TX_CLK , bidir, X, 294 , 1, Z)," &
" 294 (BC_2, *, control, 1)," &
" 293 (BC_8, PAD_SSP3_SS0 , bidir, X, 292 , 1, Z)," &
" 292 (BC_2, *, control, 1)," &
" 291 (BC_8, PAD_SAIF0_BITCLK , bidir, X, 290 , 1, Z)," &
" 290 (BC_2, *, control, 1)," &
" 289 (BC_8, PAD_SSP1_CMD , bidir, X, 288 , 1, Z)," &
" 288 (BC_2, *, control, 1)," &
" 287 (BC_8, PAD_SSP2_SS2 , bidir, X, 286 , 1, Z)," &
" 286 (BC_2, *, control, 1)," &
" 285 (BC_8, PAD_ENET_CLK , bidir, X, 284 , 1, Z)," &
" 284 (BC_2, *, control, 1)," &
" 283 (BC_8, PAD_SSP1_DATA0 , bidir, X, 282 , 1, Z)," &
" 282 (BC_2, *, control, 1)," &
" 281 (BC_8, PAD_AUART2_RX , bidir, X, 280 , 1, Z)," &
" 280 (BC_2, *, control, 1)," &
" 279 (BC_8, PAD_SSP1_DATA3 , bidir, X, 278 , 1, Z)," &
" 278 (BC_2, *, control, 1)," &
" 277 (BC_8, PAD_AUART2_TX , bidir, X, 276 , 1, Z)," &
" 276 (BC_2, *, control, 1)," &
" 275 (BC_8, PAD_ENET0_RX_EN , bidir, X, 274 , 1, Z)," &
" 274 (BC_2, *, control, 1)," &
" 273 (BC_8, PAD_SAIF0_MCLK , bidir, X, 272 , 1, Z)," &
" 272 (BC_2, *, control, 1)," &
" 271 (BC_8, PAD_ENET0_TX_EN , bidir, X, 270 , 1, Z)," &
" 270 (BC_2, *, control, 1)," &
" 269 (BC_8, PAD_AUART0_RX , bidir, X, 268 , 1, Z)," &
" 268 (BC_2, *, control, 1)," &
" 267 (BC_8, PAD_ENET0_RX_CLK , bidir, X, 266 , 1, Z)," &
" 266 (BC_2, *, control, 1)," &
" 265 (BC_8, PAD_SAIF0_LRCLK , bidir, X, 264 , 1, Z)," &
" 264 (BC_2, *, control, 1)," &
" 263 (BC_8, PAD_ENET0_TXD1 , bidir, X, 262 , 1, Z)," &
" 262 (BC_2, *, control, 1)," &
" 261 (BC_8, PAD_ENET0_TXD0 , bidir, X, 260 , 1, Z)," &
" 260 (BC_2, *, control, 1)," &
" 259 (BC_8, PAD_AUART0_TX , bidir, X, 258 , 1, Z)," &
" 258 (BC_2, *, control, 1)," &
" 257 (BC_8, PAD_ENET0_MDIO , bidir, X, 256 , 1, Z)," &
" 256 (BC_2, *, control, 1)," &
" 255 (BC_8, PAD_ENET0_TXD3 , bidir, X, 254 , 1, Z)," &
" 254 (BC_2, *, control, 1)," &
" 253 (BC_8, PAD_ENET0_TXD2 , bidir, X, 252 , 1, Z)," &
" 252 (BC_2, *, control, 1)," &
" 251 (BC_8, PAD_ENET0_RXD0 , bidir, X, 250 , 1, Z)," &
" 250 (BC_2, *, control, 1)," &
" 249 (BC_8, PAD_ENET0_RXD1 , bidir, X, 248 , 1, Z)," &
" 248 (BC_2, *, control, 1)," &
" 247 (BC_8, PAD_AUART2_CTS , bidir, X, 246 , 1, Z)," &
" 246 (BC_2, *, control, 1)," &
" 245 (BC_8, PAD_ENET0_RXD2 , bidir, X, 244 , 1, Z)," &
" 244 (BC_2, *, control, 1)," &
" 243 (BC_8, PAD_ENET0_RXD3 , bidir, X, 242 , 1, Z)," &
" 242 (BC_2, *, control, 1)," &
" 241 (BC_8, PAD_ENET0_MDC , bidir, X, 240 , 1, Z)," &
" 240 (BC_2, *, control, 1)," &
" 239 (BC_8, PAD_LCD_WR_RWN , bidir, X, 238 , 1, Z)," &
" 238 (BC_2, *, control, 1)," &
" 237 (BC_8, PAD_AUART2_RTS , bidir, X, 236 , 1, Z)," &
" 236 (BC_2, *, control, 1)," &
" 235 (BC_8, PAD_ENET0_COL , bidir, X, 234 , 1, Z)," &
" 234 (BC_2, *, control, 1)," &
" 233 (BC_8, PAD_LCD_VSYNC , bidir, X, 232 , 1, Z)," &
" 232 (BC_2, *, control, 1)," &
" 231 (BC_8, PAD_ENET0_CRS , bidir, X, 230 , 1, Z)," &
" 230 (BC_2, *, control, 1)," &
" 229 (BC_8, PAD_LCD_D00 , bidir, X, 228 , 1, Z)," &
" 228 (BC_2, *, control, 1)," &
" 227 (BC_8, PAD_AUART1_TX , bidir, X, 226 , 1, Z)," &
" 226 (BC_2, *, control, 1)," &
" 225 (BC_8, PAD_AUART0_RTS , bidir, X, 224 , 1, Z)," &
" 224 (BC_2, *, control, 1)," &
" 223 (BC_8, PAD_LCD_D02 , bidir, X, 222 , 1, Z)," &
" 222 (BC_2, *, control, 1)," &
" 221 (BC_8, PAD_PWM2 , bidir, X, 220 , 1, Z)," &
" 220 (BC_2, *, control, 1)," &
" 219 (BC_8, PAD_LCD_D01 , bidir, X, 218 , 1, Z)," &
" 218 (BC_2, *, control, 1)," &
" 217 (BC_8, PAD_AUART0_CTS , bidir, X, 216 , 1, Z)," &
" 216 (BC_2, *, control, 1)," &
" 215 (BC_8, PAD_LCD_HSYNC , bidir, X, 214 , 1, Z)," &
" 214 (BC_2, *, control, 1)," &
" 213 (BC_8, PAD_PWM0 , bidir, X, 212 , 1, Z)," &
" 212 (BC_2, *, control, 1)," &
" 211 (BC_8, PAD_LCD_DOTCLK , bidir, X, 210 , 1, Z)," &
" 210 (BC_2, *, control, 1)," &
" 209 (BC_8, PAD_AUART1_RTS , bidir, X, 208 , 1, Z)," &
" 208 (BC_2, *, control, 1)," &
" 207 (BC_8, PAD_LCD_D07 , bidir, X, 206 , 1, Z)," &
" 206 (BC_2, *, control, 1)," &
" 205 (BC_8, PAD_LCD_D03 , bidir, X, 204 , 1, Z)," &
" 204 (BC_2, *, control, 1)," &
" 203 (BC_8, PAD_AUART1_CTS , bidir, X, 202 , 1, Z)," &
" 202 (BC_2, *, control, 1)," &
" 201 (BC_8, PAD_LCD_D04 , bidir, X, 200 , 1, Z)," &
" 200 (BC_2, *, control, 1)," &
" 199 (BC_8, PAD_GPMI_RDY3 , bidir, X, 198 , 1, Z)," &
" 198 (BC_2, *, control, 1)," &
" 197 (BC_8, PAD_AUART1_RX , bidir, X, 196 , 1, Z)," &
" 196 (BC_2, *, control, 1)," &
" 195 (BC_8, PAD_AUART3_RTS , bidir, X, 194 , 1, Z)," &
" 194 (BC_2, *, control, 1)," &
" 193 (BC_8, PAD_PWM1 , bidir, X, 192 , 1, Z)," &
" 192 (BC_2, *, control, 1)," &
" 191 (BC_8, PAD_LCD_D10 , bidir, X, 190 , 1, Z)," &
" 190 (BC_2, *, control, 1)," &
" 189 (BC_8, PAD_AUART3_TX , bidir, X, 188 , 1, Z)," &
" 188 (BC_2, *, control, 1)," &
" 187 (BC_8, PAD_LCD_D12 , bidir, X, 186 , 1, Z)," &
" 186 (BC_2, *, control, 1)," &
" 185 (BC_8, PAD_GPMI_RDY2 , bidir, X, 184 , 1, Z)," &
" 184 (BC_2, *, control, 1)," &
" 183 (BC_8, PAD_LCD_D05 , bidir, X, 182 , 1, Z)," &
" 182 (BC_2, *, control, 1)," &
" 181 (BC_8, PAD_AUART3_CTS , bidir, X, 180 , 1, Z)," &
" 180 (BC_2, *, control, 1)," &
" 179 (BC_8, PAD_LCD_D06 , bidir, X, 178 , 1, Z)," &
" 178 (BC_2, *, control, 1)," &
" 177 (BC_8, PAD_GPMI_CE2N , bidir, X, 176 , 1, Z)," &
" 176 (BC_2, *, control, 1)," &
" 175 (BC_8, PAD_LCD_D08 , bidir, X, 174 , 1, Z)," &
" 174 (BC_2, *, control, 1)," &
" 173 (BC_8, PAD_LCD_RS , bidir, X, 172 , 1, Z)," &
" 172 (BC_2, *, control, 1)," &
" 171 (BC_8, PAD_LCD_D11 , bidir, X, 170 , 1, Z)," &
" 170 (BC_2, *, control, 1)," &
" 169 (BC_8, PAD_LCD_RD_E , bidir, X, 168 , 1, Z)," &
" 168 (BC_2, *, control, 1)," &
" 167 (BC_8, PAD_AUART3_RX , bidir, X, 166 , 1, Z)," &
" 166 (BC_2, *, control, 1)," &
" 165 (BC_8, PAD_LCD_D09 , bidir, X, 164 , 1, Z)," &
" 164 (BC_2, *, control, 1)," &
" 163 (BC_8, PAD_LCD_RESET , bidir, X, 162 , 1, Z)," &
" 162 (BC_2, *, control, 1)," &
" 161 (BC_8, PAD_LCD_D13 , bidir, X, 160 , 1, Z)," &
" 160 (BC_2, *, control, 1)," &
" 159 (BC_8, PAD_GPMI_RDY0 , bidir, X, 158 , 1, Z)," &
" 158 (BC_2, *, control, 1)," &
" 157 (BC_8, PAD_LCD_D16 , bidir, X, 156 , 1, Z)," &
" 156 (BC_2, *, control, 1)," &
" 155 (BC_8, PAD_LCD_D17 , bidir, X, 154 , 1, Z)," &
" 154 (BC_2, *, control, 1)," &
" 153 (BC_8, PAD_LCD_D14 , bidir, X, 152 , 1, Z)," &
" 152 (BC_2, *, control, 1)," &
" 151 (BC_8, PAD_LCD_D20 , bidir, X, 150 , 1, Z)," &
" 150 (BC_2, *, control, 1)," &
" 149 (BC_8, PAD_LCD_D23 , bidir, X, 148 , 1, Z)," &
" 148 (BC_2, *, control, 1)," &
" 147 (BC_8, PAD_GPMI_RDN , bidir, X, 146 , 1, Z)," &
" 146 (BC_2, *, control, 1)," &
" 145 (BC_8, PAD_LCD_ENABLE , bidir, X, 144 , 1, Z)," &
" 144 (BC_2, *, control, 1)," &
" 143 (BC_8, PAD_LCD_D19 , bidir, X, 142 , 1, Z)," &
" 142 (BC_2, *, control, 1)," &
" 141 (BC_8, PAD_LCD_CS , bidir, X, 140 , 1, Z)," &
" 140 (BC_2, *, control, 1)," &
" 139 (BC_8, PAD_LCD_D15 , bidir, X, 138 , 1, Z)," &
" 138 (BC_2, *, control, 1)," &
" 137 (BC_8, PAD_GPMI_CE0N , bidir, X, 136 , 1, Z)," &
" 136 (BC_2, *, control, 1)," &
" 135 (BC_8, PAD_GPMI_D05 , bidir, X, 134 , 1, Z)," &
" 134 (BC_2, *, control, 1)," &
" 133 (BC_8, PAD_GPMI_ALE , bidir, X, 132 , 1, Z)," &
" 132 (BC_2, *, control, 1)," &
" 131 (BC_8, PAD_LCD_D18 , bidir, X, 130 , 1, Z)," &
" 130 (BC_2, *, control, 1)," &
" 129 (BC_8, PAD_GPMI_RDY1 , bidir, X, 128 , 1, Z)," &
" 128 (BC_2, *, control, 1)," &
" 127 (BC_8, PAD_LCD_D22 , bidir, X, 126 , 1, Z)," &
" 126 (BC_2, *, control, 1)," &
" 125 (BC_8, PAD_LCD_D21 , bidir, X, 124 , 1, Z)," &
" 124 (BC_2, *, control, 1)," &
" 123 (BC_8, PAD_GPMI_CLE , bidir, X, 122 , 1, Z)," &
" 122 (BC_2, *, control, 1)," &
" 121 (BC_8, PAD_GPMI_D07 , bidir, X, 120 , 1, Z)," &
" 120 (BC_2, *, control, 1)," &
" 119 (BC_8, PAD_GPMI_D02 , bidir, X, 118 , 1, Z)," &
" 118 (BC_2, *, control, 1)," &
" 117 (BC_8, PAD_GPMI_WRN , bidir, X, 116 , 1, Z)," &
" 116 (BC_2, *, control, 1)," &
" 115 (BC_8, PAD_GPMI_D04 , bidir, X, 114 , 1, Z)," &
" 114 (BC_2, *, control, 1)," &
" 113 (BC_8, PAD_GPMI_RESETN , bidir, X, 112 , 1, Z)," &
" 112 (BC_2, *, control, 1)," &
" 111 (BC_8, PAD_GPMI_D06 , bidir, X, 110 , 1, Z)," &
" 110 (BC_2, *, control, 1)," &
" 109 (BC_8, PAD_GPMI_CE1N , bidir, X, 108 , 1, Z)," &
" 108 (BC_2, *, control, 1)," &
" 107 (BC_8, PAD_GPMI_D03 , bidir, X, 106 , 1, Z)," &
" 106 (BC_2, *, control, 1)," &
" 105 (BC_8, PAD_GPMI_D00 , bidir, X, 104 , 1, Z)," &
" 104 (BC_2, *, control, 1)," &
" 103 (BC_8, PAD_GPMI_CE3N , bidir, X, 102 , 1, Z)," &
" 102 (BC_2, *, control, 1)," &
" 101 (BC_8, PAD_GPMI_D01 , bidir, X, 100 , 1, Z)," &
" 100 (BC_2, *, control, 1)," &
" 99 (BC_8, PAD_EMI_A06 , bidir, X, 98 , 1, Z)," &
" 98 (BC_2, *, control, 1)," &
" 97 (BC_8, PAD_EMI_CE1N , bidir, X, 96 , 1, Z)," &
" 96 (BC_2, *, control, 1)," &
" 95 (BC_8, PAD_EMI_A08 , bidir, X, 94 , 1, Z)," &
" 94 (BC_2, *, control, 1)," &
" 93 (BC_8, PAD_EMI_A13 , bidir, X, 92 , 1, Z)," &
" 92 (BC_2, *, control, 1)," &
" 91 (BC_8, PAD_EMI_A09 , bidir, X, 90 , 1, Z)," &
" 90 (BC_2, *, control, 1)," &
" 89 (BC_8, PAD_EMI_A04 , bidir, X, 88 , 1, Z)," &
" 88 (BC_2, *, control, 1)," &
" 87 (BC_8, PAD_EMI_A11 , bidir, X, 86 , 1, Z)," &
" 86 (BC_2, *, control, 1)," &
" 85 (BC_8, PAD_EMI_A14 , bidir, X, 84 , 1, Z)," &
" 84 (BC_2, *, control, 1)," &
" 83 (BC_8, PAD_EMI_A12 , bidir, X, 82 , 1, Z)," &
" 82 (BC_2, *, control, 1)," &
" 81 (BC_8, PAD_EMI_CE0N , bidir, X, 80 , 1, Z)," &
" 80 (BC_2, *, control, 1)," &
" 79 (BC_8, PAD_EMI_A03 , bidir, X, 78 , 1, Z)," &
" 78 (BC_2, *, control, 1)," &
" 77 (BC_8, PAD_EMI_A07 , bidir, X, 76 , 1, Z)," &
" 76 (BC_2, *, control, 1)," &
" 75 (BC_8, PAD_EMI_A05 , bidir, X, 74 , 1, Z)," &
" 74 (BC_2, *, control, 1)," &
" 73 (BC_8, PAD_EMI_BA0 , bidir, X, 72 , 1, Z)," &
" 72 (BC_2, *, control, 1)," &
" 71 (BC_8, PAD_EMI_A01 , bidir, X, 70 , 1, Z)," &
" 70 (BC_2, *, control, 1)," &
" 69 (BC_8, PAD_EMI_BA1 , bidir, X, 68 , 1, Z)," &
" 68 (BC_2, *, control, 1)," &
" 67 (BC_8, PAD_EMI_A10 , bidir, X, 66 , 1, Z)," &
" 66 (BC_2, *, control, 1)," &
" 65 (BC_8, PAD_EMI_A02 , bidir, X, 64 , 1, Z)," &
" 64 (BC_2, *, control, 1)," &
" 63 (BC_8, PAD_EMI_BA2 , bidir, X, 62 , 1, Z)," &
" 62 (BC_2, *, control, 1)," &
" 61 (BC_8, PAD_EMI_CKE , bidir, X, 60 , 1, Z)," &
" 60 (BC_2, *, control, 1)," &
" 59 (BC_8, PAD_EMI_RASN , bidir, X, 58 , 1, Z)," &
" 58 (BC_2, *, control, 1)," &
" 57 (BC_8, PAD_EMI_A00 , bidir, X, 56 , 1, Z)," &
" 56 (BC_2, *, control, 1)," &
" 55 (BC_8, PAD_EMI_ODT1 , bidir, X, 54 , 1, Z)," &
" 54 (BC_2, *, control, 1)," &
" 53 (BC_8, PAD_EMI_CASN , bidir, X, 52 , 1, Z)," &
" 52 (BC_2, *, control, 1)," &
" 51 (BC_8, PAD_EMI_ODT0 , bidir, X, 50 , 1, Z)," &
" 50 (BC_2, *, control, 1)," &
" 49 (BC_8, PAD_EMI_WEN , bidir, X, 48 , 1, Z)," &
" 48 (BC_2, *, control, 1)," &
" 47 (BC_8, PAD_EMI_D02 , bidir, X, 46 , 1, Z)," &
" 46 (BC_2, *, control, 1)," &
" 45 (BC_8, PAD_EMI_D04 , bidir, X, 44 , 1, Z)," &
" 44 (BC_2, *, control, 1)," &
" 43 (BC_8, PAD_EMI_D05 , bidir, X, 42 , 1, Z)," &
" 42 (BC_2, *, control, 1)," &
" 41 (BC_8, PAD_EMI_DQM0 , bidir, X, 40 , 1, Z)," &
" 40 (BC_2, *, control, 1)," &
" 39 (BC_8, PAD_EMI_D03 , bidir, X, 38 , 1, Z)," &
" 38 (BC_2, *, control, 1)," &
" 37 (BC_8, PAD_EMI_D00 , bidir, X, 36 , 1, Z)," &
" 36 (BC_2, *, control, 1)," &
" 35 (BC_8, PAD_EMI_D01 , bidir, X, 34 , 1, Z)," &
" 34 (BC_2, *, control, 1)," &
" 33 (BC_8, PAD_EMI_D06 , bidir, X, 32 , 1, Z)," &
" 32 (BC_2, *, control, 1)," &
" 31 (BC_8, PAD_EMI_D07 , bidir, X, 30 , 1, Z)," &
" 30 (BC_2, *, control, 1)," &
" 29 (BC_8, PAD_EMI_DDR_OPEN_FB , bidir, X, 28 , 1, Z)," &
" 28 (BC_2, *, control, 1)," &
" 27 (BC_8, PAD_EMI_DDR_OPEN , bidir, X, 26 , 1, Z)," &
" 26 (BC_2, *, control, 1)," &
" 25 (BC_8, PAD_EMI_CLK , bidir, X, 24 , 1, Z)," &
" 24 (BC_2, *, control, 1)," &
" 23 (BC_8, PAD_EMI_DQS0 , bidir, X, 22 , 1, Z)," &
" 22 (BC_2, *, control, 1)," &
" 21 (BC_8, PAD_EMI_DQS1 , bidir, X, 20 , 1, Z)," &
" 20 (BC_2, *, control, 1)," &
" 19 (BC_8, PAD_EMI_D11 , bidir, X, 18 , 1, Z)," &
" 18 (BC_2, *, control, 1)," &
" 17 (BC_8, PAD_EMI_D13 , bidir, X, 16 , 1, Z)," &
" 16 (BC_2, *, control, 1)," &
" 15 (BC_8, PAD_EMI_D09 , bidir, X, 14 , 1, Z)," &
" 14 (BC_2, *, control, 1)," &
" 13 (BC_8, PAD_EMI_D12 , bidir, X, 12 , 1, Z)," &
" 12 (BC_2, *, control, 1)," &
" 11 (BC_8, PAD_EMI_D08 , bidir, X, 10, 1, Z)," &
" 10 (BC_2, *, control, 1)," &
" 9 (BC_8, PAD_EMI_D10 , bidir, X, 8, 1, Z)," &
" 8 (BC_2, *, control, 1)," &
" 7 (BC_8, PAD_EMI_D15 , bidir, X, 6, 1, Z)," &
" 6 (BC_2, *, control, 1)," &
" 5 (BC_8, PAD_EMI_DQM1 , bidir, X, 4, 1, Z)," &
" 4 (BC_2, *, control, 1)," &
" 3 (BC_8, PAD_EMI_D14 , bidir, X, 2, 1, Z)," &
" 2 (BC_2, *, control, 1)," &
" 1 (BC_8, PAD_JTAG_RTCK , bidir, X, 0, 1, Z)," &
" 0 (BC_2, *, control, 1)" ;
end catskills;
