-----------------------------------------------------------------------
-- Boundary Scan Description Language (IEEE P1149.1b) --
-- --
-- Device : LH79524
-- File Version : 1.2
-- File Name : LH79524_BSDL.txt
-- File created : Jan 24, 2004
-- Package type : CABGA
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- IMPORTANT NOTICE --
-- This information is provided on an AS IS basis and without warranty.
-- IN NO EVENT SHALL NXP BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL
-- DAMAGES ARISING FROM USE OF THIS INFORMATION. THIS DISCLAIMER OF
-- WARRANTY EXTENDS TO THE USER OF THE INFORMATION, AND TO THEIR
-- CUSTOMERS OR USERS OF PRODUCTS AND IS IN LIEU OF ALL WARRANTIES
-- WHETHER EXPRESS, IMPLIED, OR STATUTORY, INCLUDING IMPLIED WARRANTIES
-- OF MERCHANTABILITY OR FITNESS FOR PARTICULAR PURPOSE.
-- --
-- NXP does not represent or warrant that the information furnished
-- hereunder is free of infringement of any third party patents,
-- copyrights, trade secrets, or other intellectual property rights.
-- NXP does not represent or warrant that the information is free of
-- defect, or that it meets any particular standard, requirements or
-- need of the user of the information or their customers.
-- --
-- NXP reserves the right to change the information in this file
-- without notice.
-----------------------------------------------------------------------
-- $Id: LH79524_BSDL.txt.rca 1.2 Wed Sep 14 08:55:48 2005 wwhite Experimental $
-----------------------------------------------------------------------
entity LH79524 is
generic(PHYSICAL_PIN_MAP : string := "CABGA");
port (
LINREGEN: LINKAGE BIT; -- linear regulator enable
AN9 : LINKAGE BIT; -- AN9/PJ2 ADC input muxed with PJ2
AN8 : LINKAGE BIT; -- AN8/PJ4 ADC input muxed with PJ4
AN7 : LINKAGE BIT; -- AN7/PJ6/INT6 ADC input muxed with PJ6/INT6
AN6 : LINKAGE BIT; -- AN6/PJ7/INT7 ADC input muxed with PJ7/INT7
AN5 : LINKAGE BIT; -- AN5/PJ5/INT5 ADC input muxed with PJ5/INT5
AN4 : LINKAGE BIT; -- AN4/WIPER/PJ1 ADC input muxed with PJ1
AN3 : LINKAGE BIT; -- AN3/LR/Y-/PJ0 ADC input muxed with PJ0
AN2 : LINKAGE BIT; -- AN2/LL/Y+/PJ3 ADC input muxed with PJ3
AN1 : LINKAGE BIT; -- AN1/UR/X- ADC input
AN0 : LINKAGE BIT; -- AN0/UL/X+ ADC input
nRESETOUT: OUT BIT; -- System Reset Output
CLKOUT : OUT BIT; -- System Reset Output
nRESETIN: IN BIT; -- Reset Input
INT4 : INOUT BIT; --INT4/CTCLK/BATCNTL
PA7 : INOUT BIT; --PA7/CTCAP2B/CTCMP2B/SCL
PA6 : INOUT BIT; --PA6/CTCAP2A/CTCMP2A/SDA
PA5 : INOUT BIT; --PA5/CTCAP1B/CTCMP1B
PA4 : INOUT BIT; --PA4/CTCAP1A/CTCMP1A
PA3 : INOUT BIT; --PA3/CTCAP0B/CTCMP0B
PA2 : INOUT BIT; --PA2/CTCAP0A/CTCMP0A
PA1 : INOUT BIT; --PA1/INT3/UARTTX2/UARTIRTX2
PA0 : INOUT BIT; --PA0/INT2/UARTRX2/UARTIRRX2
PB7 : INOUT BIT; --PB7/INT1/UARTTX0/UARTIRTX0
PB6 : INOUT BIT; --PB6/INT0/UARTRX0/UARTIRRX0
PB5 : INOUT BIT; --PB5/SSPTX/I2STXD/UARTTX1/UARTIRTX1
PB4 : INOUT BIT; --PB4/SSPRX/I2SRXD/UARTRX1/UARTIRRX1
PB3 : INOUT BIT; --PB3/SSPCLK/I2SCLK
PB2 : INOUT BIT; --PB2/SSPFRM/I2SWS
PB1 : INOUT BIT; --PB1/DREQ/nUARTRTS0
PB0 : INOUT BIT; --PB1/nDACK/nUARTCTS0
nTRST : IN BIT; -- JTAG reset
TDO : OUT BIT; -- JTAG test data out
TDI : IN BIT; -- JTAG test data in
TCK : IN BIT; -- JTAG Test clock
TEST1 : IN BIT; -- Test mode pin 1
TEST2 : IN BIT; -- Test mode pin 2
TMS : IN BIT; -- JTAG Test mode select
PC7 : INOUT BIT; -- PC7/A23/nFRE
PC6 : INOUT BIT; -- PC6/A22/nFWE
PC5 : INOUT BIT; -- PC5/A21
PC4 : INOUT BIT; -- PC4/A20
PC3 : INOUT BIT; -- PC3/A19
PC2 : INOUT BIT; -- PC2/A18
PC1 : INOUT BIT; -- PC1/A17
PC0 : INOUT BIT; -- PC0/A16
A15 : OUT BIT; -- Ex Mem Controller Address bit 15
A14 : OUT BIT; -- Ex Mem Controller Address bit 14
A13 : OUT BIT; -- Ex Mem Controller Address bit 13
A12 : OUT BIT; -- Ex Mem Controller Address bit 12
A11 : OUT BIT; -- Ex Mem Controller Address bit 11
A10 : OUT BIT; -- Ex Mem Controller Address bit 10
A9 : OUT BIT; -- Ex Mem Controller Address bit 9
A8 : OUT BIT; -- Ex Mem Controller Address bit 8
A7 : OUT BIT; -- Ex Mem Controller Address bit 7
A6 : OUT BIT; -- Ex Mem Controller Address bit 6
A5 : OUT BIT; -- Ex Mem Controller Address bit 5
A4 : OUT BIT; -- Ex Mem Controller Address bit 4
A3 : OUT BIT; -- Ex Mem Controller Address bit 3
A2 : OUT BIT; -- Ex Mem Controller Address bit 2
A1 : OUT BIT; -- Ex Mem Controller Address bit 1
A0 : OUT BIT; -- Ex Mem Controller Address bit 0
PL7 : INOUT BIT; --PL7/D31 (Data to/from mem controller)
PL6 : INOUT BIT; --PL6/D30 (Data to/from mem controller)
PL5 : INOUT BIT; --PL5/D29 (Data to/from mem controller)
PL4 : INOUT BIT; --PL4/D28 (Data to/from mem controller)
PL3 : INOUT BIT; --PL3/LCDVD13
PL2 : INOUT BIT; --PL2/LCDVD12
PL1 : INOUT BIT; -- PL1/LCDVD15
PL0 : INOUT BIT; -- PL0/LCDVD14
PN3 : INOUT BIT; --PN3/D25 (Data to/from mem controller)
PN2 : INOUT BIT; --PN2/D24 (Data to/from mem controller)
PN1 : INOUT BIT; --PN1/D27 (Data to/from mem controller)
PN0 : INOUT BIT; --PN0/D26 (Data to/from mem controller)
PK7 : INOUT BIT; --PK7/D23 (Data to/from mem controller)
PK6 : INOUT BIT; --PK6/D22 (Data to/from mem controller)
PK5 : INOUT BIT; --PK5/D21 (Data to/from mem controller)
PK4 : INOUT BIT; --PK4/D20 (Data to/from mem controller)
PK3 : INOUT BIT; --PK3/D19 (Data to/from mem controller)
PK2 : INOUT BIT; --PK2/D18 (Data to/from mem controller)
PK1 : INOUT BIT; --PK1/D17 (Data to/from mem controller)
PK0 : INOUT BIT; --PK0/D16 (Data to/from mem controller)
PD7 : INOUT BIT; --PD7/D15 (Data to/from mem controller)
PD6 : INOUT BIT; --PD6/D14 (Data to/from mem controller)
PD5 : INOUT BIT; --PD5/D13 (Data to/from mem controller)
PD4 : INOUT BIT; --PD4/D12 (Data to/from mem controller)
PD3 : INOUT BIT; --PD3/D11 (Data to/from mem controller)
PD2 : INOUT BIT; --PD2/D10 (Data to/from mem controller)
PD1 : INOUT BIT; --PD1/D9 (Data to/from mem controller)
PD0 : INOUT BIT; --PD0/D8 (Data to/from mem controller)
D7 : INOUT BIT; --Data to/from mem controller
D6 : INOUT BIT; --Data to/from mem controller
D5 : INOUT BIT; --Data to/from mem controller
D4 : INOUT BIT; --Data to/from mem controller
D3 : INOUT BIT; --Data to/from mem controller
D2 : INOUT BIT; --Data to/from mem controller
D1 : INOUT BIT; --Data to/from mem controller
D0 : INOUT BIT; --Data to/from mem controller
nCS3 : OUT BIT; --nCS3/PM3 Ex mem controller static chip select
nCS2 : OUT BIT; --nCS2/PM2 Ex mem controller static chip select
nCS1 : OUT BIT; --nCS1/PM1 Ex mem controller static chip select
nCS0 : OUT BIT; --nCS0/PM0 Ex mem controller static chip select
nOE : OUT BIT; --Ex mem controller output enable
nBLE3 : OUT BIT; --nBLE3/PM7 Byte lane enable muxed with GPIO PM7
nBLE2 : OUT BIT; --nBLE2/PM6 Byte lane enable muxed with GPIO PM6
nBLE1 : OUT BIT; --nBLE1/PM5 Byte lane enable muxed with GPIO PM5
nBLE0 : INOUT BIT; --nBLE0/PM4 Byte lane enable muxed with PM4
nWE : OUT BIT; --Ex mem controller write enable
nCAS : OUT BIT; --Ex mem controller column address strobe
nRAS : OUT BIT; --Ex mem controller row address strobe
nDCS1 : OUT BIT; --Ex mem controller dynamic chip select
nDCS0 : OUT BIT; --Ex mem controller dynamic chip select
SDCKE : OUT BIT; --Ex mem controller dynamic clock enable
SDCLK : INOUT BIT; --Ex mem controller clock out
DQM3 : OUT BIT; --Ex mem controller dynamic mem data mask output
DQM2 : OUT BIT; --Ex mem controller dynamic mem data mask output
DQM1 : OUT BIT; --Ex mem controller dynamic mem data mask output
DQM0 : OUT BIT; --Ex mem controller dynamic mem data mask output
XTAL32IN: LINKAGE BIT; --32.768KHZ Crystal Clock Input
XTAL32OUT: LINKAGE BIT; --32.768KHZ Crystal Clock Output
XTALIN : LINKAGE BIT; --Crystal Clock Input
XTALOUT : LINKAGE BIT; --Crystal Clock Output
USBDN : LINKAGE BIT; -- USB Data Positive (differential input)
USBDP : LINKAGE BIT; -- USB Data Negative (differential input)
PE7 : INOUT BIT;--PE7/nWAIT/nDEOT
PE6 : INOUT BIT; --PE6/LCDVEEN/LCDMOD
PE5 : INOUT BIT; --PE5/LCDVDDEN
PE4 : INOUT BIT; --PE4/LCDSPLEN/LCDREV
PE3 : INOUT BIT; --PE3/LCDCLS
PE2 : INOUT BIT; --PE2/LCDPS
PE1 : INOUT BIT; --PE1/LCDDCLK
PE0 : INOUT BIT; --PE0/LCDLP/LCDHRLP
PF7 : INOUT BIT; --PF7/LCDFP/LCDSPS
PF6 : INOUT BIT; --PF6/LCDEN/LCDSPL
PF5 : INOUT BIT; --PF5/LCDVD11
PF4 : INOUT BIT; --PF4/LCDVD10
PF3 : INOUT BIT; --PF4/LCDVD9
PF2 : INOUT BIT; --PF2/LCDVD8
PF1 : INOUT BIT; --PF1/LCDVD7
PF0 : INOUT BIT; --PF0/LCDVD6
PG7 : INOUT BIT; --PG7/LCDVD5
PG6 : INOUT BIT; --PG6/LCDVD4
PG5 : INOUT BIT; --PG5/LCDVD3
PG4 : INOUT BIT; --PG4/LCDVD2
PG3 : INOUT BIT; --PG3/LCDVD1
PG2 : INOUT BIT; --PG2/LCDVD0
PG1 : INOUT BIT; --PG1/ETHERTXCLK
PG0 : INOUT BIT; --PG0/ETHERTXEN
PH7 : INOUT BIT; --PH7/ETHERTX3
PH6 : INOUT BIT; --PH6/ETHERTX2
PH5 : INOUT BIT; --PH5/ETHERTX1
PH4 : INOUT BIT; --PH4/ETHERTX0
PH3 : INOUT BIT; --PH3/ETHERTXER
PH2 : INOUT BIT; --PH2/ETHERRXCLK
PH1 : INOUT BIT; --PH1/ETHERRXDV
PH0 : INOUT BIT; --PH0/ETHERRX3
PI7 : INOUT BIT; --PI7/ETHERRX2
PI6 : INOUT BIT; --PI6/ETHERRX1
PI5 : INOUT BIT; --PI5/ETHERRX0
PI4 : INOUT BIT; --PI4/ETHERRXER
PI3 : INOUT BIT; --PI3/ETHERCRS
PI2 : INOUT BIT; -- PI2/ETHERCOL
PI1 : INOUT BIT; -- PI1/ETHERMDIO
PI0 : INOUT BIT; -- PI0/ETHERMDC
VDD : LINKAGE BIT_VECTOR(1 to 15); -- I/O RING VSS
VSS : LINKAGE BIT_VECTOR(1 to 14); -- I/O RING VSS
VDDC : LINKAGE BIT_VECTOR(1 to 5); -- Digital Core VDD
VSSC : LINKAGE BIT_VECTOR(1 to 4); -- Digital Core GND
VDDA0 : LINKAGE BIT; -- Analog power for PLL1
VSSA0 : LINKAGE BIT; -- Analog GND for PLL1
VSSA1 : LINKAGE BIT; -- Analog GND for PLL1
VDDA1 : LINKAGE BIT; -- Analog power for PLL2
VDDA2 : LINKAGE BIT; -- Analog power for PLL2
VSSA2 : LINKAGE BIT -- Analog GND for PLL2
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of LH79524 : entity is "STD_1149_1_1993";
attribute PIN_MAP of LH79524 : entity is PHYSICAL_PIN_MAP;
constant CABGA : PIN_MAP_STRING :=
"A0 : T12," &
"A1 : R11," &
"A10 : R8," &
"A11 : P8," &
"A12 : T7," &
"A13 : R7," &
"A14 : P7," &
"A15 : T6," &
"A2 : T11," &
"A3 : P10," &
"A4 : R10," &
"A5 : T10," &
"A6 : P9," &
"A7 : R9," &
"A8 : T9," &
"A9 : T8," &
"AN0 : E2," &
"AN1 : F2," &
"AN2 : G2," &
"AN3 : H2," &
"AN4 : H3," &
"AN5 : F1," &
"AN6 : F3," &
"AN7 : E1," &
"AN8 : G3," &
"AN9 : G1," &
"CLKOUT : K1," &
"D0 : M15," &
"D1 : N16," &
"D2 : L13," &
"D3 : M14," &
"D4 : N15," &
"D5 : P16," &
"D6 : M13," &
"D7 : N14," &
"DQM0 : D13," &
"DQM1 : E13," &
"DQM2 : E14," &
"DQM3 : G14," &
"INT4 : J3," &
"LINREGEN : E3," &
"nBLE0 : J15," &
"nBLE1 : J14," &
"nBLE2 : K16," &
"nBLE3 : K15," &
"nCAS : H16," &
"nCS0 : L16," &
"nCS1 : L15," &
"nCS2 : M16," &
"nCS3 : L14," &
"nDCS0 : G16," &
"nDCS1 : H14," &
"nOE : K14," &
"nRAS : H15," &
"nRESETIN : J2," &
"nRESETOUT : H1," &
"nTRST : D2," &
"nWE : J16," &
"PA0 : N1," &
"PA1 : M2," &
"PA2 : L3," &
"PA3 : M1," &
"PA4 : L2," &
"PA5 : L1," &
"PA6 : K3," &
"PA7 : K2," &
"PB0 : R2," &
"PB1 : R1," &
"PB2 : P2," &
"PB3 : N3," &
"PB4 : M4," &
"PB5 : P1," &
"PB6 : N2," &
"PB7 : M3," &
"PC0 : N7," &
"PC1 : R6," &
"PC2 : T5," &
"PC3 : P6," &
"PC4 : R5," &
"PC5 : T4," &
"PC6 : P5," &
"PC7 : R4," &
"PD0 : P15," &
"PD1 : P14," &
"PD2 : N13," &
"PD3 : T15," &
"PD4 : N12," &
"PD5 : T14," &
"PD6 : P12," &
"PD7 : T13," &
"PE0 : B12," &
"PE1 : D11," &
"PE2 : B13," &
"PE3 : C13," &
"PE4 : D12," &
"PE5 : B16," &
"PE6 : B15," &
"PE7 : D14," &
"PF0 : A8," &
"PF1 : A9," &
"PF2 : B9," &
"PF3 : C9," &
"PF4 : B10," &
"PF5 : A11," &
"PF6 : B11," &
"PF7 : A12," &
"PG0 : A5," &
"PG1 : B6," &
"PG2 : A6," &
"PG3 : C7," &
"PG4 : B7," &
"PG5 : A7," &
"PG6 : C8," &
"PG7 : B8," &
"PH0 : C4," &
"PH1 : A3," &
"PH2 : B4," &
"PH3 : C5," &
"PH4 : D6," &
"PH5 : A4," &
"PH6 : B5," &
"PH7 : C6," &
"PI0 : D3," &
"PI1 : B1," &
"PI2 : B2," &
"PI3 : D4," &
"PI4 : C3," &
"PI5 : A1," &
"PI6 : A2," &
"PI7 : B3," &
"PK0 : R16," &
"PK1 : M12," &
"PK2 : T16," &
"PK3 : R15," &
"PK4 : P13," &
"PK5 : R14," &
"PK6 : R13," &
"PK7 : N11," &
"PL0 : C1," &
"PL1 : C2," &
"PL2 : A10," &
"PL3 : C10," &
"PL4 : C12," &
"PL5 : A14," &
"PL6 : B14," &
"PL7 : C14," &
"PN0 : C11," &
"PN1 : A13," &
"PN2 : R12," &
"PN3 : P11," &
"SDCKE : G15," &
"SDCLK : F14," &
"TCK : T3," &
"TDI : T1," &
"TDO : P3," &
"TEST1 : T2," &
"TEST2 : R3," &
"TMS : P4," &
"USBDN : A16," &
"USBDP : A15," &
"VDD : (G4,D7,N9,N6,K4,H4,G13," &
"D8,N10,N8,J4,D9,L4,F13,K13)," &
"VDDA0 : D1," &
"VDDA1 : F16," &
"VDDA2 : E16," &
"VDDC : (E5,D5,N5,E4,H13)," &
"VSS : (G9,J7,K9,M5,H9,E12,J10," &
"H7,J8,G8,H10,K8,H8,J9)," &
"VSSA0 : J1," &
"VSSA1 : F15," &
"VSSA2 : E15," &
"VSSC : (N4,D10,F4,J13)," &
"XTAL32IN : D16," &
"XTAL32OUT : D15," &
"XTALIN : C16," &
"XTALOUT : C15" ;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6,BOTH); attribute TAP_SCAN_RESET of nTRST : signal is true;
attribute COMPLIANCE_PATTERNS of LH79524: entity is
"(TEST1, TEST2,nRESETIN ) (111)";
attribute INSTRUCTION_LENGTH of LH79524 : entity is 3; attribute INSTRUCTION_OPCODE of LH79524 : entity is
"extest (000)," &
"bypass (111)," &
"sample (001)," &
"highz (010)," &
"clamp (011)," &
"idcode (100)";
attribute INSTRUCTION_CAPTURE of LH79524 : entity is "001"; attribute IDCODE_REGISTER of LH79524 : entity is
"0000" & -- Version Number
"1001010100100100" & -- Part number
"00000110000" & -- Manufactuer ID
"1"; -- Required by IEEE Std. 1149.1
attribute REGISTER_ACCESS of LH79524 : entity is
"BOUNDARY (extest,sample), " &
"DEVICE_ID (idcode), " &
"BYPASS (bypass, highz, clamp)";
--{********************************************************}
--{ The first cell, cell 0 is closest to TDO }
--{ BC_1: used on all control and Output3 cells }
--{ BC_4: used on all inputs }
--{********************************************************}
attribute BOUNDARY_LENGTH of LH79524 : entity is 381; attribute BOUNDARY_REGISTER of LH79524 : entity is
-- # cell name function safe control disable disable
-- type bit signal value result
"0 (BC_1, *, control, 0 )," &
"1 (BC_1, PB0, output3, X, 0, 0, Z)," &
"2 (BC_4, PB0, observe_only, X )," &
"3 (BC_1, *, control, 0 )," &
"4 (BC_1, PB1, output3, X, 3, 0, Z)," &
"5 (BC_4, PB1, observe_only, X )," &
"6 (BC_1, *, control, 0 )," &
"7 (BC_1, PB2, output3, X, 6, 0, Z)," &
"8 (BC_4, PB2, observe_only, X )," &
"9 (BC_1, *, control, 0 )," &
"10 (BC_1, PB3, output3, X, 9, 0, Z)," &
"11 (BC_4, PB3, observe_only, X )," &
"12 (BC_1, *, control, 0 )," &
"13 (BC_1, PB4, output3, X, 12, 0, Z)," &
"14 (BC_4, PB4, observe_only, X )," &
"15 (BC_1, *, control, 0 )," &
"16 (BC_1, PB5, output3, X, 15, 0, Z)," &
"17 (BC_4, PB5, observe_only, X )," &
"18 (BC_1, *, control, 0 )," &
"19 (BC_1, PB6, output3, X, 18, 0, Z)," &
"20 (BC_4, PB6, observe_only, X )," &
"21 (BC_1, *, control, 0 )," &
"22 (BC_1, PB7, output3, X, 21, 0, Z)," &
"23 (BC_4, PB7, observe_only, X )," &
"24 (BC_1, *, control, 0 )," &
"25 (BC_1, PA0, output3, X, 24, 0, Z)," &
"26 (BC_4, PA0, observe_only, X )," &
"27 (BC_1, *, control, 0 )," &
"28 (BC_1, PA1, output3, X, 27, 0, Z)," &
"29 (BC_4, PA1, observe_only, X )," &
"30 (BC_1, *, control, 0 )," &
"31 (BC_1, PA2, output3, X, 30, 0, Z)," &
"32 (BC_4, PA2, observe_only, X )," &
"33 (BC_1, *, control, 0 )," &
"34 (BC_1, PA3, output3, X, 33, 0, Z)," &
"35 (BC_4, PA3, observe_only, X )," &
"36 (BC_1, *, control, 0 )," &
"37 (BC_1, PA4, output3, X, 36, 0, Z)," &
"38 (BC_4, PA4, observe_only, X )," &
"39 (BC_1, *, control, 0 )," &
"40 (BC_1, PA5, output3, X, 39, 0, Z)," &
"41 (BC_4, PA5, observe_only, X )," &
"42 (BC_1, *, control, 0 )," &
"43 (BC_1, PA6, output3, X, 42, 0, Z)," &
"44 (BC_4, PA6, observe_only, X )," &
"45 (BC_1, *, control, 0 )," &
"46 (BC_1, PA7, output3, X, 45, 0, Z)," &
"47 (BC_4, PA7, observe_only, X )," &
"48 (BC_1, *, control, 0 )," &
"49 (BC_1, INT4, output3, X, 48, 0, Z)," &
"50 (BC_4, INT4, observe_only, X )," &
"51 (BC_1, *, control, 0 )," &
"52 (BC_1, CLKOUT, output3, X, 51, 0, Z)," &
"53 (BC_1, *, control, 0 )," &
"54 (BC_1, nRESETOUT,output3, X, 53, 0, Z)," &
"55 (BC_1, *, control, 0 )," &
"56 (BC_1, PL0, output3, X, 55, 0, Z)," &
"57 (BC_4, PL0, observe_only, X )," &
"58 (BC_1, *, control, 0 )," &
"59 (BC_1, PL1, output3, X, 58, 0, Z)," &
"60 (BC_4, PL1, observe_only, X )," &
"61 (BC_1, *, control, 0 )," &
"62 (BC_1, PI0, output3, X, 61, 0, Z)," &
"63 (BC_4, PI0, observe_only, X )," &
"64 (BC_1, *, control, 0 )," &
"65 (BC_1, PI1, output3, X, 64, 0, Z)," &
"66 (BC_4, PI1, observe_only, X )," &
"67 (BC_1, *, control, 0 )," &
"68 (BC_1, PI2, output3, X, 67, 0, Z)," &
"69 (BC_4, PI2, observe_only, X )," &
"70 (BC_1, *, control, 0 )," &
"71 (BC_1, PI3, output3, X, 70, 0, Z)," &
"72 (BC_4, PI3, observe_only, X )," &
"73 (BC_1, *, control, 0 )," &
"74 (BC_1, PI4, output3, X, 73, 0, Z)," &
"75 (BC_4, PI4, observe_only, X )," &
"76 (BC_1, *, control, 0 )," &
"77 (BC_1, PI5, output3, X, 76, 0, Z)," &
"78 (BC_4, PI5, observe_only, X )," &
"79 (BC_1, *, control, 0 )," &
"80 (BC_1, PI6, output3, X, 79, 0, Z)," &
"81 (BC_4, PI6, observe_only, X )," &
"82 (BC_1, *, control, 0 )," &
"83 (BC_1, PI7, output3, X, 82, 0, Z)," &
"84 (BC_4, PI7, observe_only, X )," &
"85 (BC_1, *, control, 0 )," &
"86 (BC_1, PH0, output3, X, 85, 0, Z)," &
"87 (BC_4, PH0, observe_only, X )," &
"88 (BC_1, *, control, 0 )," &
"89 (BC_1, PH1, output3, X, 88, 0, Z)," &
"90 (BC_4, PH1, observe_only, X )," &
"91 (BC_1, *, control, 0 )," &
"92 (BC_1, PH2, output3, X, 91, 0, Z)," &
"93 (BC_4, PH2, observe_only, X )," &
"94 (BC_1, *, control, 0 )," &
"95 (BC_1, PH3, output3, X, 94, 0, Z)," &
"96 (BC_4, PH3, observe_only, X )," &
"97 (BC_1, *, control, 0 )," &
"98 (BC_1, PH4, output3, X, 97, 0, Z)," &
"99 (BC_4, PH4, observe_only, X )," &
"100 (BC_1, *, control, 0 )," &
"101 (BC_1, PH5, output3, X, 100, 0, Z)," &
"102 (BC_4, PH5, observe_only, X )," &
"103 (BC_1, *, control, 0 )," &
"104 (BC_1, PH6, output3, X, 103, 0, Z)," &
"105 (BC_4, PH6, observe_only, X )," &
"106 (BC_1, *, control, 0 )," &
"107 (BC_1, PH7, output3, X, 106, 0, Z)," &
"108 (BC_4, PH7, observe_only, X )," &
"109 (BC_1, *, control, 0 )," &
"110 (BC_1, PG0, output3, X, 109, 0, Z)," &
"111 (BC_4, PG0, observe_only, X )," &
"112 (BC_1, *, control, 0 )," &
"113 (BC_1, PG1, output3, X, 112, 0, Z)," &
"114 (BC_4, PG1, observe_only, X )," &
"115 (BC_1, *, control, 0 )," &
"116 (BC_1, PG2, output3, X, 115, 0, Z)," &
"117 (BC_4, PG2, observe_only, X )," &
"118 (BC_1, *, control, 0 )," &
"119 (BC_1, PG3, output3, X, 118, 0, Z)," &
"120 (BC_4, PG3, observe_only, X )," &
"121 (BC_1, *, control, 0 )," &
"122 (BC_1, PG4, output3, X, 121, 0, Z)," &
"123 (BC_4, PG4, observe_only, X )," &
"124 (BC_1, *, control, 0 )," &
"125 (BC_1, PG5, output3, X, 124, 0, Z)," &
"126 (BC_4, PG5, observe_only, X )," &
"127 (BC_1, *, control, 0 )," &
"128 (BC_1, PG6, output3, X, 127, 0, Z)," &
"129 (BC_4, PG6, observe_only, X )," &
"130 (BC_1, *, control, 0 )," &
"131 (BC_1, PG7, output3, X, 130, 0, Z)," &
"132 (BC_4, PG7, observe_only, X )," &
"133 (BC_1, *, control, 0 )," &
"134 (BC_1, PF0, output3, X, 133, 0, Z)," &
"135 (BC_4, PF0, observe_only, X )," &
"136 (BC_1, *, control, 0 )," &
"137 (BC_1, PF1, output3, X, 136, 0, Z)," &
"138 (BC_4, PF1, observe_only, X )," &
"139 (BC_1, *, control, 0 )," &
"140 (BC_1, PF2, output3, X, 139, 0, Z)," &
"141 (BC_4, PF2, observe_only, X )," &
"142 (BC_1, *, control, 0 )," &
"143 (BC_1, PF3, output3, X, 142, 0, Z)," &
"144 (BC_4, PF3, observe_only, X )," &
"145 (BC_1, *, control, 0 )," &
"146 (BC_1, PL2, output3, X, 145, 0, Z)," &
"147 (BC_4, PL2, observe_only, X )," &
"148 (BC_1, *, control, 0 )," &
"149 (BC_1, PF4, output3, X, 148, 0, Z)," &
"150 (BC_4, PF4, observe_only, X )," &
"151 (BC_1, *, control, 0 )," &
"152 (BC_1, PL3, output3, X, 151, 0, Z)," &
"153 (BC_4, PL3, observe_only, X )," &
"154 (BC_1, *, control, 0 )," &
"155 (BC_1, PF5, output3, X, 154, 0, Z)," &
"156 (BC_4, PF5, observe_only, X )," &
"157 (BC_1, *, control, 0 )," &
"158 (BC_1, PF6, output3, X, 157, 0, Z)," &
"159 (BC_4, PF6, observe_only, X )," &
"160 (BC_1, *, control, 0 )," &
"161 (BC_1, PF7, output3, X, 160, 0, Z)," &
"162 (BC_4, PF7, observe_only, X )," &
"163 (BC_1, *, control, 0 )," &
"164 (BC_1, PN0, output3, X, 163, 0, Z)," &
"165 (BC_4, PN0, observe_only, X )," &
"166 (BC_1, *, control, 0 )," &
"167 (BC_1, PE0, output3, X, 166, 0, Z)," &
"168 (BC_4, PE0, observe_only, X )," &
"169 (BC_1, *, control, 0 )," &
"170 (BC_1, PN1, output3, X, 169, 0, Z)," &
"171 (BC_4, PN1, observe_only, X )," &
"172 (BC_1, *, control, 0 )," &
"173 (BC_1, PE1, output3, X, 172, 0, Z)," &
"174 (BC_4, PE1, observe_only, X )," &
"175 (BC_1, *, control, 0 )," &
"176 (BC_1, PL4, output3, X, 175, 0, Z)," &
"177 (BC_4, PL4, observe_only, X )," &
"178 (BC_1, *, control, 0 )," &
"179 (BC_1, PE2, output3, X, 178, 0, Z)," &
"180 (BC_4, PE2, observe_only, X )," &
"181 (BC_1, *, control, 0 )," &
"182 (BC_1, PL5, output3, X, 181, 0, Z)," &
"183 (BC_4, PL5, observe_only, X )," &
"184 (BC_1, *, control, 0 )," &
"185 (BC_1, PE3, output3, X, 184, 0, Z)," &
"186 (BC_4, PE3, observe_only, X )," &
"187 (BC_1, *, control, 0 )," &
"188 (BC_1, PE4, output3, X, 187, 0, Z)," &
"189 (BC_4, PE4, observe_only, X )," &
"190 (BC_1, *, control, 0 )," &
"191 (BC_1, PL6, output3, X, 190, 0, Z)," &
"192 (BC_4, PL6, observe_only, X )," &
"193 (BC_1, *, control, 0 )," &
"194 (BC_1, PE5, output3, X, 193, 0, Z)," &
"195 (BC_4, PE5, observe_only, X )," &
"196 (BC_1, *, control, 0 )," &
"197 (BC_1, PL7, output3, X, 196, 0, Z)," &
"198 (BC_4, PL7, observe_only, X )," &
"199 (BC_1, *, control, 0 )," &
"200 (BC_1, PE6, output3, X, 199, 0, Z)," &
"201 (BC_4, PE6, observe_only, X )," &
"202 (BC_1, *, control, 0 )," &
"203 (BC_1, PE7, output3, X, 202, 0, Z)," &
"204 (BC_4, PE7, observe_only, X )," &
"205 (BC_1, *, control, 0 )," &
"206 (BC_1, DQM0, output3, X, 205, 0, Z)," &
"207 (BC_1, *, control, 0 )," &
"208 (BC_1, DQM1, output3, X, 207, 0, Z)," &
"209 (BC_1, *, control, 0 )," &
"210 (BC_1, DQM2, output3, X, 209, 0, Z)," &
"211 (BC_1, *, control, 0 )," &
"212 (BC_1, SDCLK, output3, X, 211, 0, Z)," &
"213 (BC_4, SDCLK, observe_only, X )," &
"214 (BC_1, *, control, 0 )," &
"215 (BC_1, DQM3, output3, X, 214, 0, Z)," &
"216 (BC_1, *, control, 0 )," &
"217 (BC_1, SDCKE, output3, X, 216, 0, Z)," &
"218 (BC_1, *, control, 0 )," &
"219 (BC_1, nDCS0, output3, X, 218, 0, Z)," &
"220 (BC_1, *, control, 0 )," &
"221 (BC_1, nDCS1, output3, X, 220, 0, Z)," &
"222 (BC_1, *, control, 0 )," &
"223 (BC_1, nRAS, output3, X, 222, 0, Z)," &
"224 (BC_1, *, control, 0 )," &
"225 (BC_1, nCAS, output3, X, 224, 0, Z)," &
"226 (BC_1, *, control, 0 )," &
"227 (BC_1, nWE, output3, X, 226, 0, Z)," &
"228 (BC_1, *, control, 0 )," &
"229 (BC_1, nBLE0, output3, X, 228, 0, Z)," &
"230 (BC_4, nBLE0, observe_only, X )," &
"231 (BC_1, *, control, 0 )," &
"232 (BC_1, nBLE1, output3, X, 231, 0, Z)," &
"233 (BC_1, *, control, 0 )," &
"234 (BC_1, nBLE2, output3, X, 233, 0, Z)," &
"235 (BC_1, *, control, 0 )," &
"236 (BC_1, nBLE3, output3, X, 235, 0, Z)," &
"237 (BC_1, *, control, 0 )," &
"238 (BC_1, nOE, output3, X, 237, 0, Z)," &
"239 (BC_1, *, control, 0 )," &
"240 (BC_1, nCS0, output3, X, 239, 0, Z)," &
"241 (BC_1, *, control, 0 )," &
"242 (BC_1, nCS1, output3, X, 241, 0, Z)," &
"243 (BC_1, *, control, 0 )," &
"244 (BC_1, nCS2, output3, X, 243, 0, Z)," &
"245 (BC_1, *, control, 0 )," &
"246 (BC_1, nCS3, output3, X, 245, 0, Z)," &
"247 (BC_1, *, control, 0 )," &
"248 (BC_1, D0, output3, X, 247, 0, Z)," &
"249 (BC_4, D0, observe_only, X )," &
"250 (BC_1, *, control, 0 )," &
"251 (BC_1, D1, output3, X, 250, 0, Z)," &
"252 (BC_4, D1, observe_only, X )," &
"253 (BC_1, *, control, 0 )," &
"254 (BC_1, D2, output3, X, 253, 0, Z)," &
"255 (BC_4, D2, observe_only, X )," &
"256 (BC_1, *, control, 0 )," &
"257 (BC_1, D3, output3, X, 256, 0, Z)," &
"258 (BC_4, D3, observe_only, X )," &
"259 (BC_1, *, control, 0 )," &
"260 (BC_1, D4, output3, X, 259, 0, Z)," &
"261 (BC_4, D4, observe_only, X )," &
"262 (BC_1, *, control, 0 )," &
"263 (BC_1, D5, output3, X, 262, 0, Z)," &
"264 (BC_4, D5, observe_only, X )," &
"265 (BC_1, *, control, 0 )," &
"266 (BC_1, D6, output3, X, 265, 0, Z)," &
"267 (BC_4, D6, observe_only, X )," &
"268 (BC_1, *, control, 0 )," &
"269 (BC_1, D7, output3, X, 268, 0, Z)," &
"270 (BC_4, D7, observe_only, X )," &
"271 (BC_1, *, control, 0 )," &
"272 (BC_1, PD0, output3, X, 271, 0, Z)," &
"273 (BC_4, PD0, observe_only, X )," &
"274 (BC_1, *, control, 0 )," &
"275 (BC_1, PK0, output3, X, 274, 0, Z)," &
"276 (BC_4, PK0, observe_only, X )," &
"277 (BC_1, *, control, 0 )," &
"278 (BC_1, PD1, output3, X, 277, 0, Z)," &
"279 (BC_4, PD1, observe_only, X )," &
"280 (BC_1, *, control, 0 )," &
"281 (BC_1, PK1, output3, X, 280, 0, Z)," &
"282 (BC_4, PK1, observe_only, X )," &
"283 (BC_1, *, control, 0 )," &
"284 (BC_1, PK2, output3, X, 283, 0, Z)," &
"285 (BC_4, PK2, observe_only, X )," &
"286 (BC_1, *, control, 0 )," &
"287 (BC_1, PD2, output3, X, 286, 0, Z)," &
"288 (BC_4, PD2, observe_only, X )," &
"289 (BC_1, *, control, 0 )," &
"290 (BC_1, PK3, output3, X, 289, 0, Z)," &
"291 (BC_4, PK3, observe_only, X )," &
"292 (BC_1, *, control, 0 )," &
"293 (BC_1, PD3, output3, X, 292, 0, Z)," &
"294 (BC_4, PD3, observe_only, X )," &
"295 (BC_1, *, control, 0 )," &
"296 (BC_1, PK4, output3, X, 295, 0, Z)," &
"297 (BC_4, PK4, observe_only, X )," &
"298 (BC_1, *, control, 0 )," &
"299 (BC_1, PD4, output3, X, 298, 0, Z)," &
"300 (BC_4, PD4, observe_only, X )," &
"301 (BC_1, *, control, 0 )," &
"302 (BC_1, PK5, output3, X, 301, 0, Z)," &
"303 (BC_4, PK5, observe_only, X )," &
"304 (BC_1, *, control, 0 )," &
"305 (BC_1, PD5, output3, X, 304, 0, Z)," &
"306 (BC_4, PD5, observe_only, X )," &
"307 (BC_1, *, control, 0 )," &
"308 (BC_1, PK6, output3, X, 307, 0, Z)," &
"309 (BC_4, PK6, observe_only, X )," &
"310 (BC_1, *, control, 0 )," &
"311 (BC_1, PD6, output3, X, 310, 0, Z)," &
"312 (BC_4, PD6, observe_only, X )," &
"313 (BC_1, *, control, 0 )," &
"314 (BC_1, PK7, output3, X, 313, 0, Z)," &
"315 (BC_4, PK7, observe_only, X )," &
"316 (BC_1, *, control, 0 )," &
"317 (BC_1, PD7, output3, X, 316, 0, Z)," &
"318 (BC_4, PD7, observe_only, X )," &
"319 (BC_1, *, control, 0 )," &
"320 (BC_1, PN2, output3, X, 319, 0, Z)," &
"321 (BC_4, PN2, observe_only, X )," &
"322 (BC_1, *, control, 0 )," &
"323 (BC_1, PN3, output3, X, 322, 0, Z)," &
"324 (BC_4, PN3, observe_only, X )," &
"325 (BC_1, *, control, 0 )," &
"326 (BC_1, A0, output3, X, 325, 0, Z)," &
"327 (BC_1, *, control, 0 )," &
"328 (BC_1, A1, output3, X, 327, 0, Z)," &
"329 (BC_1, *, control, 0 )," &
"330 (BC_1, A2, output3, X, 329, 0, Z)," &
"331 (BC_1, *, control, 0 )," &
"332 (BC_1, A3, output3, X, 331, 0, Z)," &
"333 (BC_1, *, control, 0 )," &
"334 (BC_1, A4, output3, X, 333, 0, Z)," &
"335 (BC_1, *, control, 0 )," &
"336 (BC_1, A5, output3, X, 335, 0, Z)," &
"337 (BC_1, *, control, 0 )," &
"338 (BC_1, A6, output3, X, 337, 0, Z)," &
"339 (BC_1, *, control, 0 )," &
"340 (BC_1, A7, output3, X, 339, 0, Z)," &
"341 (BC_1, *, control, 0 )," &
"342 (BC_1, A8, output3, X, 341, 0, Z)," &
"343 (BC_1, *, control, 0 )," &
"344 (BC_1, A9, output3, X, 343, 0, Z)," &
"345 (BC_1, *, control, 0 )," &
"346 (BC_1, A10, output3, X, 345, 0, Z)," &
"347 (BC_1, *, control, 0 )," &
"348 (BC_1, A11, output3, X, 347, 0, Z)," &
"349 (BC_1, *, control, 0 )," &
"350 (BC_1, A12, output3, X, 349, 0, Z)," &
"351 (BC_1, *, control, 0 )," &
"352 (BC_1, A13, output3, X, 351, 0, Z)," &
"353 (BC_1, *, control, 0 )," &
"354 (BC_1, A14, output3, X, 353, 0, Z)," &
"355 (BC_1, *, control, 0 )," &
"356 (BC_1, A15, output3, X, 355, 0, Z)," &
"357 (BC_1, *, control, 0 )," &
"358 (BC_1, PC0, output3, X, 357, 0, Z)," &
"359 (BC_4, PC0, observe_only, X )," &
"360 (BC_1, *, control, 0 )," &
"361 (BC_1, PC1, output3, X, 360, 0, Z)," &
"362 (BC_4, PC1, observe_only, X )," &
"363 (BC_1, *, control, 0 )," &
"364 (BC_1, PC2, output3, X, 363, 0, Z)," &
"365 (BC_4, PC2, observe_only, X )," &
"366 (BC_1, *, control, 0 )," &
"367 (BC_1, PC3, output3, X, 366, 0, Z)," &
"368 (BC_4, PC3, observe_only, X )," &
"369 (BC_1, *, control, 0 )," &
"370 (BC_1, PC4, output3, X, 369, 0, Z)," &
"371 (BC_4, PC4, observe_only, X )," &
"372 (BC_1, *, control, 0 )," &
"373 (BC_1, PC5, output3, X, 372, 0, Z)," &
"374 (BC_4, PC5, observe_only, X )," &
"375 (BC_1, *, control, 0 )," &
"376 (BC_1, PC6, output3, X, 375, 0, Z)," &
"377 (BC_4, PC6, observe_only, X )," &
"378 (BC_1, *, control, 0 )," &
"379 (BC_1, PC7, output3, X, 378, 0, Z)," &
"380 (BC_4, PC7, observe_only, X )";
end LH79524;
