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BSDL File: INTEL_XEON_MP_2MB_0 Download View details  


-- ***************************************************************************
-- Intel(R) Xeon(TM) Processor MP with up to 2-MB L3 Cache Core Boundary
-- Scan Descriptor Language (BSDL) Model, Version 1.1
--
-- A-0 processor core stepping
-- 
-- ***************************************************************************
-- Information in this document is provided in connection with Intel products.
-- No license, express or implied, by estoppel or otherwise, to any
-- intellectual property rights is granted by this document. Except as
-- provided in Intel's Terms and Conditions of Sale for such products,
-- Intel assumes no liability whatsoever, and Intel disclaims any express or
-- implied warranty, relating to sale and/or use of Intel products including
-- liability or warranties relating to fitness for a particular purpose,
-- merchantability, or infringement of any patent, copyright or other
-- intellectual property right. Intel products are not intended for use in
-- medical, life saving, or life sustaining applications.
--
-- Intel may make changes to specifications and product descriptions at any
-- time, without notice.
--
-- The Intel(R) Xeon(TM) Processor MP with up to 2-MB L3 Cache may contain
-- design defects or errors known as errata which may cause the product
-- to deviate from published specifications. Current characterized errata
-- are available on request.
--
-- Contact your local Intel sales office or your distributor to obtain the
-- latest specifications and before placing your product order.
--
-- Intel, Pentium, and Intel Xeon are trademarks or registered trademarks of
-- Intel Corporation and its subsidiaries in the United States and other
-- countries.
--
-- *Other names and brands may be claimed as the property of others.
--
-- Copyright (c) 2002 Intel Corporation
-- ***************************************************************************

entity INTEL_XEON_MP_2MB_0 is

  generic(PHYSICAL_PIN_MAP : string := "INTEL_XEON_MP_2MB_PGAN");

  port (
 	TDO        : out     bit;                 -- Diagnostic    - tap data out
 	TRST       : in      bit;		      -- Diagnostic    - tap reset
 	TMS        : in      bit;		      -- Diagnostic    - tap mode select
 	TDI        : in      bit;		      -- Diagnostic    - tap data in
 	TCK        : in      bit;		      -- Diagnostic    - tap clock
	GTLREF2    : linkage bit;		      -- Analog Pin    - 
  	LINT1      : in      bit;		      -- APIC 	       - Local Interrupt,NMI
 	LINT0      : in      bit;		      -- APIC	       - Local Interrupt,INT
 	BPRI       : in      bit;		      -- Arbitration   - Priority agent bus arbitration
	DEFER      : in      bit;		      -- Snoop         - defer signal 
 	HITM       : inout   bit;		      -- Snoop         - snoop hit modified
 	HIT        : inout   bit;		      -- Snoop         - snoop hit
 	RS         : in      bit_vector(2 downto 0);  -- Response status
 	LOCK       : inout   bit;		      -- Arbitration   - Locked transactions
 	BR0        : inout   bit;		      -- Arbitration   - symmetric agent bus arbitration
 	ADS        : inout   bit;		      -- Request       - address strobe
 	BNR        : inout   bit;		      -- Arbitration   - block next request
 	TRDY       : in      bit;		      -- Response      - target ready   
 	DBSY       : inout   bit;		      -- Data	     - data bus busy
 	DRDY       : inout   bit;		      -- Data	     - Data phase data ready
 	REQ        : inout   bit_vector( 4 downto 0); -- Request   - request command
 	A          : inout   bit_vector(35 downto 3); -- Address bus
 	ADSTB	     : inout   bit_vector( 1 downto 0); -- Request     - address bus strobe
	BR1        : in      bit;		      -- Arbitration   - symmetric bus arbitration
 	BR2        : in      bit;		      -- Arbitration   - symmetric bus arbitration
 	BR3        : in      bit;		      -- Arbitration   - symmetric bus arbitration
 	AP         : inout   bit_vector( 1 downto 0); -- address/extended request parity
 	RSP        : in      bit;		      -- Response      - Response status parity
 	BINIT      : inout   bit;		      -- Error	     - bus initialization
 	MCERR      : inout   bit;		      -- Error	     - machine check error
 	INIT       : in      bit;		      -- Exec Control  - Processor initialization
 	STPCLK     : in      bit;		      -- Pwr/Clk       - processor stop clock control
 	IERR       : out     bit;		      -- Error	     - internal processor error
 	BPM        : inout   bit_vector( 5 downto 0); -- Diagnostic - proformance monitoring break points
	GTLREF3    : linkage bit;		      -- Analog Pin    - 
      VCCA       : linkage bit;		      -- Pwr/Clk       - Analog Vcc for PLL
      VSSA       : linkage bit;		      -- Pwr/Clk       - Analog Vcc for PLL and IOPLL
      VCCIOPLL   : linkage bit;		      -- Pwr/Clk       - Analog Vcc for I/O PLL
      PWRGOOD    : in      bit;		      -- Pwr/Clk       - System Power Good
	SLP        : in      bit;		      -- Pwr/Clk       - Sleep Pin
	RESET      : in      bit;		      -- Control       - System Reset
	RSVD_W3    : in 	   bit;			-- RSVD	
	GTLREF1    : linkage bit;	              -- Analog Pin  - 
 	BCLK0	     : in      bit; 			-- Control       - differential bus clock [N]
	BCLK1	     : in 	   bit; 			-- Control       - differential bus clock [P]
	D          : inout   bit_vector(63 downto 0); -- Data      - data bus 
 	DSTBN      : inout   bit_vector( 3 downto 0); -- Data      - Data bus differential probe
 	DSTBP      : inout   bit_vector( 3 downto 0); -- Data      - Data bus differential probe
 	DBI        : inout   bit_vector( 3 downto 0); -- Data      - dynamic data bus inversion
      COMP       : linkage bit_vector( 1 downto 0); -- Pwr/Clk   - Used to configure the AGTL+ drivers
 	DP         : inout   bit_vector( 3 downto 0); -- Data      - data bus parity on 16-bit granularity
	RSVD_A15   : in 	   bit;			-- RSVD
	GTLREF0    : linkage bit;	              -- Analog Pin  - 
 	VCCSENSE   : linkage bit;		      -- Pwr/Clk       - Sense the Vcc power plane
	VSSSENSE   : linkage bit;		      -- Pwr/Clk       - Sense the Vss power plane
	FERR       : out     bit;		      -- Compatibility - floating point error
 	A20M       : in      bit;		      -- Compatibility - address 20 mask
 	SMI        : in      bit;		      -- Compatibility - system management interrupt
 	IGNNE      : in      bit;		      -- Compatibility - ignore numeric errors
 	THERMTRIP  : out     bit;		      -- Pwr/Clk       - thermal sensor
 	PROCHOT    : out     bit;		      -- Pwr/Clk       - thermal sensor
	BSEL0	     : out	   bit;
	BSEL1	     : out	   bit;
	ODTEN	     : in	   bit;
	RSVD_A1    : linkage bit;
	RSVD_A4    : linkage bit;
	RSVD_A16   : linkage bit;
	RSVD_A26   : linkage bit;
	RSVD_B1    : linkage bit;
	RSVD_C5    : linkage bit;
	RSVD_D25   : linkage bit;
	RSVD_Y3    : linkage bit;
	RSVD_Y27   : linkage bit;
	RSVD_Y28   : linkage bit;
	RSVD_AC1   : linkage bit;
	RSVD_AD1   : linkage bit;
	RSVD_AE4   : linkage bit;
	RSVD_AE15  : linkage bit;
	RSVD_AE16  : linkage bit;
	SKTOCC     : linkage bit;
	SM_ALERT   : out	   bit;
	SM_CLK     : in 	   bit;
	SM_DAT     : inout   bit;
	SM_EP_A0   : in 	   bit;
	SM_EP_A1   : in 	   bit;
	SM_EP_A2   : in 	   bit;
	SM_TS1_A0  : in	   bit;
	SM_TS1_A1  : in	   bit;
	SM_VCC     : linkage bit_vector(1 to 2);
	SM_WP	     : in	   bit;
	TESTHI0    : linkage bit;
	TESTHI1    : linkage bit;
	TESTHI2    : linkage bit;
	TESTHI3    : linkage bit;
	TESTHI4    : linkage bit;
	TESTHI5    : linkage bit;
	TESTHI6    : linkage bit;
	VCC	     : linkage bit_vector(1 to 190);
	VID0	     : linkage bit;
	VID1       : linkage bit;
	VID2       : linkage bit;
	VID3       : linkage bit;
	VID4       : linkage bit;
	VSS	     : linkage bit_vector(1 to 189)
);

  use STD_1149_1_1994.all;
  use INTEL_XEON_MP_2MB_CELLS.all;

  attribute COMPONENT_CONFORMANCE of INTEL_XEON_MP_2MB_0 : entity is "STD_1149_1_1993" ;

  attribute PIN_MAP of INTEL_XEON_MP_2MB_0 : entity is PHYSICAL_PIN_MAP;

  constant INTEL_XEON_MP_2MB_PGAN : PIN_MAP_STRING :=

     " 	TDO        : E25,"  &
     " 	TRST       : F24,"  &
     " 	TMS        : A25,"  &
     " 	TDI        : C24,"  &
     " 	TCK        : E24,"  &
     "	GTLREF2    : F23,"  &
     "	LINT1      : G23,"  &
     " 	LINT0      : B24,"  &
     " 	BPRI       : D23,"  &
     "	DEFER      : C23,"  &
     " 	HITM       : A23,"  &
     " 	HIT        : E22,"  &
     " 	RS         : (F21, D22, E21), "  &
     " 	LOCK       : A17,"  &
     " 	BR0        : D20,"  &
     " 	ADS        : D19,"  &
     " 	BNR        : F20,"  &
     " 	TRDY       : E19,"  &
     " 	DBSY       : F18,"  &
     " 	DRDY       : E18,"  &
     " 	REQ        : (B22, C20, C21, B21, B19),  "               & -- REQ4, REQ3,...,REQ0
     " 	A          : (C8, C9, A7, A6, B7, C11, D12, E13, B8,   " & -- A(35):A(27)
     "                    A9, D13, E14, C12, B11, B10, A10, F15,   " & -- A(26):A(19)
     "                    D15, D16, C14, C15, A12, B13, B14, B16,  " & -- A(18):A(11)
     "                    A13, D17, C17, A19, C18, B18, A20, A22), " & -- A(10):A(3)
     " 	ADSTB	     : (F14, F17), "  &
     "	BR1        : F12,"  &
     " 	BR2        : E11,"  &
     " 	BR3        : D10,"  &
     " 	AP         : (D9, E10), "   &
     " 	RSP        : C6, "  &
     " 	BINIT      : F11,"  &
     " 	MCERR      : D7, "  &
     " 	INIT       : D6, "  &
     " 	STPCLK     : D4, "  &
     " 	IERR       : E5, "  &
     " 	BPM        : (E4, E8, F5, E7, F8, F6) ,"  &
     "	GTLREF3    : F9, "  &
     "	VCCA       : AB4,"  &
     "	VSSA       : AA5,"  &
     "	VCCIOPLL   : AD4,"  &
     "	PWRGOOD    : AB7,"  &
     "	SLP	     : AE6,"  &
     "	RESET	     : Y8, "  &
     "	RSVD_W3    : W3, "  &
     "	GTLREF1    : W9,"   &
     "	BCLK0	     : Y4,"   & -- BCLK0
     "	BCLK1	     : W5,"   & -- BCLK1
     " 	D          : (AB6,  Y9,   AA8,  AC5,  AC6,  AE7,  AD7,  AC8,  " & -- D63:D56
     " 	              AB10, AA10, AA11, AB13, AB12, AC14, AA14, AA13, " & -- D55:D48
     "                    AC9,  AD8,  AD10, AE9,  AC11, AE10, AC12, AD11, " & -- D47:D40
     " 	              AD14, AD13, AB15, AD18, AE13, AC17, AA16, AB16, " & -- D39:D32
     " 	              AB17, AD19, AD21, AE20, AE22, AC21, AC20, AA18, " & -- D31:D24
     " 	              AC23, AE23, AD24, AC24, AE25, AD25, AC26, AE26, " & -- D23:D16
     "                    AA19, AB19, AB22, AB20, AA21, AA22, AB23, AB25, " & -- D15:D8
     " 	              AB26, AA24, Y23,  AD27, AA25, Y24,  AA27, Y26), " & -- D7:D0
     " 	DSTBN      : (Y12,  Y15,  Y18,  Y21) , "  &
     " 	DSTBP      : (Y11,  Y14,  Y17,  Y20) , "  &
     " 	DBI        : (AB9,  AE12, AD22, AC27), "  &                       -- DBI3:DBI0
     "	COMP       : (E16,  AD16),             "  &
     " 	DP         : (AE17, AC15, AE19, AC18), "  &
     "	RSVD_A15   : A15, "  &
     "	GTLREF0    : W23, "  &
     "	VCCSENSE   : B27, "  &
     "	VSSSENSE   : D26, "  &
     "	FERR       : E27, "  &
     " 	A20M       : F27, "  &
     " 	SMI        : C27, "  &
     " 	IGNNE      : C26, "  &
     " 	THERMTRIP  : F26, "  &
     " 	PROCHOT    : B25, "  &
     "	BSEL0	     : AA3, "  &
     "	BSEL1	     : AB3, "  &
     "	ODTEN	     : B5,  "  &
     "	RSVD_A1    : A1,  "  &
     "	RSVD_A4    : A4,  "  &
     "	RSVD_A16   : A16, "  &
     "	RSVD_A26   : A26, "  &
     "	RSVD_B1    : B1,  "  &
     "	RSVD_C5    : C5,  "  &
     "	RSVD_D25   : D25, "  &
     "	RSVD_Y3    : Y3,  "  &
     "	RSVD_Y27   : Y27, "  &
     "	RSVD_Y28   : Y28, "  &
     "	RSVD_AC1   : AC1, "  &
     "	RSVD_AD1   : AD1, "  &
     "	RSVD_AE4   : AE4, "  &
     "	RSVD_AE15  : AE15,"  &
     "	RSVD_AE16  : AE16,"  &
     "	SKTOCC     : A3,  "  &
     "	SM_ALERT   : AD28,"  &
     "	SM_CLK     : AC28,"  &
     "	SM_DAT     : AC29,"  &
     "	SM_EP_A0   : AA29,"  &
     "	SM_EP_A1   : AB29,"  &
     "	SM_EP_A2   : AB28,"  &
     "	SM_TS1_A0  : AA28,"  &
     "	SM_TS1_A1  : Y29, "  &
     "	SM_VCC     : (AE28,  AE29),"  &
     "	SM_WP	     : AD29,"  &
     "	TESTHI0    : W6,  "  &
     "	TESTHI1    : W7,  "  &
     "	TESTHI2    : W8,  "  &
     "	TESTHI3    : Y6,  "  &
     "	TESTHI4    : AA7, "  &
     "	TESTHI5    : AD5, "  &
     "	TESTHI6    : AE5, "  &
     "	VCC	     : (A2,   A8,   A14,  A18,  A24,  A28,  A30,  B4,   B6,   B12,	" & 
     " 	              B20,  B26,  B29,  B31,  C2,   C4,   C10,  C16,  C22,  C28,  	" & 
     "                    C30,  D1,   D8,   D14,  D18,  D24,  D29,  D31,  E2,   E6,		" & 
     " 	              E12,  E20,  E26,  E28,  E30,  F1,   F4,   F10,  F16,  F22,	" & 
     " 	              F29,  F31,  G2,   G4,   G6,   G8,   G24,  G26,  G28,  G30,	" & 
     " 	              H1,   H3,   H5,   H7,   H9,   H23,  H25,  H27,  H29,  H31,	" & 
     "                    J2,   J4,   J6,   J8,   J24,  J26,  J28,  J30,  K1,   K3,		" & 
     " 	              K5,   K7,   K9,   K23,  K25,  K27,  K29,  K31,  L2,   L4,		" &
     " 	              L6,   L8,   L24,  L26,  L28,  L30,  M1,   M3,   M5,   M7,		" & 
     " 	              M9,   M23,  M25,  M27,  M29,  M31,  N1,   N3,   N5,   N7,		" & 
     " 	              N9,   N23,  N25,  N27,  N29,  N31,  P2,   P4,   P6,   P8,		" & 
     " 	              P24,  P26,  P28,  P30,  R1,   R3,   R5,   R7,   R9,   R23,	" & 
     " 	              R25,  R27,  R29,  R31,  T2,   T4,   T6,   T8,   T24,  T26,	" & 
     " 	              T28,  T30,  U1,   U3,   U5,   U7,   U9,   U23,  U25,  U27,	" & 
     " 	              U29,  U31,  V2,   V4,   V6,   V8,   V24,  V26,  V28,  V30,	" & 
     " 	              W1,   W25,  W27,  W29,  W31,  Y10,  Y16,  Y2,   Y22,  Y30,	" & 
     " 	              AA1,  AA4,  AA6,  AA12, AA20, AA26, AA31, AB2,  AB8,  AB14,	" & 
     " 	              AB18, AB24, AB30, AC3,  AC4,  AC10, AC16, AC22, AC31, AD2,	" & 
     " 	              AD6,  AD12, AD20, AD26, AD30, AE3,  AE8,  AE14, AE18, AE24),	" &   
     "	VID0	     : F3,  "  &
     "	VID1       : E3,  "  &
     "	VID2       : D3,  "  &
     "      VID3       : C3,  "  &
     "	VID4       : B3,  "  &
     "	VSS	     : (A5,   A11,  A21,  A27,  A29,  A31,  B2,   B9,   B15,  B17,	" & 
     " 	              B23,  B28,  B30,  C1,   C7,   C13,  C19,  C25,  C29,  C31,  	" & 
     "                    D2,   D5,   D11,  D21,  D27,  D28,  D30,  E1,   E9,   E15,	" & 
     " 	              E17,  E23,  E29,  E31,  F2,   F7,   F13,  F19,  F25,  F28,	" & 
     " 	              F30,  G1,   G3,   G5,   G7,   G9,   G25,  G27,  G29,  G31,	" & 
     " 	              H2,   H4,   H6,   H8,   H24,  H26,  H28,  H30,  J1,   J3,		" & 
     "                    J5,   J7,   J9,   J23,  J25,  J27,  J29,  J31,  K2,   K4,		" & 
     " 	              K6,   K8,   K24,  K26,  K28,  K30,  L1,   L3,   L5,   L7,		" &
     " 	              L9,   L23,  L25,  L27,  L29,  L31,  M2,   M4,   M6,   M8,		" & 
     " 	              M24,  M26,  M28,  M30,  N2,   N4,   N6,   N8,   N24,  N26,	" & 
     " 	              N28,  N30,  P1,   P3,   P5,   P7,   P9,   P23,  P25,  P27,	" & 
     " 	              P29,  P31,  R2,   R4,   R6,   R8,   R24,  R26,  R28,  R30,	" & 
     " 	              T1,   T3,   T5,   T7,   T9,   T23,  T25,  T27,  T29,  T31,	" & 
     " 	              U2,   U4,   U6,   U8,   U24,  U26,  U28,  U30,  V1,   V3,		" & 
     " 	              V5,   V7,   V9,   V23,  V25,  V27,  V29,  V31,  W2,   W4,		" & 
     " 	              W24,  W26,  W28,  W30,  Y1,   Y5,   Y7,   Y13,  Y19,  Y25,	" & 
     " 	              Y31,  AA2,  AA9,  AA15, AA17, AA23, AA30, AB1,  AB5,  AB11,	" & 
     " 	              AB21, AB27, AB31, AC2,  AC7,  AC13, AC19, AC25, AC30, AD3,	" & 
     " 	              AD9,  AD15, AD17, AD23, AD31, AE2,  AE11, AE21, AE27)		"  
  ;

--
-- Scan Port Identification
--

  attribute TAP_SCAN_IN    of TDI  : signal is true;
  attribute TAP_SCAN_MODE  of TMS  : signal is true;
  attribute TAP_SCAN_OUT   of TDO  : signal is true;
  attribute TAP_SCAN_RESET of TRST : signal is true;
  attribute TAP_SCAN_CLOCK of TCK  : signal is (25.0e6, both);

  attribute Instruction_Length of INTEL_XEON_MP_2MB_0: entity is 7;

  attribute Instruction_Opcode of INTEL_XEON_MP_2MB_0: entity is

	" EXTEST   ( 0000000 ),                             "  &
	" SAMPLE   ( 0000001 ),					    "  &
	" IDCODE   ( 0000010 ),					    "  &
	" CLAMP    ( 0000100 ),					    "  &
	" RUNBIST  ( 0000111 ),					    "  &
	" HIGHZ    ( 0001000 ),					    "  &
	" BYPASS   ( 1111111 ),					    "  &
	" Reserved ( 0000011, 0000101, 0000110, 0001001, 0001010,   "  &
	"            0001011, 0001100, 0001101, 0001110, 0001111,   "  &
	"            0010000, 0010001, 0010010, 0010011, 0010100,   "  &
	"            0010101, 0010110, 0010111, 0011000, 0011001,   "  &
	"            0011010, 0011011, 0011100, 0011101, 0011110,   "  &
	"            0011111, 0100000, 0100001, 0100010, 0100011,   "  &
	"            0100100, 0100101, 0100110, 0100111, 0101000,   "  &
	"            0101001, 0101010, 0101011, 0101100, 0101101,   "  &
	"            0101110, 0101111, 0110000, 0110001, 0110010,   "  &
	"            0110011, 0110100, 0110101, 0110110, 0110111,   "  &
	"            0111000, 0111001, 0111010, 0111011, 0111100,   "  &
	"            0111101, 0111110, 0111111, 1000000, 1000001,   "  &
	"            1000010, 1000011, 1000100, 1000101, 1000110,   "  &
	"            1000111, 1001000, 1001001, 1001100           ) "  ;  

  attribute Instruction_Capture of INTEL_XEON_MP_2MB_0: entity is "0000001";
  attribute Instruction_Private of INTEL_XEON_MP_2MB_0: entity is "Reserved";

--
-- A-0 Stepping IDCODE Register
--

  attribute Idcode_Register of INTEL_XEON_MP_2MB_0: entity is
	    "0010"             &     -- A-0 stepping
	    "1000001100000011" &     -- Part number
	    "00000001001"      &     -- Manufacturer's identity
	    "1";                     -- Required by the 1149.1 standard

--
-- Data Register Access
--

  attribute Register_Access of INTEL_XEON_MP_2MB_0: entity is

	    "BOUNDARY   (EXTEST, SAMPLE), "       &
	    "RUNBIST[1] (RUNBIST), "              &
	    "DEVICE_ID  (IDCODE), "               &
	    "BYPASS     (CLAMP, HIGHZ, BYPASS)";

--
--  Boundary Scan cells
--
--    BS_4 : INPUT
--    BC_2 : OUTPUT2
--    BS_G : GTL BIDIR/CONTROL Combo cell
--
--    Boundary Register Description
--    Cell 0 is closest to TDO
--
  attribute BOUNDARY_LENGTH   of INTEL_XEON_MP_2MB_0 : entity is 166;

  attribute Boundary_Register of INTEL_XEON_MP_2MB_0 : entity is

--                   	
 	" 0   (BS_4,  LINT1,  	 input,     X                       		), " &
 	" 1   (BS_4,  LINT0,  	 input,     X                       		), " &
 	" 2   (BS_4,  BPRI,      input,     X                       		), " &
 	" 3   (BS_4,  DEFER,     input,     X                       		), " &
 	" 4   (BS_G,  HITM,      output2,   1,      4,  	1,    	Weak1 ), " &
 	" 4   (BS_G,  HITM,      input,     1                       		), " &
	" 5   (BS_G,  HIT,       output2,   1,      5,  	1,    	Weak1 ), " &
 	" 5   (BS_G,  HIT,       input,     1                       		), " &
 	" 6   (BS_4,  RS(2),     input,     X                       		), " &
 	" 7   (BS_4,  RS(1),     input,     X                       		), " &
 	" 8   (BS_4,  RS(0),     input,     X                       		), " &
 	" 9   (BS_G,  LOCK,      output2,   1,      9,  	1,    	Weak1 ), " &
 	" 9   (BS_G,  LOCK,      input,     1                       		), " &
 	" 10  (BS_G,  BR0,       output2,   1,     10,  	1,    	Weak1 ), " &
 	" 10  (BS_G,  BR0,       input,     1                       		), " &
 	" 11  (BS_G,  ADS,       output2,   1,     11,  	1,    	Weak1 ), " &
 	" 11  (BS_G,  ADS,       input,     1                       		), " &
 	" 12  (BS_G,  BNR,       output2,   1,     12,  	1,    	Weak1 ), " &
 	" 12  (BS_G,  BNR,       input,     1                       		), " &
 	" 13  (BS_4,  TRDY,      input,     X                       		), " &
 	" 14  (BS_G,  DBSY,      output2,   1,     14,  	1,    	Weak1 ), " &
 	" 14  (BS_G,  DBSY,      input,     1                       		), " &
 	" 15  (BS_G,  DRDY,      output2,   1,     15,  	1,    	Weak1 ), " &
 	" 15  (BS_G,  DRDY,      input,     1                       		), " &
 	" 16  (BS_G,  REQ(4),    output2,   1,     16,  	1,    	Weak1 ), " &
 	" 16  (BS_G,  REQ(4),    input,     1                       		), " &
 	" 17  (BS_G,  REQ(3),    output2,   1,     17,  	1,    	Weak1 ), " &
 	" 17  (BS_G,  REQ(3),    input,     1                       		), " &
 	" 18  (BS_G,  REQ(2),    output2,   1,     18,  	1,    	Weak1 ), " &
 	" 18  (BS_G,  REQ(2),    input,     1                       		), " &
 	" 19  (BS_G,  REQ(1),    output2,   1,     19,  	1,    	Weak1 ), " &
 	" 19  (BS_G,  REQ(1),    input,     1                       		), " &
 	" 20  (BS_G,  REQ(0),    output2,   1,     20,  	1,    	Weak1 ), " &
 	" 20  (BS_G,  REQ(0),    input,     1                       		), " &
 	" 21  (BS_G,  A(3),      output2,   1,     21,  	1,    	Weak1 ), " &
 	" 21  (BS_G,  A(3),      input,     1                       		), " &
 	" 22  (BS_G,  A(4),      output2,   1,     22,  	1,    	Weak1 ), " &
 	" 22  (BS_G,  A(4),      input,     1                       		), " &
 	" 23  (BS_G,  A(5),      output2,   1,     23,  	1,    	Weak1 ), " &
 	" 23  (BS_G,  A(5),      input,     1                       		), " &
 	" 24  (BS_G,  A(6),      output2,   1,     24,  	1,    	Weak1 ), " &
 	" 24  (BS_G,  A(6),      input,     1                       		), " &
 	" 25  (BS_G,  A(7),      output2,   1,     25,  	1,    	Weak1 ), " &
 	" 25  (BS_G,  A(7),      input,     1                       		), " &
 	" 26  (BS_G,  ADSTB(0),  output2,   1,     26,  	1,    	Weak1 ), " &
 	" 26  (BS_G,  ADSTB(0),  input,     1                       		), " &
 	" 27  (BS_G,  A(8),      output2,   1,     27,  	1,    	Weak1 ), " &
 	" 27  (BS_G,  A(8),      input,     1                       		), " &
 	" 28  (BS_G,  A(9),      output2,   1,     28,  	1,    	Weak1 ), " &
 	" 28  (BS_G,  A(9),      input,     1                       		), " &
 	" 29  (BS_G,  A(10),     output2,   1,     29,  	1,    	Weak1 ), " &
 	" 29  (BS_G,  A(10),     input,     1                       		), " &
 	" 30  (BS_G,  A(11),     output2,   1,     30,  	1,    	Weak1 ), " &
 	" 30  (BS_G,  A(11),     input,     1                       		), " &
 	" 31  (BS_G,  A(13),     output2,   1,     31,  	1,    	Weak1 ), " &
 	" 31  (BS_G,  A(13),     input,     1                       		), " &
 	" 32  (BS_G,  A(12),     output2,   1,     32,  	1,    	Weak1 ), " &
 	" 32  (BS_G,  A(12),     input,     1                       		), " &
 	" 33  (BS_G,  A(14),     output2,   1,     33,  	1,    	Weak1 ), " &
 	" 33  (BS_G,  A(14),     input,     1                       		), " &
 	" 34  (BS_G,  A(15),     output2,   1,     34,  	1,    	Weak1 ), " &
 	" 34  (BS_G,  A(15),     input,     1                       		), " &
 	" 35  (BS_G,  A(16),     output2,   1,     35,  	1,    	Weak1 ), " &
 	" 35  (BS_G,  A(16),     input,     1                       		), " &
 	" 36  (BS_G,  A(17),     output2,   1,     36,  	1,    	Weak1 ), " &
 	" 36  (BS_G,  A(17),     input,     1                       		), " &
 	" 37  (BS_G,  A(18),     output2,   1,     37,  	1,    	Weak1 ), " &
 	" 37  (BS_G,  A(18),     input,     1                       		), " &
 	" 38  (BS_G,  A(19),     output2,   1,     38,  	1,    	Weak1 ), " &
 	" 38  (BS_G,  A(19),     input,     1                       		), " &
 	" 39  (BS_G,  A(20),     output2,   1,     39,  	1,    	Weak1 ), " &
 	" 39  (BS_G,  A(20),     input,     1                       		), " &
 	" 40  (BS_G,  A(21),     output2,   1,     40,  	1,    	Weak1 ), " &
 	" 40  (BS_G,  A(21),     input,     1                       		), " &
 	" 41  (BS_G,  A(22),     output2,   1,     41,  	1,    	Weak1 ), " &
 	" 41  (BS_G,  A(22),     input,     1                       		), " &
 	" 42  (BS_G,  A(23),     output2,   1,     42,  	1,    	Weak1 ), " &
 	" 42  (BS_G,  A(23),     input,     1                       		), " &
 	" 43  (BS_G,  A(24),     output2,   1,     43,  	1,    	Weak1 ), " &
 	" 43  (BS_G,  A(24),     input,     1                       		), " &
 	" 44  (BS_G,  A(25),     output2,   1,     44,  	1,    	Weak1 ), " &
 	" 44  (BS_G,  A(25),     input,     1                       		), " &
 	" 45  (BS_G,  A(26),     output2,   1,     45,  	1,    	Weak1 ), " &
 	" 45  (BS_G,  A(26),     input,     1                       		), " &
 	" 46  (BS_G,  ADSTB(1),  output2,   1,     46,  	1,    	Weak1 ), " &
 	" 46  (BS_G,  ADSTB(1),  input,     1                       		), " &
 	" 47  (BS_G,  A(27),     output2,   1,     47,  	1,    	Weak1 ), " &
 	" 47  (BS_G,  A(27),     input,     1                       		), " &
 	" 48  (BS_G,  A(28),     output2,   1,     48,  	1,    	Weak1 ), " &
 	" 48  (BS_G,  A(28),     input,     1                       		), " &
 	" 49  (BS_G,  A(29),     output2,   1,     49,  	1,    	Weak1 ), " &
 	" 49  (BS_G,  A(29),     input,     1                       		), " &
 	" 50  (BS_G,  A(30),     output2,   1,     50,  	1,    	Weak1 ), " &
 	" 50  (BS_G,  A(30),     input,     1                       		), " &
 	" 51  (BS_G,  A(31),     output2,   1,     51,  	1,    	Weak1 ), " &
 	" 51  (BS_G,  A(31),     input,     1                       		), " &
 	" 52  (BS_G,  A(32),     output2,   1,     52,  	1,    	Weak1 ), " &
 	" 52  (BS_G,  A(32),     input,     1                       		), " &
 	" 53  (BS_G,  A(33),     output2,   1,     53,  	1,    	Weak1 ), " &
 	" 53  (BS_G,  A(33),     input,     1                       		), " &
 	" 54  (BS_G,  A(34),     output2,   1,     54,  	1,    	Weak1 ), " &
 	" 54  (BS_G,  A(34),     input,     1                       		), " &
 	" 55  (BS_G,  A(35),     output2,   1,     55,  	1,    	Weak1 ), " &
 	" 55  (BS_G,  A(35),     input,     1                       		), " &
 	" 56  (BS_4,  BR1,       input,     X                       		), " &
 	" 57  (BS_4,  BR2,       input,     X                       		), " &
 	" 58  (BS_4,  BR3,       input,     X                       		), " &
 	" 59  (BS_G,  AP(1),     output2,   1,     59,  	1,    	Weak1 ), " &
 	" 59  (BS_G,  AP(1),     input,     1                       		), " &
 	" 60  (BS_G,  AP(0),     output2,   1,     60,  	1,    	Weak1 ), " &
 	" 60  (BS_G,  AP(0),     input,     1                       		), " &
 	" 61  (BS_4,  RSP,       input,     X                       		), " &
 	" 62  (BS_G,  BINIT,     output2,   1,     62,  	1,    	Weak1 ), " &
 	" 62  (BS_G,  BINIT,     input,     1                       		), " &
 	" 63  (BS_G,  MCERR,     output2,   1,     63,  	1,    	Weak1 ), " &
 	" 63  (BS_G,  MCERR,     input,     1                       		), " &
 	" 64  (BS_4,  INIT,      input,     X                       		), " &
 	" 65  (BS_4,  STPCLK,    input,     X                       		), " &
 	" 66  (BC_2,  IERR,      output2,   1,     66,  	1,    	Weak1 ), " &
 	" 67  (BS_G,  BPM(5),    output2,   1,     67,  	1,    	Weak1 ), " &
 	" 67  (BS_G,  BPM(5),    input,     1                       		), " &
 	" 68  (BS_G,  BPM(4),    output2,   1,     68,  	1,    	Weak1 ), " &
 	" 68  (BS_G,  BPM(4),    input,     1                       		), " &
 	" 69  (BS_G,  BPM(3),    output2,   1,     69,  	1,    	Weak1 ), " &
 	" 69  (BS_G,  BPM(3),    input,     1                       		), " &
 	" 70  (BS_G,  BPM(2),    output2,   1,     70,  	1,    	Weak1 ), " &
 	" 70  (BS_G,  BPM(2),    input,     1                       		), " &
 	" 71  (BS_G,  BPM(1),    output2,   1,     71,  	1,    	Weak1 ), " &
 	" 71  (BS_G,  BPM(1),    input,     1                       		), " &
 	" 72  (BS_G,  BPM(0),    output2,   1,     72,  	1,    	Weak1 ), " &
 	" 72  (BS_G,  BPM(0),    input,     1                       		), " &
 	" 73  (BS_G,  BCLK0,     input,     X                       		), " &
 	" 74  (BS_G,  BCLK1,     input,     X                       		), " &
 	" 75  (BS_4,  PWRGOOD,   input,     0                       		), " &
 	" 76  (BS_4,  SLP,       input,     1                       		), " &
 	" 77  (BS_4,  RESET,     input,     1                       		), " &
 	" 78  (BS_4,  RSVD_W3,   input,     1                       		), " &
 	" 79  (BS_G,  D(62),     output2,   1,     79,  	1,    	Weak1 ), " &
 	" 79  (BS_G,  D(62),     input,     1                       		), " &
 	" 80  (BS_G,  D(63),     output2,   1,     80,  	1,    	Weak1 ), " &
 	" 80  (BS_G,  D(63),     input,     1                       		), " &
 	" 81  (BS_G,  D(61),     output2,   1,     81,  	1,    	Weak1 ), " &
 	" 81  (BS_G,  D(61),     input,     1                       		), " &
 	" 82  (BS_G,  D(60),     output2,   1,     82,  	1,    	Weak1 ), " &
 	" 82  (BS_G,  D(60),     input,     1                       		), " &
 	" 83  (BS_G,  D(59),     output2,   1,     83,  	1,    	Weak1 ), " &
 	" 83  (BS_G,  D(59),     input,     1                       		), " &
 	" 84  (BS_G,  D(58),     output2,   1,     84,  	1,    	Weak1 ), " &
 	" 84  (BS_G,  D(58),     input,     1                       		), " &
 	" 85  (BS_G,  D(56),     output2,   1,     85,  	1,    	Weak1 ), " &
 	" 85  (BS_G,  D(56),     input,     1                       		), " &
 	" 86  (BS_G,  D(57),     output2,   1,     86,  	1,    	Weak1 ), " &
 	" 86  (BS_G,  D(57),     input,     1                       		), " &
 	" 87  (BS_G,  DSTBN(3),  output2,   1,     87,  	1,    	Weak1 ), " &
 	" 87  (BS_G,  DSTBN(3),  input,     1                       		), " &
 	" 88  (BS_G,  DSTBP(3),  output2,   1,     88,  	1,    	Weak1 ), " &
 	" 88  (BS_G,  DSTBP(3),  input,     1                       		), " &
 	" 89  (BS_G,  DBI(3),    output2,   1,     89,  	1,    	Weak1 ), " &
 	" 89  (BS_G,  DBI(3),    input,     1                       		), " &
 	" 90  (BS_G,  D(55),     output2,   1,     90,  	1,    	Weak1 ), " &
 	" 90  (BS_G,  D(55),     input,     1                       		), " &
 	" 91  (BS_G,  D(54),     output2,   1,     91,  	1,    	Weak1 ), " &
 	" 91  (BS_G,  D(54),     input,     1                       		), " &
 	" 92  (BS_G,  D(53),     output2,   1,     92,  	1,    	Weak1 ), " &
 	" 92  (BS_G,  D(53),     input,     1                       		), " &
 	" 93  (BS_G,  D(51),     output2,   1,     93,  	1,    	Weak1 ), " &
 	" 93  (BS_G,  D(51),     input,     1                       		), " &
 	" 94  (BS_G,  D(52),     output2,   1,     94,  	1,    	Weak1 ), " &
 	" 94  (BS_G,  D(52),     input,     1                       		), " &
 	" 95  (BS_G,  D(50),     output2,   1,     95,  	1,    	Weak1 ), " &
 	" 95  (BS_G,  D(50),     input,     1                       		), " &
 	" 96  (BS_G,  D(49),     output2,   1,     96,  	1,    	Weak1 ), " &
 	" 96  (BS_G,  D(49),     input,     1                       		), " &
 	" 97  (BS_G,  D(48),     output2,   1,     97,  	1,    	Weak1 ), " &
 	" 97  (BS_G,  D(48),     input,     1                       		), " &
 	" 98  (BS_G,  D(47),     output2,   1,     98,  	1,    	Weak1 ), " &
 	" 98  (BS_G,  D(47),     input,     1                       		), " &
 	" 99  (BS_G,  D(46),     output2,   1,     99,  	1,    	Weak1 ), " &
 	" 99  (BS_G,  D(46),     input,     1                       		), " &
 	" 100 (BS_G,  D(45),     output2,   1,    100,  	1,    	Weak1 ), " &
 	" 100 (BS_G,  D(45),     input,     1                       		), " &
 	" 101 (BS_G,  D(44),     output2,   1,    101,  	1,    	Weak1 ), " &
 	" 101 (BS_G,  D(44),     input,     1                       		), " &
 	" 102 (BS_G,  D(43),     output2,   1,    102,  	1,    	Weak1 ), " &
 	" 102 (BS_G,  D(43),     input,     1                       		), " &
 	" 103 (BS_G,  D(42),     output2,   1,    103,  	1,    	Weak1 ), " &
 	" 103 (BS_G,  D(42),     input,     1                       		), " &
 	" 104 (BS_G,  D(41),     output2,   1,    104,  	1,    	Weak1 ), " &
 	" 104 (BS_G,  D(41),     input,     1                       		), " &
 	" 105 (BS_G,  D(40),     output2,   1,    105,  	1,    	Weak1 ), " &
 	" 105 (BS_G,  D(40),     input,     1                       		), " &
 	" 106 (BS_G,  DSTBN(2),  output2,   1,    106,  	1,    	Weak1 ), " &
 	" 106 (BS_G,  DSTBN(2),  input,     1                       		), " &
 	" 107 (BS_G,  DSTBP(2),  output2,   1,    107,  	1,    	Weak1 ), " &
 	" 107 (BS_G,  DSTBP(2),  input,     1                       		), " &
 	" 108 (BS_G,  DBI(2),    output2,   1,    108,  	1,    	Weak1 ), " &
 	" 108 (BS_G,  DBI(2),    input,     1                       		), " &
 	" 109 (BS_G,  D(38),     output2,   1,    109,  	1,    	Weak1 ), " &
 	" 109 (BS_G,  D(38),     input,     1                       		), " &
 	" 110 (BS_G,  D(39),     output2,   1,    110,  	1,    	Weak1 ), " &
 	" 110 (BS_G,  D(39),     input,     1                       		), " &
 	" 111 (BS_G,  D(37),     output2,   1,    111,  	1,    	Weak1 ), " &
 	" 111 (BS_G,  D(37),     input,     1                       		), " &
 	" 112 (BS_G,  D(35),     output2,   1,    112,  	1,    	Weak1 ), " &
 	" 112 (BS_G,  D(35),     input,     1                       		), " &
 	" 113 (BS_G,  D(36),     output2,   1,    113,  	1,    	Weak1 ), " &
 	" 113 (BS_G,  D(36),     input,     1                       		), " &
 	" 114 (BS_G,  D(34),     output2,   1,    114,  	1,    	Weak1 ), " &
 	" 114 (BS_G,  D(34),     input,     1                       		), " &
 	" 115 (BS_G,  D(33),     output2,   1,    115,  	1,    	Weak1 ), " &
 	" 115 (BS_G,  D(33),     input,     1                       		), " &
 	" 116 (BS_G,  D(32),     output2,   1,    116,  	1,    	Weak1 ), " &
 	" 116 (BS_G,  D(32),     input,     1                       		), " &
 	" 117 (BS_G,  DP(3),     output2,   1,    117,  	1,    	Weak1 ), " &
 	" 117 (BS_G,  DP(3),     input,     1                       		), " &
 	" 118 (BS_G,  DP(2),     output2,   1,    118,  	1,    	Weak1 ), " &
 	" 118 (BS_G,  DP(2),     input,     1                       		), " &
 	" 119 (BS_G,  DP(1),     output2,   1,    119,  	1,    	Weak1 ), " &
 	" 119 (BS_G,  DP(1),     input,     1                       		), " &
 	" 120 (BS_G,  DP(0),     output2,   1,    120,  	1,    	Weak1 ), " &
 	" 120 (BS_G,  DP(0),     input,     1                       		), " &
 	" 121 (BS_G,  D(31),     output2,   1,    121,  	1,    	Weak1 ), " &
 	" 121 (BS_G,  D(31),     input,     1                       		), " &
 	" 122 (BS_G,  D(28),     output2,   1,    122,  	1,    	Weak1 ), " &
 	" 122 (BS_G,  D(28),     input,     1                       		), " &
 	" 123 (BS_G,  D(29),     output2,   1,    123,  	1,    	Weak1 ), " &
 	" 123 (BS_G,  D(29),     input,     1                       		), " &
 	" 124 (BS_G,  D(30),     output2,   1,    124,  	1,    	Weak1 ), " &
 	" 124 (BS_G,  D(30),     input,     1                       		), " &
 	" 125 (BS_G,  D(27),     output2,   1,    125,  	1,    	Weak1 ), " &
 	" 125 (BS_G,  D(27),     input,     1                       		), " &
 	" 126 (BS_G,  D(26),     output2,   1,    126,  	1,    	Weak1 ), " &
 	" 126 (BS_G,  D(26),     input,     1                       		), " &
 	" 127 (BS_G,  D(25),     output2,   1,    127,  	1,    	Weak1 ), " &
 	" 127 (BS_G,  D(25),     input,     1                       		), " &
 	" 128 (BS_G,  D(24),     output2,   1,    128,  	1,    	Weak1 ), " &
 	" 128 (BS_G,  D(24),     input,     1                       		), " &
 	" 129 (BS_G,  DSTBN(1),  output2,   1,    129,  	1,    	Weak1 ), " &
 	" 129 (BS_G,  DSTBN(1),  input,     1                       		), " &
 	" 130 (BS_G,  DSTBP(1),  output2,   1,    130,  	1,    	Weak1 ), " &
 	" 130 (BS_G,  DSTBP(1),  input,     1                       		), " &
 	" 131 (BS_G,  DBI(1),    output2,   1,    131,  	1,    	Weak1 ), " &
 	" 131 (BS_G,  DBI(1),    input,     1                       		), " &
 	" 132 (BS_G,  D(22),     output2,   1,    132,  	1,    	Weak1 ), " &
 	" 132 (BS_G,  D(22),     input,     1                       		), " &
 	" 133 (BS_G,  D(23),     output2,   1,    133,  	1,    	Weak1 ), " &
 	" 133 (BS_G,  D(23),     input,     1                       		), " &
 	" 134 (BS_G,  D(21),     output2,   1,    134,  	1,    	Weak1 ), " &
 	" 134 (BS_G,  D(21),     input,     1                       		), " &
 	" 135 (BS_G,  D(20),     output2,   1,    135,  	1,    	Weak1 ), " &
 	" 135 (BS_G,  D(20),     input,     1                       		), " &
 	" 136 (BS_G,  D(19),     output2,   1,    136,  	1,    	Weak1 ), " &
 	" 136 (BS_G,  D(19),     input,     1                       		), " &
 	" 137 (BS_G,  D(18),     output2,   1,    137,  	1,    	Weak1 ), " &
 	" 137 (BS_G,  D(18),     input,     1                       		), " &
 	" 138 (BS_G,  D(16),     output2,   1,    138,  	1,    	Weak1 ), " &
 	" 138 (BS_G,  D(16),     input,     1                       		), " &
 	" 139 (BS_G,  D(17),     output2,   1,    139,  	1,    	Weak1 ), " &
 	" 139 (BS_G,  D(17),     input,     1                       		), " &
 	" 140 (BS_G,  D(15),     output2,   1,    140,  	1,    	Weak1 ), " &
 	" 140 (BS_G,  D(15),     input,     1                       		), " &
 	" 141 (BS_G,  D(14),     output2,   1,    141,  	1,    	Weak1 ), " &
 	" 141 (BS_G,  D(14),     input,     1                       		), " &
 	" 142 (BS_G,  D(12),     output2,   1,    142,  	1,    	Weak1 ), " &
 	" 142 (BS_G,  D(12),     input,     1                       		), " &
 	" 143 (BS_G,  D(13),     output2,   1,    143,  	1,    	Weak1 ), " &
 	" 143 (BS_G,  D(13),     input,     1                       		), " &
 	" 144 (BS_G,  D(11),     output2,   1,    144,  	1,    	Weak1 ), " &
 	" 144 (BS_G,  D(11),     input,     1                       		), " &
 	" 145 (BS_G,  D(10),     output2,   1,    145,  	1,    	Weak1 ), " &
 	" 145 (BS_G,  D(10),     input,     1                       		), " &
 	" 146 (BS_G,  D(9),      output2,   1,    146,  	1,    	Weak1 ), " &
 	" 146 (BS_G,  D(9),      input,     1                       		), " &
 	" 147 (BS_G,  D(8),      output2,   1,    147,  	1,    	Weak1 ), " &
 	" 147 (BS_G,  D(8),      input,     1                       		), " &
 	" 148 (BS_G,  DSTBN(0),  output2,   1,    148,  	1,    	Weak1 ), " &
 	" 148 (BS_G,  DSTBN(0),  input,     1                       		), " &
 	" 149 (BS_G,  DSTBP(0),  output2,   1,    149,  	1,    	Weak1 ), " &
 	" 149 (BS_G,  DSTBP(0),  input,     1                       		), " &
 	" 150 (BS_G,  DBI(0),    output2,   1,    150,  	1,    	Weak1 ), " &
 	" 150 (BS_G,  DBI(0),    input,     1                       		), " &
 	" 151 (BS_G,  D(7),      output2,   1,    151,  	1,    	Weak1 ), " &
 	" 151 (BS_G,  D(7),      input,     1                       		), " &
 	" 152 (BS_G,  D(5),      output2,   1,    152,  	1,    	Weak1 ), " &
 	" 152 (BS_G,  D(5),      input,     1                       		), " &
 	" 153 (BS_G,  D(6),      output2,   1,    153,  	1,    	Weak1 ), " &
 	" 153 (BS_G,  D(6),      input,     1                       		), " &
 	" 154 (BS_G,  D(3),      output2,   1,    154,  	1,    	Weak1 ), " &
 	" 154 (BS_G,  D(3),      input,     1                       		), " &
 	" 155 (BS_G,  D(4),      output2,   1,    155,  	1,    	Weak1 ), " &
 	" 155 (BS_G,  D(4),      input,     1                       		), " &
 	" 156 (BS_G,  D(2),      output2,   1,    156,  	1,    	Weak1 ), " &
 	" 156 (BS_G,  D(2),      input,     1                       		), " &
 	" 157 (BS_G,  D(1),      output2,   1,    157,  	1,    	Weak1 ), " &
 	" 157 (BS_G,  D(1),      input,     1                       		), " &
 	" 158 (BS_G,  D(0),      output2,   1,    158,  	1,    	Weak1 ), " &
 	" 158 (BS_G,  D(0),      input,     1                       		), " &
 	" 159 (BS_G,  RSVD_A15,  input,     X                       		), " &
 	" 160 (BC_2,  FERR,      output2,   1,    160,  	1,    	Weak1 ), " &
 	" 161 (BS_4,  A20M,      input,     X                       		), " &
 	" 162 (BS_4,  SMI,       input,     X                       		), " &
 	" 163 (BS_4,  IGNNE,     input,     X                       		), " &
 	" 164 (BC_2,  THERMTRIP, output2,   1,    164,  	1,    	Weak1 ), " &
 	" 165 (BC_2,  PROCHOT,   output2,   1,    165,  	1,    	Weak1 )  " ;   

end INTEL_XEON_MP_2MB_0;

This library contains 7714 BSDL files (for 6086 distinct entities) from 64 vendors
Last BSDL model (CY7C1512KV18) was added on Sep 15, 2017 14:30
info@bsdl.info