-- GSI 8180VD18 PBGA J T A G S O F T W A R E
-- BSDL File Generated: 29 July 2003
--
-- Revision History:
entity GS8180VD18 is
generic (PHYSICAL_PIN_MAP : string := "BGA_PACKAGE");
port (
ADDR: in bit_vector(0 to 17);
Cbar: in bit;
C: in bit;
nR: in bit;
nBW1: in bit;
nBW2: in bit;
K: in bit;
Kbar: in bit;
ZQ: in bit;
nW: in bit;
D: in bit_vector(0 to 17);
Q: inout bit_vector(0 to 17);
TMS: in bit;
TDI: in bit;
TDO: out bit;
TCK: in bit;
VREF: linkage bit_vector(0 to 1);
VDD: linkage bit_vector(0 to 9);
VSS: linkage bit_vector(0 to 25);
VDDQ: linkage bit_vector(0 to 15);
NC: linkage bit_vector(0 to 42)
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of GS8180VD18 : entity is
"STD_1149_1_1993";
attribute PIN_MAP of GS8180VD18 : entity is PHYSICAL_PIN_MAP;
constant BGA_PACKAGE : PIN_MAP_STRING :=
"ADDR: (N6,P7,N7,R7,R8,P8,R9,B8,C7,C5, " &
"B4,R3,R4,P4,P5,N5,R5,A9), " &
"TMS: R10," &
"TDI: R11," &
"TDO: R1," &
"TCK: R2," &
"Cbar: R6, " &
"C: P6," &
"nR: A8," &
"nBW1: B7, " &
"nBW2: A5, " &
"K: B6, " &
"Kbar: A6," &
"nW: A4, " &
"Q: (P11,M10,L11,K11,J10,F11,E11,C10,B11," &
"B2,D3,E3,F2,G3,K3,L2,N3,P3), " &
"D: (P10,N11,M11,K10,J11,G11,E10,D11,C11,B3,C3," &
"D2,F3,G2,J3,L3,M3,N2), " &
"ZQ: H11, " &
"VREF: (H2,H10)," &
"VDD: (F5,F7,G5,G7,H5,H7,J5,J7,K5,K7), " &
"VSS: (C4,C8,D4,D5,D6,D7,D8,E5,E6,E7,F6,G6,H6,J6,K6,L5,L6, " &
"C6,L7,M4,M5,M6,M7,M8,N4,N8), " &
"VDDQ: (E4,E8,F4,F8,G4,G8,H3,H4,H8,H9,J4,J8,K4,K8,L4,L8)," &
"NC: (A2,A3,A10,B1,B5,B9,B10,C1,C2,C9,D1,D9,D10, " &
"E1,E2,E9,F1,F9,F10,G1,G9,G10,J1,J2,J9,K1,K2,K9, " &
"L1,L9,L10,M1,M2,M9,N1,N9,N10,P1,P2,P9,A1,A11,H1)";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute INSTRUCTION_LENGTH of GS8180VD18 : entity is 3;
attribute INSTRUCTION_OPCODE of GS8180VD18 : entity is
"EXTEST (000)," &
"SAMPLE (100)," &
"PRELOAD (100)," &
"IDCODE (001)," &
"SAMPLZ (010)," &
"BYPASS (111)";
attribute INSTRUCTION_CAPTURE of GS8180VD18 : entity is "X01";
attribute IDCODE_REGISTER of GS8180VD18 : entity is
"0000" & -- Die Revision Code
"0000" & -- Not Used
"110100001010" & -- I/O Configuration 0011 is x18
"00011011001" & -- GSI JEDEC Vendor ID Code
"1"; -- Presence Register (1149.1 requirement)
attribute REGISTER_ACCESS of GS8180VD18 : entity is
"BOUNDARY (EXTEST,SAMPLE,SAMPLZ),"&
"DEVICE_ID (IDCODE),"&
"BYPASS (BYPASS)";
attribute BOUNDARY_LENGTH of GS8180VD18 : entity is 107;
attribute BOUNDARY_REGISTER of GS8180VD18 : entity is
-- num cell port func safe [ccell disval rslt]
"0 (BC_4, Cbar ,input, X)," &
"1 (BC_4, C, input, X)," &
"2 (BC_4, ADDR(0), input, X)," &
"3 (BC_4, ADDR(1), input, X)," &
"4 (BC_4, ADDR(2), input, X)," &
"5 (BC_4, ADDR(3), input, X)," &
"6 (BC_4, ADDR(4), input, X)," &
"7 (BC_4, ADDR(5), input, X)," &
"8 (BC_4, ADDR(6), input, X)," &
--Boundary Scan for I/O pin
"9 (BC_7, Q(0), BIDIR, X, 47, 0, Z)," &
"10 (BC_4, D(0), input, X)," &
"11 (BC_4, * , internal, X)," &
"12 (BC_4, * , internal, X)," &
"13 (BC_7, Q(1) , BIDIR, X, 47, 0, Z)," &
"14 (BC_4, D(1), input, X)," &
"15 (BC_4, * , internal, X)," &
"16 (BC_4, * , internal, X)," &
"17 (BC_7, Q(2) , BIDIR, X, 47, 0, Z)," &
"18 (BC_4, D(2), input, X)," &
"19 (BC_4, * , internal, X)," &
"20 (BC_4, * , internal, X)," &
"21 (BC_7, Q(3) , BIDIR, X, 47, 0, Z)," &
"22 (BC_4, D(3), input, X)," &
"23 (BC_4, * , internal, X)," &
"24 (BC_4, * , internal, X)," &
"25 (BC_7, Q(4) , BIDIR, X, 47, 0, Z)," &
"26 (BC_4, D(4), input, X)," &
"27 (BC_4, ZQ, input, X)," &
"28 (BC_4, * , internal, X)," &
"29 (BC_4, * , internal, X)," &
"30 (BC_7, Q(5) , BIDIR, X, 47, 0, Z)," &
"31 (BC_4, D(5), input, X)," &
"32 (BC_4, * , internal, X)," &
"33 (BC_4, * , internal, X)," &
"34 (BC_7, Q(6) , BIDIR, X, 47, 0, Z)," &
"35 (BC_4, D(6), input, X)," &
"36 (BC_4, * , internal, X)," &
"37 (BC_4, * , internal, X)," &
"38 (BC_7, Q(7) , BIDIR, X, 47, 0, Z)," &
"39 (BC_4, D(7), input, X)," &
"40 (BC_4, * , internal, X)," &
"41 (BC_4, * , internal, X)," &
"42 (BC_7, Q(8) , BIDIR, X, 47, 0, Z)," &
"43 (BC_4, D(8), input, X)," &
"44 (BC_4, * , internal, X)," &
"45 (BC_4, * , internal, X)," &
"46 (BC_4, * , internal, X)," &
"47 (BC_2, * ,controlr, 0)," &
"48 (BC_4, ADDR(17), input, X)," &
--Boundary Scan for I/O pin
"49 (BC_4, ADDR(7), input, X)," &
"50 (BC_4, ADDR(8), input, X)," &
"51 (BC_4, * , internal, X)," &
"52 (BC_4, nR, input, X)," &
"53 (BC_4, * , internal, X)," &
"54 (BC_4, nBW1, input, X)," &
"55 (BC_2, K, input, X)," &
"56 (BC_2, Kbar, input, X)," &
"57 (BC_4, * , internal, X)," &
"58 (BC_4, nBW2, input, X)," &
"59 (BC_4, nW, input, X)," &
"60 (BC_4, ADDR(9), input, X)," &
"61 (BC_4, ADDR(10), input, X)," &
"62 (BC_4, * ,internal, X)," &
"63 (BC_4, * , internal, X)," &
"64 (BC_4, * , internal, X)," &
"65 (BC_7, Q(9) , BIDIR, X, 47, 0, Z)," &
"66 (BC_4, D(9), input, X)," &
"67 (BC_4, * , internal, X)," &
"68 (BC_4, * , internal, X)," &
"69 (BC_7, Q(10) , BIDIR, X, 47, 0, Z)," &
"70 (BC_4, D(10), input, X)," &
"71 (BC_4, * , internal, X)," &
"72 (BC_4, * , internal, X)," &
"73 (BC_7, Q(11) , BIDIR, X, 47, 0, Z)," &
"74 (BC_4, D(11), input, X)," &
"75 (BC_4, * , internal, X)," &
"76 (BC_4, * , internal, X)," &
"77 (BC_7, Q(12) , BIDIR, X, 47, 0, Z)," &
"78 (BC_4, D(12), input, X)," &
"79 (BC_4, * , internal, X)," &
"80 (BC_4, * , internal, X)," &
"81 (BC_7, Q(13) , BIDIR, X, 47, 0, Z)," &
"82 (BC_4, D(13), input, X)," &
"83 (BC_4, * , internal, X)," &
"84 (BC_4, * , internal, X)," &
"85 (BC_7, Q(14) , BIDIR, X, 47, 0, Z)," &
"86 (BC_4, D(14), input, X)," &
"87 (BC_4, * , internal, X)," &
"88 (BC_4, * , internal, X)," &
"89 (BC_7, Q(15) , BIDIR, X, 47, 0, Z)," &
"90 (BC_4, D(15), input, X)," &
"91 (BC_4, * , internal, X)," &
"92 (BC_4, * , internal, X)," &
"93 (BC_7, Q(16) , BIDIR, X, 47, 0, Z)," &
"94 (BC_4, D(16), input, X)," &
"95 (BC_4, * , internal, X)," &
"96 (BC_4, * , internal, X)," &
"97 (BC_7, Q(17) , BIDIR, X, 47, 0, Z)," &
"98 (BC_4, D(17), input, X)," &
"99 (BC_4, * , internal, X)," &
"100 (BC_4, * , internal, X)," &
"101 (BC_4, ADDR(11), input, X)," &
"102 (BC_4, ADDR(12), input, X)," &
"103 (BC_4, ADDR(13), input, X)," &
"104 (BC_4, ADDR(14), input, X)," &
"105 (BC_4, ADDR(15), input, X)," &
"106 (BC_4, ADDR(16), input, X)";
end GS8180VD18;