-------------------------------------------------------------------------------
-- SA-1110.bsdl
-- The BSDL Description for SA-1110 IEEE 1149.1 Circuits
-------------------------------------------------------------------------------
-- Revision History
-- Rev Date Description
-- 00 07-OCT-1999 Taken the bsdl code from SA1100 and
-- revised for SA1110
-------------------------------------------------------------------------------
entity SA1110 is -- (ref B.8)
generic (PHYSICAL_PIN_MAP: string:= "MBGA_256"); -- (ref B.8.2)
port( -- (ref B.8.3)
RXDC :inout bit;
TXDC :inout bit;
D :inout bit_vector (31 downto 0);
SDCLK :out bit_vector (2 downto 0);
SDCKE :out bit_vector (1 downto 0);
SMROMEN :in bit;
GP :inout bit_vector (27 downto 0);
LBIAS :inout bit;
LPCLK :inout bit;
LDD :inout bit_vector (7 downto 0);
LLCLK :inout bit;
LFCLK :inout bit;
POE :out bit;
PWE :out bit;
PIOR :out bit;
PIOW :out bit;
PSKTSEL :out bit;
IOIS16 :in bit;
PWAIT :in bit;
PREG :out bit;
PCE2 :out bit;
PCE1 :out bit;
WE :out bit;
OE :out bit;
nSDRAS :out bit;
nSDCAS :out bit;
RAS :out bit_vector (3 downto 0);
CAS :out bit_vector (3 downto 0);
RDY :in bit;
RDnWR :out bit;
CS :out bit_vector (5 downto 0);
A :out bit_vector (25 downto 0);
UDCP :inout bit;
UDCN :inout bit;
RXD1 :inout bit;
TXD1 :inout bit;
RXD2 :inout bit;
TXD2 :inout bit;
RXD3 :inout bit;
TXD3 :inout bit;
TXTAL :linkage bit;
TEXTAL :linkage bit;
PEXTAL :linkage bit;
PXTAL :linkage bit;
RESET :in bit;
RESETO :out bit;
ROMSEL :in bit;
TCKBYP :linkage bit;
TESTCLK :linkage bit;
TMS :in bit;
TCK :in bit;
TDI :in bit;
TDO :out bit;
TRST :in bit;
BATTF :in bit;
VDDFA :in bit; -- changed from linkage bit (rjf)
PWREN :linkage bit;
SFRMC :inout bit; -- changed from linkage bit (rjf)
SCLKC :inout bit; -- changed from linkage bit (rjf)
VDDP :linkage bit;
VDDX :linkage bit_vector (21 downto 0);
VSSX :linkage bit_vector (20 downto 0);
VDD :linkage bit_vector (7 downto 0);
VSS :linkage bit_vector (8 downto 0)
) ;
use STD_1149_1_1994.all ; -- (ref B.8.4) -- removed comment (rjf)
-- changed to 1990 for Teradyne Victory compiler -- "COMPILERSENSITIVE"
-- use STD_1149_1_1990.all ; -- "COMPILERSENSITIVE" -- inserted comment (rjf)
attribute COMPONENT_CONFORMANCE of SA1110: entity is "STD_1149_1_1993"; -- (ref B.8.6)
attribute PIN_MAP of SA1110 : entity is PHYSICAL_PIN_MAP ; -- (ref B.8.7)
constant MBGA_256 : PIN_MAP_STRING :=
"BATTF: A4, " &
"PWREN: A3, " &
"SCLKC: A2, " &
"D: ( M1, L2, K3, J3, H4, G3, F3, E3, M2, L3, " &
" K2, J2, G1, G4, E1, D1, L4, K4, J1, J6, " &
" H6, F1, E2, D2, L1, K1, J4, H1, G2, F2, " &
" F4, E4), " &
"SDCLK: ( M3, N3, P1), " &
"SDCKE: ( N2, N1), " &
"SMROMEN: M4, " &
"GP: ( R1, T1, R2, P4, T2, R3, T3, R4, T4, P5, " &
" R5, T5, N6, P6, R6, R7, T6, P7, T7, P8, " &
" N8, R8, P9, T9, N10, R10, P10, T10), " &
"LBIAS: R11, " &
"LPCLK: P11, " &
"LDD: ( P13, T13, R13, T12, P12, R12, T11, N12), " &
"LLCLK: R14, " &
"LFCLK: T14, " &
"POE: R15, " &
"PWE: T15, " &
"PIOR: T16, " &
"PIOW: R16, " &
"PSKTSEL: P16, " &
"IOIS16: N13, " &
"PWAIT: N16, " &
"PREG: N14, " &
"PCE2: N15, " &
"PCE1: M16, " &
"WE: M13, " &
"OE: M15, " &
"nSDRAS: M14, " &
"nSDCAS: L16, " &
"RAS: ( L15, L14, L13, K16), " &
"CAS: ( K13, K15, J15, J14), " &
"RDnWR: J13, " &
"RDY: H13, " &
"CS: ( H16, H15, H14, G16, G15, G14), " &
"A: ( F16, G13, F13, F15, E16, F14, E15, D16, E14, D15, " &
" C16, E13, D13, B16, C14, B14, B15, A16, A15, A14, " &
" B13, C13, A13, B12, C12, D12), " &
"UDCN: A12, " &
"UDCP: C11, " &
"RXD1: B11, " &
"TXD1: A11, " &
"RXD2: B10, " &
"TXD2: D10, " &
"RXD3: C10, " &
"TXD3: A10, " &
"TXTAL: B9, " &
"TEXTAL: C9, " &
"PEXTAL: A8, " &
"PXTAL: B8, " &
"RESET: B7, " &
"RESETO: C7, " &
"ROMSEL: D6, " &
"RXDC: B1, " &
"TXDC: C2, " &
"TCKBYP: A6, " &
"TESTCLK: B6, " &
"TMS: C6, " &
"TCK: C5, " &
"TDI: A5, " &
"TDO: B5, " &
"TRST: B4, " &
"VDDFA: C4, " &
"SFRMC: B3, " &
"VDDP: C8, " &
"VDDX: ( E12, F12, G5, G12, H5, H12, D5, D9, D11, E6, " &
" E7, J5, J12, K5, K12, L5, L12, E8, E9, E10, " &
" D7, E11), " &
"VSSX: ( A1, B2, C3, D4, E5, F6, F7, F8, F9, F10, " &
" F11, G6, G7, G8, G9, G10, G11, H7, H8, H9, " &
" H10), " &
"VDD: ( C1, H3, P3, T8, P15, J16, C15, A7), " &
"VSS: ( D3, H2, P2, R9, P14, K14, D14, A9, D8) ";
attribute TAP_SCAN_CLOCK of TCK : signal is (16.60e6, LOW); -- (Ref B.8.9)
attribute TAP_SCAN_IN of TDI : signal is TRUE;
attribute TAP_SCAN_OUT of TDO : signal is TRUE;
attribute TAP_SCAN_MODE of TMS : signal is TRUE;
attribute TAP_SCAN_RESET of TRST : signal is TRUE;
attribute INSTRUCTION_LENGTH of SA1110 : entity is 5 ; -- (Ref B.8.11)
attribute INSTRUCTION_OPCODE of SA1110 : entity is
"EXTEST (00000)," &
"SAMPLE (00001)," &
"CLAMP (00100)," &
"HIGHZ (00101)," &
"IDCODE (00110)," &
"BYPASS (11111)" ;
attribute INSTRUCTION_CAPTURE of SA1110 : entity is "00001" ;
-- attribute INSTRUCTION_PRIVATE of SA1110 : entity is "Private"; -- "COMPILERSENSITIVE" Comment out
-- if unsupported by the compiler
-- ID Register Description
attribute IDCODE_REGISTER of SA1110: entity is
"0100" & -- Version
"1001001001100001" & -- Part Number
"00000001001" & -- Manufacturer
"1"; -- Mandatory LSB
attribute REGISTER_ACCESS of SA1110 : entity is -- (ref B.8.13)
"BOUNDARY (EXTEST, SAMPLE)," & -- Redundant. Added for completeness
"BYPASS (BYPASS, HIGHZ, CLAMP)"; -- ditto
-- "DIE_ID[32] (DIE_ID)";
attribute BOUNDARY_LENGTH of SA1110 : entity is 292 ; -- (ref B.8.14)
attribute BOUNDARY_REGISTER of SA1110 : entity is
------------------------------------------------------------------------------
-- scan cell cntr disable disable
-- cell type port function safe cell value state
------------------------------------------------------------------------------
"291 (BC_4, BATTF, INPUT, x), " &
"290 (BC_4, VDDFA, INPUT, x), " &
"289 (BC_4, *, internal,x), " & -- PWREN pad
"288 (BC_2, *, control, x), " &
"287 (BC_1, SFRMC, OUTPUT3, x, 288, 0, Z ), " &
"286 (BC_4, SFRMC, INPUT, x), " &
"285 (BC_2, *, control, x), " &
"284 (BC_1, SCLKC, OUTPUT3, x, 285, 0, Z ), " &
"283 (BC_4, SCLKC, INPUT, x), " &
"282 (BC_2, *, control, x), " &
"281 (BC_1, RXDC, OUTPUT3, x, 282, 0, Z ), " &
"280 (BC_4, RXDC, INPUT, x), " &
"279 (BC_2, *, control, x), " &
"278 (BC_1, TXDC, OUTPUT3, x, 279, 0, Z ), " &
"277 (BC_4, TXDC, INPUT, x), " &
"276 (BC_1, D(0), OUTPUT3, x, 212, 1, Z ), " &
"275 (BC_4, D(0), INPUT, x), " &
"274 (BC_1, D(8), OUTPUT3, x, 212, 1, Z ), " &
"273 (BC_4, D(8), INPUT, x), " &
"272 (BC_1, D(16), OUTPUT3, x, 212, 1, Z ), " &
"271 (BC_4, D(16), INPUT, x), " &
"270 (BC_1, D(24), OUTPUT3, x, 212, 1, Z ), " &
"269 (BC_4, D(24), INPUT, x), " &
"268 (BC_1, D(1), OUTPUT3, x, 212, 1, Z ), " &
"267 (BC_4, D(1), INPUT, x), " &
"266 (BC_1, D(9), OUTPUT3, x, 212, 1, Z ), " &
"265 (BC_4, D(9), INPUT, x), " &
"264 (BC_1, D(17), OUTPUT3, x, 212, 1, Z ), " &
"263 (BC_4, D(17), INPUT, x), " &
"262 (BC_1, D(25), OUTPUT3, x, 212, 1, Z ), " &
"261 (BC_4, D(25), INPUT, x), " &
"260 (BC_1, D(2), OUTPUT3, x, 212, 1, Z ), " &
"259 (BC_4, D(2), INPUT, x), " &
"258 (BC_1, D(10), OUTPUT3, x, 212, 1, Z ), " &
"257 (BC_4, D(10), INPUT, x), " &
"256 (BC_1, D(18), OUTPUT3, x, 212, 1, Z ), " &
"255 (BC_4, D(18), INPUT, x), " &
"254 (BC_1, D(26), OUTPUT3, x, 212, 1, Z ), " &
"253 (BC_4, D(26), INPUT, x), " &
"252 (BC_1, D(3), OUTPUT3, x, 212, 1, Z ), " &
"251 (BC_4, D(3), INPUT, x), " &
"250 (BC_1, D(11), OUTPUT3, x, 212, 1, Z ), " &
"249 (BC_4, D(11), INPUT, x), " &
"248 (BC_1, D(19), OUTPUT3, x, 212, 1, Z ), " &
"247 (BC_4, D(19), INPUT, x), " &
"246 (BC_1, D(27), OUTPUT3, x, 212, 1, Z ), " &
"245 (BC_4, D(27), INPUT, x), " &
"244 (BC_1, D(4), OUTPUT3, x, 212, 1, Z ), " &
"243 (BC_4, D(4), INPUT, x), " &
"242 (BC_1, D(12), OUTPUT3, x, 212, 1, Z ), " &
"241 (BC_4, D(12), INPUT, x), " &
"240 (BC_1, D(20), OUTPUT3, x, 212, 1, Z ), " &
"239 (BC_4, D(20), INPUT, x), " &
"238 (BC_1, D(28), OUTPUT3, x, 212, 1, Z ), " &
"237 (BC_4, D(28), INPUT, x), " &
"236 (BC_1, D(5), OUTPUT3, x, 212, 1, Z ), " &
"235 (BC_4, D(5), INPUT, x), " &
"234 (BC_1, D(13), OUTPUT3, x, 212, 1, Z ), " &
"233 (BC_4, D(13), INPUT, x), " &
"232 (BC_1, D(21), OUTPUT3, x, 212, 1, Z ), " &
"231 (BC_4, D(21), INPUT, x), " &
"230 (BC_1, D(29), OUTPUT3, x, 212, 1, Z ), " &
"229 (BC_4, D(29), INPUT, x), " &
"228 (BC_1, D(6), OUTPUT3, x, 212, 1, Z ), " &
"227 (BC_4, D(6), INPUT, x), " &
"226 (BC_1, D(14), OUTPUT3, x, 212, 1, Z ), " &
"225 (BC_4, D(14), INPUT, x), " &
"224 (BC_1, D(22), OUTPUT3, x, 212, 1, Z ), " &
"223 (BC_4, D(22), INPUT, x), " &
"222 (BC_1, D(30), OUTPUT3, x, 212, 1, Z ), " &
"221 (BC_4, D(30), INPUT, x), " &
"220 (BC_1, D(7), OUTPUT3, x, 212, 1, Z ), " &
"219 (BC_4, D(7), INPUT, x), " &
"218 (BC_1, D(15), OUTPUT3, x, 212, 1, Z ), " &
"217 (BC_4, D(15), INPUT, x), " &
"216 (BC_1, D(23), OUTPUT3, x, 212, 1, Z ), " &
"215 (BC_4, D(23), INPUT, x), " &
"214 (BC_1, D(31), OUTPUT3, x, 212, 1, Z ), " &
"213 (BC_4, D(31), INPUT, x), " &
"212 (BC_2, *, control, x), " &
"211 (BC_1, SDCLK(2), OUTPUT2, x), " &
"210 (BC_1, SDCKE(1), OUTPUT2, x), " &
"209 (BC_2, *, control, x), " &
"208 (BC_1, SDCLK(1), OUTPUT3, x, 209, 1, Z ), " &
"207 (BC_1, SDCKE(0), OUTPUT2, x), " &
"206 (BC_1, SDCLK(0), OUTPUT2, x), " &
"205 (BC_4, SMROMEN, INPUT, x), " &
"204 (BC_2, *, control, x), " &
"203 (BC_1, GP(27), OUTPUT3, x, 204, 0, Z ), " &
"202 (BC_4, GP(27), INPUT, x), " &
"201 (BC_2, *, control, x), " &
"200 (BC_1, GP(26), OUTPUT3, x, 201, 0, Z ), " &
"199 (BC_4, GP(26), INPUT, x), " &
"198 (BC_2, *, control, x), " &
"197 (BC_1, GP(25), OUTPUT3, x, 198, 0, Z ), " &
"196 (BC_4, GP(25), INPUT, x), " &
"195 (BC_2, *, control, x), " &
"194 (BC_1, GP(24), OUTPUT3, x, 195, 0, Z ), " &
"193 (BC_4, GP(24), INPUT, x), " &
"192 (BC_2, *, control, x), " &
"191 (BC_1, GP(23), OUTPUT3, x, 192, 0, Z ), " &
"190 (BC_4, GP(23), INPUT, x), " &
"189 (BC_2, *, control, x), " &
"188 (BC_1, GP(22), OUTPUT3, x, 189, 0, Z ), " &
"187 (BC_4, GP(22), INPUT, x), " &
"186 (BC_2, *, control, x), " &
"185 (BC_1, GP(21), OUTPUT3, x, 186, 0, Z ), " &
"184 (BC_4, GP(21), INPUT, x), " &
"183 (BC_2, *, control, x), " &
"182 (BC_1, GP(20), OUTPUT3, x, 183, 0, Z ), " &
"181 (BC_4, GP(20), INPUT, x), " &
"180 (BC_2, *, control, x), " &
"179 (BC_1, GP(19), OUTPUT3, x, 180, 0, Z ), " &
"178 (BC_4, GP(19), INPUT, x), " &
"177 (BC_2, *, control, x), " &
"176 (BC_1, GP(18), OUTPUT3, x, 177, 0, Z ), " &
"175 (BC_4, GP(18), INPUT, x), " &
"174 (BC_2, *, control, x), " &
"173 (BC_1, GP(17), OUTPUT3, x, 174, 0, Z ), " &
"172 (BC_4, GP(17), INPUT, x), " &
"171 (BC_2, *, control, x), " &
"170 (BC_1, GP(16), OUTPUT3, x, 171, 0, Z ), " &
"169 (BC_4, GP(16), INPUT, x), " &
"168 (BC_2, *, control, x), " &
"167 (BC_1, GP(15), OUTPUT3, x, 168, 0, Z ), " &
"166 (BC_4, GP(15), INPUT, x), " &
"165 (BC_2, *, control, x), " &
"164 (BC_1, GP(14), OUTPUT3, x, 165, 0, Z ), " &
"163 (BC_4, GP(14), INPUT, x), " &
"162 (BC_2, *, control, x), " &
"161 (BC_1, GP(13), OUTPUT3, x, 162, 0, Z ), " &
"160 (BC_4, GP(13), INPUT, x), " &
"159 (BC_2, *, control, x), " &
"158 (BC_1, GP(12), OUTPUT3, x, 159, 0, Z ), " &
"157 (BC_4, GP(12), INPUT, x), " &
"156 (BC_2, *, control, x), " &
"155 (BC_1, GP(11), OUTPUT3, x, 156, 0, Z ), " &
"154 (BC_4, GP(11), INPUT, x), " &
"153 (BC_2, *, control, x), " &
"152 (BC_1, GP(10), OUTPUT3, x, 153, 0, Z ), " &
"151 (BC_4, GP(10), INPUT, x), " &
"150 (BC_2, *, control, x), " &
"149 (BC_1, GP(9), OUTPUT3, x, 150, 0, Z ), " &
"148 (BC_4, GP(9), INPUT, x), " &
"147 (BC_2, *, control, x), " &
"146 (BC_1, GP(8), OUTPUT3, x, 147, 0, Z ), " &
"145 (BC_4, GP(8), INPUT, x), " &
"144 (BC_2, *, control, x), " &
"143 (BC_1, GP(7), OUTPUT3, x, 144, 0, Z ), " &
"142 (BC_4, GP(7), INPUT, x), " &
"141 (BC_2, *, control, x), " &
"140 (BC_1, GP(6), OUTPUT3, x, 141, 0, Z ), " &
"139 (BC_4, GP(6), INPUT, x), " &
"138 (BC_2, *, control, x), " &
"137 (BC_1, GP(5), OUTPUT3, x, 138, 0, Z ), " &
"136 (BC_4, GP(5), INPUT, x), " &
"135 (BC_2, *, control, x), " &
"134 (BC_1, GP(4), OUTPUT3, x, 135, 0, Z ), " &
"133 (BC_4, GP(4), INPUT, x), " &
"132 (BC_2, *, control, x), " &
"131 (BC_1, GP(3), OUTPUT3, x, 132, 0, Z ), " &
"130 (BC_4, GP(3), INPUT, x), " &
"129 (BC_2, *, control, x), " &
"128 (BC_1, GP(2), OUTPUT3, x, 129, 0, Z ), " &
"127 (BC_4, GP(2), INPUT, x), " &
"126 (BC_2, *, control, x), " &
"125 (BC_1, GP(1), OUTPUT3, x, 126, 0, Z ), " &
"124 (BC_4, GP(1), INPUT, x), " &
"123 (BC_2, *, control, x), " &
"122 (BC_1, GP(0), OUTPUT3, x, 123, 0, Z ), " &
"121 (BC_4, GP(0), INPUT, x), " &
"120 (BC_2, *, control, x), " &
"119 (BC_1, LBIAS, OUTPUT3, x, 120, 0, Z ), " &
"118 (BC_4, LBIAS, INPUT, x), " &
"117 (BC_2, *, control, x), " &
"116 (BC_1, LPCLK, OUTPUT3, x, 117, 0, Z ), " &
"115 (BC_4, LPCLK, INPUT, x), " &
"114 (BC_2, *, control, x), " &
"113 (BC_1, LDD(0), OUTPUT3, x, 114, 0, Z ), " &
"112 (BC_4, LDD(0), INPUT, x), " &
"111 (BC_2, *, control, x), " &
"110 (BC_1, LDD(1), OUTPUT3, x, 111, 0, Z ), " &
"109 (BC_4, LDD(1), INPUT, x), " &
"108 (BC_2, *, control, x), " &
"107 (BC_1, LDD(2), OUTPUT3, x, 108, 0, Z ), " &
"106 (BC_4, LDD(2), INPUT, x), " &
"105 (BC_2, *, control, x), " &
"104 (BC_1, LDD(3), OUTPUT3, x, 105, 0, Z ), " &
"103 (BC_4, LDD(3), INPUT, x), " &
"102 (BC_2, *, control, x), " &
"101 (BC_1, LDD(4), OUTPUT3, x, 102, 0, Z ), " &
"100 (BC_4, LDD(4), INPUT, x), " &
"99 (BC_2, *, control, x), " &
"98 (BC_1, LDD(5), OUTPUT3, x, 99, 0, Z ), " &
"97 (BC_4, LDD(5), INPUT, x), " &
"96 (BC_2, *, control, x), " &
"95 (BC_1, LDD(6), OUTPUT3, x, 96, 0, Z ), " &
"94 (BC_4, LDD(6), INPUT, x), " &
"93 (BC_2, *, control, x), " &
"92 (BC_1, LDD(7), OUTPUT3, x, 93, 0, Z ), " &
"91 (BC_4, LDD(7), INPUT, x), " &
"90 (BC_2, *, control, x), " &
"89 (BC_1, LLCLK, OUTPUT3, x, 90, 0, Z ), " &
"88 (BC_4, LLCLK, INPUT, x), " &
"87 (BC_2, *, control, x), " &
"86 (BC_1, LFCLK, OUTPUT3, x, 87, 0, Z ), " &
"85 (BC_4, LFCLK, INPUT, x), " &
"84 (BC_1, POE, OUTPUT2, x), " &
"83 (BC_1, PWE, OUTPUT2, x), " &
"82 (BC_1, PIOR, OUTPUT2, x), " &
"81 (BC_1, PIOW, OUTPUT2, x), " &
"80 (BC_1, PSKTSEL, OUTPUT2, x), " &
"79 (BC_4, IOIS16, INPUT, x), " &
"78 (BC_4, PWAIT, INPUT, x), " &
"77 (BC_1, PREG, OUTPUT2, x), " &
"76 (BC_1, PCE2, OUTPUT2, x), " &
"75 (BC_1, PCE1, OUTPUT2, x), " &
"74 (BC_2, *, control, x), " &
"73 (BC_1, WE, OUTPUT3, x, 74, 1, Z ), " &
"72 (BC_1, OE, OUTPUT3, x, 74, 1, Z ), " &
"71 (BC_1, nSDRAS, OUTPUT3, x, 74, 1, Z ), " &
"70 (BC_1, nSDCAS, OUTPUT3, x, 74, 1, Z ), " &
"69 (BC_1, RAS(3), OUTPUT2, x), " &
"68 (BC_1, RAS(2), OUTPUT2, x), " &
"67 (BC_1, RAS(1), OUTPUT2, x), " &
"66 (BC_1, RAS(0), OUTPUT3, x, 74, 1, Z ), " &
"65 (BC_1, CAS(3), OUTPUT3, x, 74, 1, Z ), " &
"64 (BC_1, CAS(2), OUTPUT3, x, 74, 1, Z ), " &
"63 (BC_1, CAS(1), OUTPUT3, x, 74, 1, Z ), " &
"62 (BC_1, CAS(0), OUTPUT3, x, 74, 1, Z ), " &
"61 (BC_1, RDnWR, OUTPUT2, x), " &
"60 (BC_4, RDY, INPUT, x), " &
"59 (BC_1, CS(5), OUTPUT2, x), " &
"58 (BC_1, CS(4), OUTPUT2, x), " &
"57 (BC_1, CS(3), OUTPUT2, x), " &
"56 (BC_1, CS(2), OUTPUT2, x), " &
"55 (BC_1, CS(1), OUTPUT2, x), " &
"54 (BC_1, CS(0), OUTPUT2, x), " &
"53 (BC_1, A(25), OUTPUT3, x, 74, 1, Z ), " &
"52 (BC_1, A(24), OUTPUT3, x, 74, 1, Z ), " &
"51 (BC_1, A(23), OUTPUT3, x, 74, 1, Z ), " &
"50 (BC_1, A(22), OUTPUT3, x, 74, 1, Z ), " &
"49 (BC_1, A(21), OUTPUT3, x, 74, 1, Z ), " &
"48 (BC_1, A(20), OUTPUT3, x, 74, 1, Z ), " &
"47 (BC_1, A(19), OUTPUT3, x, 74, 1, Z ), " &
"46 (BC_1, A(18), OUTPUT3, x, 74, 1, Z ), " &
"45 (BC_1, A(17), OUTPUT3, x, 74, 1, Z ), " &
"44 (BC_1, A(16), OUTPUT3, x, 74, 1, Z ), " &
"43 (BC_1, A(15), OUTPUT3, x, 74, 1, Z ), " &
"42 (BC_1, A(14), OUTPUT3, x, 74, 1, Z ), " &
"41 (BC_1, A(13), OUTPUT3, x, 74, 1, Z ), " &
"40 (BC_1, A(12), OUTPUT3, x, 74, 1, Z ), " &
"39 (BC_1, A(11), OUTPUT3, x, 74, 1, Z ), " &
"38 (BC_1, A(10), OUTPUT3, x, 74, 1, Z ), " &
"37 (BC_1, A(9), OUTPUT3, x, 74, 1, Z ), " &
"36 (BC_1, A(8), OUTPUT3, x, 74, 1, Z ), " &
"35 (BC_1, A(7), OUTPUT3, x, 74, 1, Z ), " &
"34 (BC_1, A(6), OUTPUT3, x, 74, 1, Z ), " &
"33 (BC_1, A(5), OUTPUT3, x, 74, 1, Z ), " &
"32 (BC_1, A(4), OUTPUT3, x, 74, 1, Z ), " &
"31 (BC_1, A(3), OUTPUT3, x, 74, 1, Z ), " &
"30 (BC_1, A(2), OUTPUT3, x, 74, 1, Z ), " &
"29 (BC_1, A(1), OUTPUT3, x, 74, 1, Z ), " &
"28 (BC_1, A(0), OUTPUT3, x, 74, 1, Z ), " &
"27 (BC_2, *, control, x), " &
"26 (BC_1, UDCN, OUTPUT3, x, 27, 1, Z ), " &
"25 (BC_4, UDCN, INPUT, x), " &
"24 (BC_4, *, INTERNAL,x), " &
"23 (BC_2, *, control, x), " &
"22 (BC_1, UDCP, OUTPUT3, x, 23, 1, Z ), " &
"21 (BC_4, UDCP, INPUT, x), " &
"20 (BC_2, *, control, x), " &
"19 (BC_1, RXD1, OUTPUT3, x, 20, 0, Z ), " &
"18 (BC_4, RXD1, INPUT, x), " &
"17 (BC_2, *, control, x), " &
"16 (BC_1, TXD1, OUTPUT3, x, 17, 0, Z ), " &
"15 (BC_4, TXD1, INPUT, x), " &
"14 (BC_2, *, control, x), " &
"13 (BC_1, RXD2, OUTPUT3, x, 14, 0, Z ), " &
"12 (BC_4, RXD2, INPUT, x), " &
"11 (BC_2, *, control, x), " &
"10 (BC_1, TXD2, OUTPUT3, x, 11, 0, Z ), " &
"9 (BC_4, TXD2, INPUT, x), " &
"8 (BC_2, *, control, x), " &
"7 (BC_1, RXD3, OUTPUT3, x, 8, 0, Z ), " &
"6 (BC_4, RXD3, INPUT, x), " &
"5 (BC_2, *, control, x), " &
"4 (BC_1, TXD3, OUTPUT3, x, 5, 0, Z ), " &
"3 (BC_4, TXD3, INPUT, x), " &
"2 (BC_4, RESET, INPUT, x), " &
"1 (BC_1, RESETO, OUTPUT2, x), " &
"0 (BC_4, ROMSEL, INPUT, x) ";
------------------------------------------------------------------------------
-- scan cell port function safe cntrl disable disable
-- cell type cell value state
------------------------------------------------------------------------------
attribute DESIGN_WARNING of SA1110: entity is -- (ref B.8.18)
" 1.IEEE 1149.1 circuits on SA1110 are designed " &
" primarily to support testing in off-line module " &
" manufacturing environment. The SAMPLE/PRELOAD " &
" instruction support is designed primarily for " &
" supporting interconnection verification test and not " &
" for at-speed samples of pin data. " &
" 2.Ensure to drive BATTF and VDDF to logic level 0 else the chip " &
" will sleep! ";
end SA1110;
