------------------------------------------------------------------------
-- File Type : BSDL Description for Top-Level Entity TMS320F2812 --
------------------------------------------------------------------------
------------------------------------------------------------------------
-- TI TMS320F2812 32-bit 179-pin Fixed-Point DSP with Boundary Scan --
------------------------------------------------------------------------
-- Supported Devices: TMS320F2812 179-pin Rev C and higher --
------------------------------------------------------------------------
-- Created by : Texas Instruments Incorporated --
-- Documentation : TMS320F28x Users Guide --
-- BSDL Revision : 1.2 --
-- Date : 25 Jan 2005
-- BSDL status : TMS --
-- --
-- History: --
--
-- Rev. 1.2, Jan 25, 2005: Made the following changes
-- 1) Renamed ZACS6AND7n to XZCS6AND7n
-- --
-- Rev. 1.1, Jan 14, 2005: Made the following changes (DMA) --
-- --
-- 1) Changed the following pin names throughout the document to --
-- be consistent with the device datasheet, SPRS174. --
-- --
-- OLD NAME NEW NAME --
-- -------- -------- --
-- VDDAFL VDDAIO --
-- VDDSFL VDDIO --
-- VSSA3 VSSAIO --
-- ADCIN0 ADCINA --
-- ADCIN1 ADCINB --
-- C1TRIPN C1TRIPn --
-- C2TRIPN C2TRIPn --
-- C3TRIPN C3TRIPn --
-- C4TRIPN C4TRIPn --
-- C5TRIPN C5TRIPn --
-- C6TRIPN C6TRIPn --
-- T1CTRIP_PDPINTAn T1CTRIPn_PDPINTAn --
-- T2CTRIP_EVASOCn T2CTRIPn_EVASOCn --
-- T3CTRIP_PDPINTBn T3CTRIPn_PDPINTBn --
-- T4CTRIP_EVBSOCn T4CTRIPn_EVBSOCn --
-- XINT1_XBION XINT1_XBIOn --
-- x1 x1_xclkin --
-- xa XA --
-- xclkout XCLKOUT --
-- xd XD --
-- xholdan XHOLDAn --
-- xholdn XHOLDn --
-- xmpnmc XMPnMC --
-- xrdn XRDn --
-- xready XREADY --
-- xrnw XRnW --
-- xrsn XRSn --
-- xwen XWEn --
-- xzcs0and1n XZCS0AND1n --
-- xzcs2n XZCS2n --
-- xzcs6and7n XZCS6AND7n --
-- --
-- 2) Adjusted order of PHYSICAL_PIN_STRING entries to match --
-- the order of the PHYSICAL_PIN_MAP entries. --
-- --
-- 3) Corrected the "Device Pins not testable ..." comment in --
-- this header. --
-- from: X2/XCLKIN, X1 --
-- to: X1/XCLKIN, X2 --
-- --
-- 4) Added missing balls C10 and K1 to Vss PIN_MAP_STRING. --
-- --
-- Rev. 1.0, Oct 15, 2003: Original --
-- --
------------------------------------------------------------------------
--
-- Initialization Requirements for Boundary Scan Test
-- --------------------------------------------------
--
-- The F281x DSPs use the JTAG port for boundary scan tests, emulation
-- capability and factory test purposes. To use boundary scan test,
-- the following pin configuration must be used:
--
-- TESTSEL = 0
-- EMU1 = 0
-- EMU0 = 1
-- TRSTN = 0 -> 1 ( transitioning to a 1 will latch the device into
-- boundary scan mode )
--
-- TRSTN is a reset to the JTAG state machine (active low), hence it has
-- to be pulled high before any JTAG scans are made.
--
-- F281x Devices have two taps - one for the CPU and one for boundary scan.
-- The boundary scan IR size is 3 bits.
--
-- Device Pins not testable by Boundary Scan
-- ------------------------------------------
-- The following pins cannot be tested through boundary scan:
-- EMU0, EMU1, X1/XCLKIN, X2, TESTSEL, TEST1, TEST2, and all the analog pins
--
--
-- IMPORTANT NOTICE
-- Texas Instruments Incorporated (TI) reserves the right to make
-- changes to its products or to discontinue any semiconductor
-- product or service without notice, and advises its customers to
-- obtain the latest version of the relevant information to
-- verify, before placing orders, that the information being
-- relied on is current.
-- TI warrants performance of its semiconductor products and
-- related software to the specifications applicable at the time
-- of sale in accordance with TI's standard warranty. Testing and
-- other quality control techniques are utilized to the extent TI
-- deems necessary to support this warranty. Specific testing of
-- all parameters of each device is not necessarily performed,
-- except those mandated by government requirements.
--
-- Certain applications using semiconductor devices may involve
-- potential risks of death, personal injury, or severe property
-- or environmental damage ("Critical Applications").
--
-- TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
-- AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN
-- LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
-- CRITICAL APPLICATIONS.
--
-- Inclusion of TI products in such applications is understood
-- to be fully at the risk of the customer. Use of TI products
-- in such applications requires the written approval of an
-- appropriate TI officer. Questions concerning potential risk
-- applications should be directed to TI through a local SC sales
-- office.
-- In order to minimize risks associated with the customer's
-- applications, adequate design and operating safeguards should
-- be provided by the
-- customer to minimize inherent or procedural hazards.
--
-- TI assumes no liability for applications assistance, customer
-- product design, software performance, or infringement of
-- patents or services described herein. Nor does TI warrant or
-- represent that any license, either express or implied, is
-- granted under any patent right, copyright, mask work right, or
-- other intellectual property right of TI covering or relating
-- to any combination, machine, or process in which such
-- semiconductor products or services might be or are used.
-- Copyright (c) 2000, Texas Instruments Incorporated
------------------------------------------------------------------------
entity TMS320F2812 is
generic(PHYSICAL_PIN_MAP : string := "GHH");
port (
VDDAIO : linkage bit;
VDDA1 : linkage bit;
VSSA1 : linkage bit;
VDD : linkage bit_vector(9 downto 0);
VSS : linkage bit_vector(15 downto 0);
VDDIO : linkage bit_vector(5 downto 0);
VDD3VFL : linkage bit;
VDD1 : linkage bit;
VSS1 : linkage bit;
VDDA2 : linkage bit;
VSSA2 : linkage bit;
VSSAIO : linkage bit;
ADCINA : linkage bit_vector(7 downto 0);
ADCINB : linkage bit_vector(7 downto 0);
ADCLO : linkage bit;
ADCREFM : linkage bit;
ADCREFP : linkage bit;
ADCRESEXT : linkage bit;
AVSSREFBG : linkage bit;
AVDDREFBG : linkage bit;
ADCBGREFIN : linkage bit;
C3TRIPn : inout bit;
C2TRIPn : inout bit;
C1TRIPn : inout bit;
TCLKINA : inout bit;
TDIRA : inout bit;
CAP3_QEPI1 : inout bit;
CAP2_QEP2 : inout bit;
CAP1_QEP1 : inout bit;
T2PWM_T2CMP : inout bit;
T1PWM_T1CMP : inout bit;
PWM6 : inout bit;
PWM5 : inout bit;
PWM4 : inout bit;
PWM3 : inout bit;
PWM2 : inout bit;
PWM1 : inout bit;
C6TRIPn : inout bit;
C5TRIPn : inout bit;
C4TRIPn : inout bit;
TCLKINB : inout bit;
TDIRB : inout bit;
CAP6_QEPI2 : inout bit;
CAP5_QEP4 : inout bit;
CAP4_QEP3 : inout bit;
T4PWM_T4CMP : inout bit;
T3PWM_T3CMP : inout bit;
PWM12 : inout bit;
PWM11 : inout bit;
PWM10 : inout bit;
PWM9 : inout bit;
PWM8 : inout bit;
PWM7 : inout bit;
T1CTRIPn_PDPINTAn : inout bit;
T2CTRIPn_EVASOCn : inout bit;
T3CTRIPn_PDPINTBn : inout bit;
T4CTRIPn_EVBSOCn : inout bit;
XINT1_XBIOn : inout bit;
XINT2_ADCSOC : inout bit;
XNMI_XINT13 : inout bit;
XF_XPLLDISn : inout bit;
MDRA : inout bit;
MDXA : inout bit;
MFSRA : inout bit;
MFSXA : inout bit;
MCLKRA : inout bit;
MCLKXA : inout bit;
CANRXA : inout bit;
CANTXA : inout bit;
SCIRXDA : inout bit;
SCITXDA : inout bit;
SPISTEA : inout bit;
SPICLKA : inout bit;
SPISOMIA : inout bit;
SPISIMOA : inout bit;
SCITXDB : inout bit;
SCIRXDB : inout bit;
TESTSEL : in bit;
X1_XCLKIN : linkage bit;
X2 : linkage bit;
XA : out bit_vector(18 downto 0);
XCLKOUT : out bit;
XD : inout bit_vector(15 downto 0);
XHOLDAn : out bit;
XHOLDn : in bit;
XMPnMC : in bit;
XRDn : out bit;
XREADY : in bit;
XRnW : out bit;
XRSn : inout bit;
XWEn : out bit;
XZCS0AND1n : out bit;
XZCS2n : out bit;
XZCS6AND7n : out bit;
TDI : in bit;
TMS : in bit;
TCK : in bit;
TDO : out bit;
TRSTn : in bit;
EMU0 : in bit;
EMU1 : in bit;
TEST1 : linkage bit;
TEST2 : linkage bit
);
use STD_1149_1_1994.all; -- Get IEEE 1149.1-1994 attributes and definitions
attribute COMPONENT_CONFORMANCE of TMS320F2812 : entity is "STD_1149_1_1993";
attribute PIN_MAP of TMS320F2812 : entity is PHYSICAL_PIN_MAP;
constant GHH : PIN_MAP_STRING :=
"VDDAIO:B2,"&
"VDDA1:F4,"&
"VSSA1:F3,"&
"VDD: (H1,L1,P5,P9,P12,K12,G12,C14,B10,C8)," &
"VSS: (G4,L2,P4,K6,P8,M10,L11,K13,J14,G13,E14,B14,D10,B8,C10,K1)," &
"VDDIO: (J4,L7,L10,N14,G11,E9)," &
"VDD3VFL:N8," &
"VDD1:A6," &
"VSS1:C6," &
"VDDA2:A5," &
"VSSA2:C5," &
"VSSAIO:A2," &
"ADCINA: (B5,D5,E5,A4,B4,C4,D4,A3)," &
"ADCINB: (F5,D1,D2,D3,C1,B1,C3,C2)," &
"ADCLO: B3," &
"ADCREFM: E4," &
"ADCREFP: E2," &
"ADCRESEXT: F2," &
"AVSSREFBG: E3," &
"AVDDREFBG:E1," &
"ADCBGREFIN: E6," &
"C3TRIPn: F10," &
"C2TRIPn: E11," &
"C1TRIPn: E13," &
"TCLKINA: F13," &
"TDIRA: F14," &
"CAP3_QEPI1: H12," &
"CAP2_QEP2: H11," &
"CAP1_QEP1: H10," &
"T2PWM_T2CMP: J13," &
"T1PWM_T1CMP: J11," &
"PWM6: K14," &
"PWM5: K11," &
"PWM4: L13," &
"PWM3: L12," &
"PWM2: M14," &
"PWM1: M12," &
"C6TRIPn: K7," &
"C5TRIPn: L6," &
"C4TRIPn: N6," &
"TCLKINB: K8," &
"TDIRB: L8," &
"CAP6_QEPI2: P6," &
"CAP5_QEP4: M6," &
"CAP4_QEP3: M5," &
"T4PWM_T4CMP: N5," &
"T3PWM_T3CMP: K5," &
"PWM12: M4," &
"PWM11: L4," &
"PWM10: P3," &
"PWM9: N3," &
"PWM8: P2," &
"PWM7: N2," &
"T1CTRIPn_PDPINTAn: H14," &
"T2CTRIPn_EVASOCn: G10," &
"T3CTRIPn_PDPINTBn: P10," &
"T4CTRIPn_EVBSOCn: P11," &
"XINT1_XBIOn: D9," &
"XINT2_ADCSOC: D8," &
"XNMI_XINT13: E8," &
"XF_XPLLDISn: A11," &
"MDRA: G2," &
"MDXA: G1," &
"MFSRA: J2," &
"MFSXA: H4," &
"MCLKRA: H2," &
"MCLKXA: J1," &
"CANRXA: N13," &
"CANTXA: N12," &
"SCIRXDA: A7," &
"SCITXDA: C7," &
"SPISTEA: K4," &
"SPICLKA: K2," &
"SPISOMIA: N1," &
"SPISIMOA: M1," &
"SCITXDB: P14," &
"SCIRXDB: M13," &
"TESTSEL: A13," &
"X1_XCLKIN: K9," &
"X2: M9," &
"XA: (D7,B7,A8,B9,A10,E10,C11,A14,C12,D14,E12,F12,G14,H13,J12,M11,N10,M2,G5)," &
"XCLKOUT: F11," &
"XD: (A9,B11,J10,L14,N9,L9,M8,P7,L5,L3,J5,K3,J3,H5,H3,G3)," &
"XHOLDAn: K10," &
"XHOLDn: E7," &
"XMPnMC: F1," &
"XRDn: M3," &
"XREADY: B6," &
"XRnW: N4," &
"XRSn: D6," &
"XWEn: N11," &
"XZCS0AND1n: P1," &
"XZCS2n: P13," &
"XZCS6AND7n: B13," &
"TDI: C13," &
"TMS: D13," &
"TCK: A12," &
"TDO: D12," &
"TRSTn: B12," &
"EMU0: D11," &
"EMU1: C9," &
"TEST1: M7 ," &
"TEST2: N7";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH);
attribute TAP_SCAN_RESET of TRSTN : signal is true;
attribute COMPLIANCE_PATTERNS of TMS320F2812 : entity is "(TESTSEL,EMU1,EMU0)(001)";
attribute INSTRUCTION_LENGTH of TMS320F2812 : entity is 3;
attribute INSTRUCTION_OPCODE of TMS320F2812 : entity is
"extest (000)," &
"bypass (111)," &
"sample (001)," &
"idcode (100)";
attribute INSTRUCTION_CAPTURE of TMS320F2812 : entity is "001";
attribute IDCODE_REGISTER of TMS320F2812 : entity is
"0001" & -- Version Number
"1011010011110100" & -- Part Number
"00000010111" & -- Manufacturer ID
"1"; -- Required by IEEE Std. 1149.1-1990
attribute REGISTER_ACCESS of TMS320F2812 : entity is
"BOUNDARY (extest, sample), " &
"DEVICE_ID (idcode), " &
"BYPASS (bypass)";
attribute BOUNDARY_LENGTH of TMS320F2812 : entity is 237;
attribute BOUNDARY_REGISTER of TMS320F2812 : entity is
-- num cell port function safe [ccell disval rslt]
"0 ( bc_4, XMPnMC, input, X)," &
"1 ( bc_1, XA(0), output3, X, 2, 1, Z)," &
"2 ( bc_1, *, control, 1)," &
"3 ( bc_4, MDRA, input, X)," &
"4 ( bc_1, MDRA, output3, X, 5, 1, PULL1)," &
"5 ( bc_1, *, control, 1)," &
"6 ( bc_4, XD(0), input, X)," &
"7 ( bc_1, XD(0), output3, X, 8, 1, PULL1)," &
"8 ( bc_1, *, control, 1)," &
"9 ( bc_4, MDXA, input, X)," &
"10 ( bc_1, MDXA, output3, X, 11, 1, Z)," &
"11 ( bc_1, *, control, 1)," &
"12 ( bc_4, XD(1), input, X)," &
"13 ( bc_1, XD(1), output3, X, 8, 1, PULL1)," &
"14 ( bc_4, MCLKRA, input, X)," &
"15 ( bc_1, MCLKRA, output3, X, 16, 1, PULL1)," &
"16 ( bc_1, *, control, 1)," &
"17 ( bc_4, MFSXA, input, X)," &
"18 ( bc_1, MFSXA, output3, X, 19, 1, PULL1)," &
"19 ( bc_1, *, control, 1)," &
"20 ( bc_4, XD(2), input, X)," &
"21 ( bc_1, XD(2), output3, X, 8, 1, PULL1)," &
"22 ( bc_4, MCLKXA, input, X)," &
"23 ( bc_1, MCLKXA, output3, X, 24, 1, PULL1)," &
"24 ( bc_1, *, control, 1)," &
"25 ( bc_4, MFSRA, input, X)," &
"26 ( bc_1, MFSRA, output3, X, 27, 1, PULL1)," &
"27 ( bc_1, *, control, 1)," &
"28 ( bc_4, XD(3), input, X)," &
"29 ( bc_1, XD(3), output3, X, 8, 1, PULL1)," &
"30 ( bc_4, XD(4), input, X)," &
"31 ( bc_1, XD(4), output3, X, 8, 1, PULL1)," &
"32 ( bc_4, SPICLKA, input, X)," &
"33 ( bc_1, SPICLKA, output3, X, 34, 1, Z)," &
"34 ( bc_1, *, control, 1)," &
"35 ( bc_4, SPISTEA, input, X)," &
"36 ( bc_1, SPISTEA, output3, X, 37, 1, Z)," &
"37 ( bc_1, *, control, 1)," &
"38 ( bc_4, XD(5), input, X)," &
"39 ( bc_1, XD(5), output3, X, 8, 1, PULL1)," &
"40 ( bc_4, XD(6), input, X)," &
"41 ( bc_1, XD(6), output3, X, 8, 1, PULL1)," &
"42 ( bc_4, SPISIMOA, input, X)," &
"43 ( bc_1, SPISIMOA, output3, X, 44, 1, Z)," &
"44 ( bc_1, *, control, 1)," &
"45 ( bc_4, SPISOMIA, input, X)," &
"46 ( bc_1, SPISOMIA, output3, X, 47, 1, Z)," &
"47 ( bc_1, *, control, 1)," &
"48 ( bc_1, XRDn, output3, X, 49, 1, Z)," &
"49 ( bc_1, *, control, 1)," &
"50 ( bc_1, XA(1), output3, X, 2, 1, Z)," &
"51 ( bc_1, XZCS0AND1n, output3, X, 49, 1, Z)," &
"52 ( bc_4, PWM7, input, X)," &
"53 ( bc_1, PWM7, output3, X, 54, 1, PULL1)," &
"54 ( bc_1, *, control, 1)," &
"55 ( bc_4, PWM8, input, X)," &
"56 ( bc_1, PWM8, output3, X, 57, 1, PULL1)," &
"57 ( bc_1, *, control, 1)," &
"58 ( bc_4, PWM9, input, X)," &
"59 ( bc_1, PWM9, output3, X, 60, 1, PULL1)," &
"60 ( bc_1, *, control, 1)," &
"61 ( bc_4, PWM10, input, X)," &
"62 ( bc_1, PWM10, output3, X, 63, 1, PULL1)," &
"63 ( bc_1, *, control, 1)," &
"64 ( bc_4, PWM11, input, X)," &
"65 ( bc_1, PWM11, output3, X, 66, 1, PULL1)," &
"66 ( bc_1, *, control, 1)," &
"67 ( bc_4, PWM12, input, X)," &
"68 ( bc_1, PWM12, output3, X, 69, 1, PULL1)," &
"69 ( bc_1, *, control, 1)," &
"70 ( bc_1, XRnW, output3, X, 49, 1, Z)," &
"71 ( bc_4, T3PWM_T3CMP, input, X)," &
"72 ( bc_1, T3PWM_T3CMP, output3, X, 73, 1, PULL1)," &
"73 ( bc_1, *, control, 1)," &
"74 ( bc_4, XD(7), input, X)," &
"75 ( bc_1, XD(7), output3, X, 8, 1, PULL1)," &
"76 ( bc_4, T4PWM_T4CMP, input, X)," &
"77 ( bc_1, T4PWM_T4CMP, output3, X, 78, 1, PULL1)," &
"78 ( bc_1, *, control, 1)," &
"79 ( bc_4, CAP4_QEP3, input, X)," &
"80 ( bc_1, CAP4_QEP3, output3, X, 81, 1, PULL1)," &
"81 ( bc_1, *, control, 1)," &
"82 ( bc_4, CAP5_QEP4, input, X)," &
"83 ( bc_1, CAP5_QEP4, output3, X, 84, 1, PULL1 )," &
"84 ( bc_1, *, control, 1)," &
"85 ( bc_4, CAP6_QEPI2, input, X)," &
"86 ( bc_1, CAP6_QEPI2, output3, X, 87, 1, PULL1)," &
"87 ( bc_1, *, control, 1)," &
"88 ( bc_4, C4TRIPn, input, X)," &
"89 ( bc_1, C4TRIPn, output3, X, 90, 1, PULL1)," &
"90 ( bc_1, *, control, 1)," &
"91 ( bc_4, C5TRIPn, input, X)," &
"92 ( bc_1, C5TRIPn, output3, X, 93, 1, PULL1)," &
"93 ( bc_1, *, control, 1)," &
"94 ( bc_4, C6TRIPn, input, X)," &
"95 ( bc_1, C6TRIPn, output3, X, 96, 1, PULL1)," &
"96 ( bc_1, *, control, 1)," &
"97 ( bc_4, XD(8), input, X)," &
"98 ( bc_1, XD(8), output3, X, 8, 1, PULL1)," &
"99 ( bc_4, XD(9), input, X)," &
"100 ( bc_1, XD(9), output3, X, 8, 1, PULL1)," &
"101 ( bc_4, TDIRB, input, X)," &
"102 ( bc_1, TDIRB, output3, X, 103, 1, PULL1)," &
"103 ( bc_1, *, control, 1)," &
"104 ( bc_4, TCLKINB, input, X)," &
"105 ( bc_1, TCLKINB, output3, X, 106, 1, PULL1)," &
"106 ( bc_1, *, control, 1)," &
"107 ( bc_4, XD(10), input, X)," &
"108 ( bc_1, XD(10), output3, X, 8, 1, PULL1)," &
"109 ( bc_4, XD(11), input, X)," &
"110 ( bc_1, XD(11), output3, X, 8, 1, PULL1)," &
"111 ( bc_4, T3CTRIPn_PDPINTBn, input, X)," &
"112 ( bc_1, T3CTRIPn_PDPINTBn, output3, X, 113, 1, PULL1)," &
"113 ( bc_1, *, control, 1)," &
"114 ( bc_1, XA(2), output3, X, 2, 1, Z)," &
"115 ( bc_1, xholdan, output3, X, 116, 1, Z)," &
"116 ( bc_1, *, control, 1)," &
"117 ( bc_4, T4CTRIPn_EVBSOCn, input, X)," &
"118 ( bc_1, T4CTRIPn_EVBSOCn, output3, X, 119, 1, PULL1)," &
"119 ( bc_1, *, control, 1)," &
"120 ( bc_1, XWEn, output3, X, 49, 1, Z)," &
"121 ( bc_1, XA(3), output3, X, 2, 1, Z)," &
"122 ( bc_4, CANTXA, input, X)," &
"123 ( bc_1, CANTXA, output3, X, 124, 1, PULL1)," &
"124 ( bc_1, *, control, 1)," &
"125 ( bc_1, XZCS2n, output3, X, 49, 1, Z)," &
"126 ( bc_4, CANRXA, input, X)," &
"127 ( bc_1, CANRXA, output3, X, 128, 1, PULL1)," &
"128 ( bc_1, *, control, 1)," &
"129 ( bc_4, SCITXDB, input, X)," &
"130 ( bc_1, SCITXDB, output3, X, 131, 1, Z)," &
"131 ( bc_1, *, control, 1)," &
"132 ( bc_4, SCIRXDB, input, X)," &
"133 ( bc_1, SCIRXDB, output3, X, 134, 1, Z)," &
"134 ( bc_1, *, control, 1)," &
"135 ( bc_4, PWM1, input, X)," &
"136 ( bc_1, PWM1, output3, X, 137, 1, PULL1)," &
"137 ( bc_1, *, control, 1)," &
"138 ( bc_4, PWM2, input, X)," &
"139 ( bc_1, PWM2, output3, X, 140, 1, PULL1)," &
"140 ( bc_1, *, control, 1)," &
"141 ( bc_4, PWM3, input, X)," &
"142 ( bc_1, PWM3, output3, X, 143, 1, PULL1)," &
"143 ( bc_1, *, control, 1)," &
"144 ( bc_4, PWM4, input, X)," &
"145 ( bc_1, PWM4, output3, X, 146, 1, PULL1)," &
"146 ( bc_1, *, control, 1)," &
"147 ( bc_4, XD(12), input, X)," &
"148 ( bc_1, XD(12), output3, X, 8, 1, PULL1)," &
"149 ( bc_4, XD(13), input, X)," &
"150 ( bc_1, XD(13), output3, X, 8, 1, PULL1)," &
"151 ( bc_4, PWM5, input, X)," &
"152 ( bc_1, PWM5, output3, X, 153, 1, PULL1)," &
"153 ( bc_1, *, control, 1)," &
"154 ( bc_4, PWM6, input, X)," &
"155 ( bc_1, PWM6, output3, X, 156, 1, PULL1)," &
"156 ( bc_1, *, control, 1)," &
"157 ( bc_4, T1PWM_T1CMP, input, X)," &
"158 ( bc_1, T1PWM_T1CMP, output3, X, 159, 1, PULL1)," &
"159 ( bc_1, *, control, 1)," &
"160 ( bc_1, XA(4), output3, X, 2, 1, Z)," &
"161 ( bc_4, T2PWM_T2CMP, input, X)," &
"162 ( bc_1, T2PWM_T2CMP, output3, X, 163, 1, PULL1)," &
"163 ( bc_1, *, control, 1)," &
"164 ( bc_4, CAP1_QEP1, input, X)," &
"165 ( bc_1, CAP1_QEP1, output3, X, 166, 1, PULL1)," &
"166 ( bc_1, *, control, 1)," &
"167 ( bc_4, CAP2_QEP2, input, X)," &
"168 ( bc_1, CAP2_QEP2, output3, X, 169, 1, PULL1)," &
"169 ( bc_1, *, control, 1)," &
"170 ( bc_1, XA(5), output3, X, 2, 1, Z)," &
"171 ( bc_4, CAP3_QEPI1, input, X)," &
"172 ( bc_1, CAP3_QEPI1, output3, X, 173, 1, PULL1)," &
"173 ( bc_1, *, control, 1)," &
"174 ( bc_4, T1CTRIPn_PDPINTAn, input, X)," &
"175 ( bc_1, T1CTRIPn_PDPINTAn, output3, X, 176, 1, PULL1)," &
"176 ( bc_1, *, control, 1)," &
"177 ( bc_1, XA(6), output3, X, 2, 1, Z)," &
"178 ( bc_4, T2CTRIPn_EVASOCn, input, X)," &
"179 ( bc_1, T2CTRIPn_EVASOCn, output3, X, 180, 1, PULL1)," &
"180 ( bc_1, *, control, 1)," &
"181 ( bc_4, TDIRA, input, X)," &
"182 ( bc_1, TDIRA, output3, X, 183, 1, PULL1)," &
"183 ( bc_1, *, control, 1)," &
"184 ( bc_4, TCLKINA, input, X)," &
"185 ( bc_1, TCLKINA, output3, X, 186, 1, PULL1)," &
"186 ( bc_1, *, control, 1)," &
"187 ( bc_1, XA(7), output3, X, 2, 1, Z)," &
"188 ( bc_1, XCLKOUT, output3, X, 116, 1, Z)," &
"189 ( bc_1, XA(8), output3, X, 2, 1, Z)," &
"190 ( bc_4, C1TRIPn, input, X)," &
"191 ( bc_1, C1TRIPn, output3, X, 192, 1, PULL1)," &
"192 ( bc_1, *, control, 1)," &
"193 ( bc_4, C2TRIPn, input, X)," &
"194 ( bc_1, C2TRIPn, output3, X, 195, 1, PULL1)," &
"195 ( bc_1, *, control, 1)," &
"196 ( bc_4, C3TRIPn, input, X)," &
"197 ( bc_1, C3TRIPn, output3, X, 198, 1, PULL1)," &
"198 ( bc_1, *, control, 1)," &
"199 ( bc_1, XA(9), output3, X, 2, 1, Z)," &
"200 ( bc_1, XA(10), output3, X, 2, 1, Z)," &
"201 ( bc_1, XA(11), output3, X, 2, 1, Z)," &
"202 ( bc_1, XZCS6AND7n, output3, X, 49, 1, Z)," &
"203 ( bc_1, XA(12), output3, X, 2, 1, Z)," &
"204 ( bc_4, XD(14), input, X)," &
"205 ( bc_1, XD(14), output3, X, 8, 1, PULL1)," &
"206 ( bc_4, XF_XPLLDISn, input, X)," &
"207 ( bc_1, XF_XPLLDISn, output3, X, 208, 1, PULL1)," &
"208 ( bc_1, *, control, 1)," &
"209 ( bc_1, XA(13), output3, X, 2, 1, Z)," &
"210 ( bc_1, XA(14), output3, X, 2, 1, Z)," &
"211 ( bc_4, XD(15), input, X)," &
"212 ( bc_1, XD(15), output3, X, 8, 1, PULL1)," &
"213 ( bc_1, XA(15), output3, X, 2, 1, Z)," &
"214 ( bc_4, XINT1_XBIOn, input, X)," &
"215 ( bc_1, XINT1_XBIOn, output3, X, 216, 1, Z)," &
"216 ( bc_1, *, control, 1)," &
"217 ( bc_4, XNMI_XINT13, input, X)," &
"218 ( bc_1, XNMI_XINT13, output3, X, 219, 1, PULL1)," &
"219 ( bc_1, *, control, 1)," &
"220 ( bc_4, XINT2_ADCSOC, input, X)," &
"221 ( bc_1, XINT2_ADCSOC, output3, X, 222, 1, Z)," &
"222 ( bc_1, *, control, 1)," &
"223 ( bc_1, XA(16), output3, X, 2, 1, Z)," &
"224 ( bc_4, SCITXDA, input, X)," &
"225 ( bc_1, SCITXDA, output3, X, 226, 1, PULL1)," &
"226 ( bc_1, *, control, 1)," &
"227 ( bc_1, XA(17), output3, X, 2, 1, Z)," &
"228 ( bc_4, SCIRXDA, input, X)," &
"229 ( bc_1, SCIRXDA, output3, X, 230, 1, PULL1)," &
"230 ( bc_1, *, control, 1)," &
"231 ( bc_1, XA(18), output3, X, 2, 1, Z)," &
"232 ( bc_4, XHOLDn, input, X)," &
"233 ( bc_4, XREADY, input, X)," &
"234 ( bc_1, XRSn, output3, X, 235, 1, PULL1)," &
"235 ( bc_1, *, control, 1)," &
"236 ( bc_4, XRSn, input, X)";
end TMS320F2812;
