BSDL Files Library for JTAG
The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BS/JTAG tools

ChipVORX ISP IP for Ultra Fast Flash Programming
BSDL File: DS21Q42 Download View details  


-- File Name		:DS21Q42.BSD
-- Created by		:Dallas Semiconductor
-- Documentation		:DS21Q42 series data sheets
--
-- 
--
-- BSDL Revision		:1.2
--
-- Date created	        :08/10/99
-- Date modified	:05/25/00
-- Device	        :DS21Q42
-- Package	        :128-pin LQFP
-- 
--
-- Dallas Semiconductor customers are advised to obtain the latest version of 
-- device specifications before relying on any published information contained 
-- herein. Dallas Semiconductor assumes no responsibility or liability arising 
-- out of the application of any information described herein.
--
-- The characters "/", "(", ")" and "*" have been removed from signal names for 
-- compatibility with BSDL file format.
-- 
-- 
entity DS21Q42 is
generic (PHYSICAL_PIN_MAP : string := "LQFP_128");
port (
A8MCLK		:buffer bit;
A0		:in bit;
A1		:in bit;
A2		:in bit;
A3		:in bit;
A4		:in bit;
A5		:in bit;
A6ALEAS	:in bit;
A7 		:in bit;
BTS		:in bit;
CLKSI		:in bit;
CS		:in bit;
D0AD0		:inout bit;
D1AD1		:inout bit;
D2AD2		:inout bit;
D3AD3		:inout bit;
D4AD4		:inout bit;
D5AD5		:inout bit;
D6AD6		:inout bit;
D7AD7		:inout bit;
FMS		:in bit;
FS0		:in bit;
FS1		:in bit;
INT		:out bit;
JTCLK		:in bit;
JTDI		:in bit;
JTDO		:out bit;
JTMS		:in bit;
JTRST		:in bit;
MUX		:in bit;
RCHBLK0	:out bit;
RCHBLK1	:out bit;
RCHBLK2	:out bit;
RCHBLK3	:out bit;
RCLK0		:in bit;
RCLK1		:in bit;
RCLK2		:in bit;
RCLK3		:in bit;
RDDS 		:in bit;
RFSYNC0	:out bit;
RFSYNC1	:out bit;
RFSYNC2	:out bit;
RFSYNC3	:out bit;
RLCLK0	:out bit;
RLCLK1	:out bit;
RLCLK2	:out bit;
RLCLK3	:out bit;
RLINK0	:out bit;
RLINK1	:out bit;
RLINK2	:out bit;
RLINK3	:out bit;
RNEG0		:in bit;
RNEG1		:in bit;
RNEG2		:in bit;
RNEG3		:in bit;
RPOS0		:in bit;
RPOS1		:in bit;
RPOS2		:in bit;
RPOS3		:in bit;
RSER0		:out bit;
RSER1		:out bit;
RSER2		:out bit;
RSER3		:out bit;
RSIG0		:out bit;
RSIG1		:out bit;
RSIG2		:out bit;
RSIG3		:out bit;
RSYNC0	:inout bit;
RSYNC1	:inout bit;
RSYNC2	:inout bit;
RSYNC3	:inout bit;
RSYSCLK0	:in bit;
RSYSCLK1	:in bit;
RSYSCLK2	:in bit;
RSYSCLK3	:in bit;
TCHBLK0	:buffer bit;
TCHBLK1	:buffer bit;
TCHBLK2	:buffer bit;
TCHBLK3	:buffer bit;
TCLK0		:in bit;
TCLK1		:in bit;
TCLK2		:in bit;
TCLK3		:in bit;
TEST		:in bit;
TLCLK0	:buffer bit;
TLCLK1	:buffer bit;
TLCLK2	:buffer bit;
TLCLK3	:buffer bit;
TLINK0	:in bit;
TLINK1	:in bit;
TLINK2	:in bit;
TLINK3	:in bit;
TNEG0		:buffer bit;
TNEG1		:buffer bit;
TNEG2		:buffer bit;
TNEG3		:buffer bit;
TPOS0		:buffer bit;
TPOS1		:buffer bit;
TPOS2		:buffer bit;
TPOS3		:buffer bit;
TSER0		:in bit;
TSER1		:in bit;
TSER2		:in bit;
TSER3		:in bit;
TSIG0		:in bit;
TSIG1		:in bit;
TSIG2		:in bit;
TSIG3		:in bit;
TSSYNC0	:in bit;
TSSYNC1	:in bit;
TSSYNC2	:in bit;
TSSYNC3	:in bit;
TSYNC0	:inout bit;
TSYNC1	:inout bit;
TSYNC2	:inout bit;
TSYNC3	:inout bit;
TSYSCLK0	:in bit;
TSYSCLK1	:in bit;
TSYSCLK2	:in bit;
TSYSCLK3	:in bit;
WRRW		:in bit;
VDD		:linkage bit_vector(1 to 3);
VSS		:linkage bit_vector(1 to 3);
SPARE1	:linkage bit
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of DS21Q42 : entity is
	"STD_1149_1_1993";
attribute PIN_MAP of DS21Q42 : entity is PHYSICAL_PIN_MAP;
constant LQFP_128 : PIN_MAP_STRING :=
"TCHBLK0:1,"&
"TPOS0:2,"&
"TNEG0:3,"&
"RLINK0:4,"&
"RLCLK0:5,"&
"RCLK0:6,"&
"RNEG0:7,"&
"RPOS0:8,"&
"RSIG0:9,"&
"RCHBLK0:10,"&
"RSYSCLK0:11,"&
"RSYNC0:12,"&
"RSER0:13,"&
"RFSYNC0:17,"&
"JTRST:18,"&
"TCLK0:19,"&
"TLCLK0:20,"&
"TSYNC0:21,"&
"TLINK0:22,"&
"A0:23,"&
"A1:24,"&
"A2:25,"&
"A3:26,"&
"A4:27,"&
"A5:28,"&
"A6ALEAS:29,"&
"INT:30,"&
"TSYSCLK1:31,"&
"TSER1:32,"&
"TSSYNC1:33,"&
"TSIG1:34,"&
"TCHBLK1:35,"&
"TPOS1:36,"&
"TNEG1:37,"&
"RLINK1:38,"&
"RLCLK1:39,"&
"RCLK1:40,"&
"RNEG1:41,"&
"RPOS1:42,"&
"RSIG1:43,"&
"RCHBLK1:44,"&
"RSYSCLK1:45,"&
"A7:46,"&
"FMS:47,"&
"RSYNC1:48,"&
"RSER1:49,"&
"JTMS:50,"&
"RFSYNC1:51,"&
"JTCLK:52,"&
"TCLK1:53,"&
"TLCLK1:54,"&
"TSYNC1:55,"&
"TLINK1:56,"&
"TEST:57,"&
"FS0:58,"&
"FS1:59,"&
"CS:60,"&
"BTS:61,"&
"RDDS:62,"&
"WRRW:63,"&
"MUX:64,"&
"TSYSCLK2:65,"&
"TSER2:66,"&
"TSSYNC2:67,"&
"TSIG2:68,"&
"TCHBLK2:69,"&
"TPOS2:70,"&
"TNEG2:71,"&
"RLINK2:72,"&
"RLCLK2:73,"&
"RCLK2:74,"&
"RNEG2:75,"&
"RPOS2:76,"&
"RSIG2:77,"&
"RCHBLK2:80,"&
"RSYSCLK2:81,"&
"RSYNC2:82,"&
"RSER2:83,"&
"JTDI:84,"&
"RFSYNC2:85,"&
"JTDO:86,"&
"TCLK2:87,"&
"TLCLK2:88,"&
"TSYNC2:89,"&
"TLINK2:90,"&
"TSYSCLK3:91,"&
"TSER3:92,"&
"TSSYNC3:93,"&
"TSIG3:94,"&
"TCHBLK3:95,"&
"TPOS3:96,"&
"TNEG3:97,"&
"RLINK3:98,"&
"RLCLK3:99,"&
"RCLK3:100,"&
"RNEG3:101,"&
"RPOS3:102,"&
"RSIG3:103,"&
"RCHBLK3:104,"&
"RSYSCLK3:105,"&
"RSYNC3:106,"&
"RSER3:107,"&
"A8MCLK:108,"&
"RFSYNC3:109,"&
"CLKSI:112,"&
"TCLK3:113,"&
"TLCLK3:114,"&
"TSYNC3:115,"&
"TLINK3:116,"&
"D0AD0:117,"&
"D1AD1:118,"&
"D2AD2:119,"&
"D3AD3:120,"&
"D4AD4:121,"&
"D5AD5:122,"&
"D6AD6:123,"&
"D7AD7:124,"&
"TSYSCLK0:125,"&
"TSER0:126,"&
"TSSYNC0:127,"&
"TSIG0:128,"&
"VDD:(15, 79, 111),"&
"VSS:(14, 78, 110),"&
"SPARE1:16";
attribute TAP_SCAN_IN of JTDI		:signal is true;
attribute TAP_SCAN_MODE of JTMS	:signal is true;
attribute TAP_SCAN_OUT of JTDO	:signal is true;
attribute TAP_SCAN_RESET of JTRST	:signal is true;
attribute TAP_SCAN_CLOCK of JTCLK	:signal is (10.00e6,BOTH);
attribute INSTRUCTION_LENGTH of DS21Q42	:entity is 3;
attribute INSTRUCTION_OPCODE of DS21Q42	:entity is
"EXTEST (000),"&
"BYPASS (111),"&
"SAMPLE (010),"&
"IDCODE (001),"&
"CLAMP (011),"&
"HIGHZ (100)";
attribute INSTRUCTION_CAPTURE of DS21Q42 :entity is "001";
attribute IDCODE_REGISTER of DS21Q42 :entity is
"0000"&			-- 4-bit Version
"0000000000000000"&	-- 16-bit Part Number
"00010100001"&		-- 11-bit Manufacturer's Identity
"1";				-- Mandatory LSB
attribute BOUNDARY_LENGTH of DS21Q42 :entity is 126;
attribute BOUNDARY_REGISTER of DS21Q42 :entity is 
"0	(BC_1, RFSYNC2,output2,X),"&
"1	(BC_1, RSER2,output2,X),"&
"2	(BC_7, RSYNC2,bidir,0,3,0,Z),"&
"3	(BC_2, *,control,0),"&
"4	(BC_1, RSYSCLK2,input,X),"&
"5	(BC_1, RCHBLK2,output2,X),"&
"6	(BC_1, RSIG2,output2,X),"&
"7	(BC_1, RPOS2,input,X),"&
"8	(BC_1, RNEG2,input,X),"&
"9	(BC_1, RCLK2,input,X),"&
"10	(BC_1, RLCLK2,output2,X),"&
"11	(BC_1, RLINK2,output2,X),"&
"12	(BC_1, TNEG2,output2,X),"&
"13	(BC_1, TPOS2,output2,X),"&
"14	(BC_1, TCHBLK2,output2,X),"&
"15	(BC_1, TSIG2,input,X),"&
"16	(BC_1, TSSYNC2,input,X),"&
"17	(BC_1, TSER2,input,X),"&
"18	(BC_1, TSYSCLK2,input,X),"&
"19	(BC_1, MUX,input,X),"&
"20	(BC_1, WRRW,input,X),"&
"21	(BC_1, RDDS,input,X),"&
"22	(BC_1, BTS,input,X),"&
"23	(BC_1, CS,input,X),"&
"24	(BC_1, FS1,input,X),"&
"25	(BC_1, FS0,input,X),"&
"26	(BC_1, TEST,input,X),"&
"27	(BC_1, TLINK1,input,X),"&
"28	(BC_7, TSYNC1,bidir,0,29,0,Z),"&
"29	(BC_2, *,control,0),"&
"30	(BC_1, TLCLK1,output2,X),"&
"31	(BC_1, TCLK1,input,X),"&
"32	(BC_1, RFSYNC1,output2,X),"&
"33	(BC_1, RSER1,output2,X),"&
"34	(BC_7, RSYNC1,bidir,0,35,0,Z),"&
"35	(BC_2, *,control,0),"&
"36	(BC_1, FMS,input,X),"&
"37	(BC_1, A7,input,X),"&
"38	(BC_1, RSYSCLK1,input,X),"&
"39	(BC_1, RCHBLK1,output2,X),"&
"40	(BC_1, RSIG1,output2,X),"&
"41	(BC_1, RPOS1,input,X),"&
"42	(BC_1, RNEG1,input,X),"&
"43	(BC_1, RCLK1,input,X),"&
"44	(BC_1, RLCLK1,output2,X),"&
"45	(BC_1, RLINK1,output2,X),"&
"46	(BC_1, TNEG1,output2,X),"&
"47	(BC_1, TPOS1,output2,X),"&
"48	(BC_1, TCHBLK1,output2,X),"&
"49	(BC_1, TSIG1,input,X),"&
"50	(BC_1, TSSYNC1,input,X),"&
"51	(BC_1, TSER1,input,X),"&
"52	(BC_1, TSYSCLK1,input,X),"&
"53	(BC_1, INT,output2,X),"&
"54	(BC_1, A6ALEAS,input,X),"&
"55	(BC_1, A5,input,X),"&
"56	(BC_1, A4,input,X),"&
"57	(BC_1, A3,input,X),"&
"58	(BC_1, A2,input,X),"&
"59	(BC_1, A1,input,X),"&
"60	(BC_1, A0,input,X),"&
"61	(BC_1, TLINK0,input,X),"&
"62	(BC_7, TSYNC0,bidir,0,63,0,Z),"&
"63	(BC_2, *,control,0),"&
"64	(BC_1, TLCLK0,output2,X),"&
"65	(BC_1, TCLK0,input,X),"&
"66	(BC_1, RFSYNC0,output2,X),"&
"67	(BC_1, *,internal,X),"&
"68	(BC_1, RSER0,output2,X),"&
"69	(BC_7, RSYNC0,bidir,0,70,0,Z),"&
"70	(BC_2, *,control,0),"&
"71	(BC_1, RSYSCLK0,input,X),"&
"72	(BC_1, RCHBLK0,output2,X),"&
"73	(BC_1, RSIG0,output2,X),"&
"74	(BC_1, RPOS0,input,X),"&
"75	(BC_1, RNEG0,input,X),"&
"76	(BC_1, RCLK0,input,X),"&
"77	(BC_1, RLCLK0,output2,X),"&
"78	(BC_1, RLINK0,output2,X),"&
"79	(BC_1, TNEG0,output2,X),"&
"80	(BC_1, TPOS0,output2,X),"&
"81	(BC_1, TCHBLK0,output2,X),"&
"82	(BC_1, TSIG0,input,X),"&
"83	(BC_1, TSSYNC0,input,X),"&
"84	(BC_1, TSER0,input,X),"&
"85	(BC_1, TSYSCLK0,input,X),"&
"86	(BC_7, D7AD7,bidir,0,94,0,Z),"&
"87	(BC_7, D6AD6,bidir,0,94,0,Z),"&
"88	(BC_7, D5AD5,bidir,0,94,0,Z),"&
"89	(BC_7, D4AD4,bidir,0,94,0,Z),"&
"90	(BC_7, D3AD3,bidir,0,94,0,Z),"&
"91	(BC_7, D2AD2,bidir,0,94,0,Z),"&
"92	(BC_7, D1AD1,bidir,0,94,0,Z),"&
"93	(BC_7, D0AD0,bidir,0,94,0,Z),"&
"94	(BC_2, *,control,0),"&
"95	(BC_1, TLINK3,input,X),"&
"96	(BC_7, TSYNC3,bidir,0,97,0,Z),"&
"97   (BC_2, *,control,0),"&
"98	(BC_1, TLCLK3,output2,X),"&
"99	(BC_1, TCLK3,input,X),"&
"100	(BC_1, CLKSI,input,X),"&
"101	(BC_1, RFSYNC3,output2,X),"&
"102	(BC_1, A8MCLK,output2,X),"&
"103	(BC_1, RSER3,output2,X),"&
"104	(BC_7, RSYNC3,bidir,0,105,0,Z),"&
"105	(BC_2, *,control,0),"&
"106	(BC_1, RSYSCLK3,input,X),"&
"107	(BC_1, RCHBLK3,output2,X),"&
"108	(BC_1, RSIG3,output2,X),"&
"109	(BC_1, RPOS3,input,X),"&
"110	(BC_1, RNEG3,input,X),"&
"111	(BC_1, RCLK3,input,X),"&
"112	(BC_1, RLCLK3,output2,X),"&
"113	(BC_1, RLINK3,output2,X),"&
"114	(BC_1, TNEG3,output2,X),"&
"115	(BC_1, TPOS3,output2,X),"&
"116	(BC_1, TCHBLK3,output2,X),"&
"117	(BC_1, TSIG3,input,X),"&
"118	(BC_1, TSSYNC3,input,X),"&
"119	(BC_1, TSER3,input,X),"&
"120	(BC_1, TSYSCLK3,input,X),"&
"121	(BC_1, TLINK2,input,X),"&
"122	(BC_7, TSYNC2,bidir,0,123,0,Z),"&
"123	(BC_2, *,control,0),"&
"124	(BC_1, TLCLK2,output2,X),"&
"125	(BC_1, TCLK2,input,X)";
end DS21Q42;

This library contains 7716 BSDL files (for 6087 distinct entities) from 66 vendors
Last BSDL model (chip) was added on Oct 17, 2017 16:06
info@bsdl.info