BSDL Files Library for JTAG
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ChipVORX ISP IP for Ultra Fast Flash Programming
BSDL File: DSP56F801 Download View details  


-- M O T O R O L A   S S D T   J T A G   S O F T W A R E
-- BSDL File Generated: Thu Jan  6 10:15:39 2000
--
-- Revision History:
--

entity DSP56F801 is 
	generic(PHYSICAL_PIN_MAP : string := "X48LQFP");

	port (  TRST_B:	in	bit;
	           TDO:	out	bit;
	           TDI:	in	bit;
	           TMS:	in	bit;
	           TCK:	in	bit;
		   TD0: inout   bit;       
		   TD1: inout   bit;       
		   TD2: inout   bit;      
		  SS_B: inout   bit;     
		  MISO: inout   bit;     
		  MOSI: inout   bit;     
		  SCLK: inout   bit;     
		  TXD0: inout   bit;     
	    GROUND_IO5: linkage bit;      
	     POWER_IO5: linkage bit;      
	          RXD0: inout   bit;     
	          DE_B: out     bit;
	           TCS: linkage bit;      
	       IREQA_B: in      bit;  
	        VCAPC2: linkage bit;    
	    GROUND_IO4: linkage bit;      
	     POWER_IO4: linkage bit;      
	         EXTAL: linkage bit;    
	          XTAL: linkage bit;    
	       RESET_B: in      bit;  
	     VDDA_ADC1: linkage bit;     
	     VSSA_ADC1: linkage bit;     
	     POWER_IO2: linkage bit;      
	    GROUND_IO2: linkage bit;      
	       FAULTA0: in      bit;  
	          ANA0: linkage bit;     
	          ANA1: linkage bit;     
	          ANA2: linkage bit;     
	           VRH: linkage bit;      
	          ANA3: linkage bit;     
	          ANA4: linkage bit;     
	          ANA5: linkage bit;     
	          ANA6: linkage bit;     
	          ANA7: linkage bit;     
	         PWMA0: out     bit;    
	        VCAPC1: linkage bit;    
	     POWER_IO1: linkage bit;      
	    GROUND_IO1: linkage bit;      
	         PWMA1: out     bit;    
	         PWMA2: out     bit;    
	         PWMA3: out     bit;   
	         PWMA4: out     bit;   
           	 PWMA5: out     bit);   


	use STD_1149_1_1994.all;

	attribute COMPONENT_CONFORMANCE of DSP56F801 : entity is "STD_1149_1_1993";

	attribute PIN_MAP of DSP56F801 : entity is PHYSICAL_PIN_MAP;

	constant X48LQFP : PIN_MAP_STRING := 
	"TD0:          1, " &
	"TD1:          2, " &
	"TD2:          3, " &
	"SS_B:         4, " &
	"MISO:         5, " &
	"MOSI:         6, " &
	"SCLK:         7, " &
	"TXD0:         8, " &
	"GROUND_IO5:   9, " &
	"POWER_IO5:   10, " &
	"RXD0:        11, " &
	"DE_B:        12, " &
	"TCS:         13, " &
	"TCK:         14, " &
	"TMS:         15, " &
	"IREQA_B:     16, " &
	"TDI:         17, " &
	"VCAPC2:      18, " &
	"GROUND_IO4:  19, " &
	"POWER_IO4:   20, " &
	"EXTAL:       21, " &
	"XTAL:        22, " &
	"TDO:         23, " &
	"TRST_B:      24, " &
	"RESET_B:     25, " &
	"VDDA_ADC1:   26, " &
	"VSSA_ADC1:   27, " &
	"POWER_IO2:   28, " &
	"GROUND_IO2:  29, " &
	"FAULTA0:     30, " &
	"ANA0:        31, " &
	"ANA1:        32, " &
	"ANA2:        33, " &
	"VRH:         34, " &
	"ANA3:        35, " &
	"ANA4:        36, " &
	"ANA5:        37, " &
	"ANA6:        38, " &
	"ANA7:        39, " &
	"PWMA0:       40, " &
	"VCAPC1:      41, " &
	"POWER_IO1:   42, " &
	"GROUND_IO1:  43, " &
	"PWMA1:       44, " &
	"PWMA2:       45, " &
	"PWMA3:       46, " &
	"PWMA4:       47, " &
	"PWMA5:       48";

 attribute TAP_SCAN_IN    of     TDI: signal is true;
 attribute TAP_SCAN_OUT   of     TDO: signal is true;
 attribute TAP_SCAN_MODE  of     TMS: signal is true;
 attribute TAP_SCAN_RESET of  TRST_B: signal is true;
 attribute TAP_SCAN_CLOCK of     TCK: signal is (20.0e6, BOTH);


	attribute INSTRUCTION_LENGTH of DSP56F801 : entity is 4;

	attribute INSTRUCTION_OPCODE of DSP56F801 : entity is 
	   "EXTEST       	(0000)," &
	   "SAMPLE       	(0001)," &
	   "IDCODE       	(0010)," &
	   "CLAMP        	(0101)," &
	   "HIGHZ        	(0100)," &
	   "EXTEST_PULLUP	(0011)," &
	   "ENABLE_ONCE  	(0110)," &
	   "DEBUG_REQUEST	(0111)," &
	   "BYPASS       	(1111)";

	attribute INSTRUCTION_CAPTURE of DSP56F801 : entity is "XX01";
	attribute INSTRUCTION_PRIVATE of DSP56F801 : entity is 
	   "ENABLE_ONCE, DEBUG_REQUEST ";

	attribute IDCODE_REGISTER   of DSP56F801 : entity is 
	   "00000001111100100001000000011101";

	attribute REGISTER_ACCESS of DSP56F801 : entity is 
	   "BOUNDARY   (EXTEST_PULLUP)," &
	   "BYPASS   (ENABLE_ONCE, DEBUG_REQUEST)" ;

	attribute BOUNDARY_LENGTH of DSP56F801 : entity is 53;

	attribute BOUNDARY_REGISTER of DSP56F801 : entity is 
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   " 52    (BC_1, PWMA5,       output3,       X,       51,   1,   Z)," &
	   " 51    (BC_1, *,           control,       1)," &
	   " 50    (BC_1, PWMA4,       output3,       X,       49,   1,   Z)," &
	   " 49    (BC_1, *,           control,       1)," &
	   " 48    (BC_1, PWMA3,       output3,       X,       47,   1,   Z)," &
	   " 47    (BC_1, *,           control,       1)," &
	   " 46    (BC_1, PWMA2,       output3,       X,       45,   1,   Z)," &
	   " 45    (BC_1, *,           control,       1)," &
	   " 44    (BC_1, PWMA1,       output3,       X,       43,   1,   Z)," &
	   " 43    (BC_1, *,           control,       1)," &
	   " 42    (BC_1, PWMA0,       output3,       X,      41,   1,   Z)," &
	   " 41    (BC_1, *,           control,       1)," &
	   " 40    (BC_1, FAULTA0,     input,         X)," &
	   " 39    (BC_1, RESET_B,     input,         X)," &
	   " 38    (BC_1, IREQA_B,     input,         X)," &
	   " 37    (BC_1, DE_B,        output3,       X,      36,   1,   Z)," &
	   " 36    (BC_1, *,           control,       1)," &
	   " 35    (BC_1, RXD0,        input,         X)," &
	   " 34    (BC_1, RXD0,        output3,       X,      33,   1,   PULL1)," &
	   " 33    (BC_1, *,           control,       1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   " 32    (BC_1, *,           internal,      1)," &
	   " 31    (BC_1, TXD0,        input,         X)," &
	   " 30    (BC_1, TXD0,        output3,       X,      29,   1,   PULL1)," &
	   " 29    (BC_1, *,           control,       1)," &
	   " 28    (BC_1, *,           internal,      1)," &
	   " 27    (BC_1, SCLK,        input,         X)," &
	   " 26    (BC_1, SCLK,        output3,       X,      25,   1,   PULL1)," &
	   " 25    (BC_1, *,           control,       1)," &
	   " 24    (BC_1, *,           internal,      1)," &
	   " 23    (BC_1, MOSI,        input,         X)," &
	   " 22    (BC_1, MOSI,        output3,       X,      21,   1,   PULL1)," &
	   " 21    (BC_1, *,           control,       1)," &
	   " 20    (BC_1, *,           internal,      1)," &
	   " 19    (BC_1, MISO,        input,         X)," &
	   " 18    (BC_1, MISO,        output3,       X,      17,   1,   PULL1)," &
	   " 17    (BC_1, *,           control,       1)," &
	   " 16    (BC_1, *,           internal,      1)," &
	   " 15    (BC_1, SS_B,        input,         X)," &
	   " 14    (BC_1, SS_B,        output3,       X,      13,   1,   PULL1)," &
	   " 13    (BC_1, *,           control,       1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   " 12    (BC_1, *,           internal,      1)," &
	   " 11    (BC_1, TD2,         input,         X)," &
	   " 10    (BC_1, TD2,         output3,       X,       9,   1,   PULL1)," &
	   "  9    (BC_1, *,           control,       1)," &
	   "  8    (BC_1, *,           internal,      1)," &
	   "  7    (BC_1, TD1,         input,         X)," &
	   "  6    (BC_1, TD1,         output3,       X,       5,   1,   PULL1)," &
	   "  5    (BC_1, *,           control,       1)," &
	   "  4    (BC_1, *,           internal,      1)," &
	   "  3    (BC_1, TD0,         input,         X)," &
	   "  2    (BC_1, TD0,         output3,       X,       1,   1,   PULL1)," &
	   "  1    (BC_1, *,           control,       1)," &
	   "  0    (BC_1, *,           internal,      1)";

end DSP56F801;

This library contains 7716 BSDL files (for 6087 distinct entities) from 66 vendors
Last BSDL model (chip) was added on Oct 17, 2017 16:06
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