BSDL Files Library for JTAG
The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BS/JTAG tools

ChipVORX ISP IP for Ultra Fast Flash Programming
BSDL File: fstr_0 Download View details  


-- ***************************************************************************
-- Intel(R) Xeon(tm) Processor MP Core Boundary Scan Descriptor Language 
-- (BSDL) Model, Version 1.0
--
--
-- 
--
-- ***************************************************************************
-- Information in this document is provided in connection with Intel products.
-- No license, express or implied, by estoppel or otherwise, to any
-- intellectual property rights is granted by this document. Except as
-- provided in Intel's Terms and Conditions of Sale for such products,
-- Intel assumes no liability whatsoever, and Intel disclaims any express or
-- implied warranty, relating to sale and/or use of Intel products including
-- liability or warranties relating to fitness for a particular purpose,
-- merchantability, or infringement of any patent, copyright or other
-- intellectual property right. Intel products are not intended for use in
-- medical, life saving, or life sustaining applications.
--
-- Intel may make changes to specifications and product descriptions at any
-- time, without notice.
--
-- The Intel Xeon Processor MP may contain design defects or errors 
-- known as errata which may cause the product to deviate from published
-- specifications. Current characterized errata are available on request.
--
-- Contact your local Intel sales office or your distributor to obtain the
-- latest specifications and before placing your product order.
--
-- Copyright (c) Intel Corporation 2001. Other names and brands may be
-- claimed as the property of others.
-- ***************************************************************************

entity fstr_0 is

  generic(PHYSICAL_PIN_MAP : string := "FSTR_PGAN");

  port (
 	TDO	: out    bit;			-- Diagnostic    - tap data out
 	TRST	: in      bit;			-- Diagnostic    - tap reset
 	TMS	: in      bit;			-- Diagnostic    - tap mode select
 	TDI	: in      bit;		      	-- Diagnostic    - tap data in
 	TCK	: in      bit;		      	-- Diagnostic    - tap clock
	GTLREF2	: linkage bit;	      		-- Analog Pin    - 
  	LINT1	: in      bit;		      	-- APIC 	 - Local Interrupt,NMI
 	LINT0	: in      bit;		      	-- APIC	      	 - Local Interrupt,INT
 	BPRI	: in      bit;		      	-- Arbitration   - Priority agent bus arbitration
	DEFER	: in      bit;		      	-- Snoop          - defer signal 
 	HITM	: inout   bit;			-- Snoop          - snoop hit modified
 	HIT	: inout   bit;			-- Snoop          - snoop hit
 	RS	: in      bit_vector(2 downto 0);  	-- Response status
 	LOCK	: inout   bit;			-- Arbitration   - Locked transactions
 	BR0	: inout   bit;			-- Arbitration  - symmetric agent bus arbitration
 	ADS	: inout   bit;			-- Request      - address strobe
 	BNR	: inout   bit;			-- Arbitration  - block next request
 	TRDY	: in  bit;		      	-- Response     - target ready   
 	DBSY	: inout  bit;			-- Data	      	- data bus busy
 	DRDY	: inout  bit;			-- Data	     	- Data phase data ready
 	REQ	: inout  bit_vector( 4 downto 0); 	-- Request        - request command
 	A	: inout  bit_vector(35 downto 3); 	-- Address bus
 	ADSTB	: inout  bit_vector( 1 downto 0); 	-- Request       - address bus strobe
	BR1	: in  bit;		      	-- Arbitration   - symmetric bus arbitration
 	BR2	: in  bit;		      	-- Arbitration   - symmetric bus arbitration
 	BR3	: in  bit;		      	-- Arbitration   - symmetric bus arbitration
 	AP	: inout bit_vector( 1 downto 0); 	-- address/extended request parity
 	RSP	: in  bit;		      	-- Response    - Response status parity
 	BINIT	: inout  bit;			-- Error	     - bus initialization
 	MCERR	: inout  bit;			-- Error	     - machine check error
 	INIT	: in  bit;		      	-- Exec Control  - Processor initialization
 	STPCLK	: in  bit;		      	-- Pwr/Clk       - processor stop clock control
 	IERR	: out  bit;		      	-- Error	     - internal processor error
 	BPM	: inout   bit_vector( 5 downto 0); 	-- Diagnostic - proformance monitoring break points
	GTLREF3	: linkage bit;	      	-- Analog Pin    - 
	VCCA	: linkage bit;	     	-- Pwr/Clk       - Analog Vcc for PLL
  	VSSA	: linkage bit;		-- Pwr/Clk       - Analog Vcc for PLL and IOPLL
  	VCCIOPLL   : linkage bit;	      		-- Pwr/Clk      - Analog Vcc for I/O PLL
	VID	: out bit_vector(4 downto 0);		-- Pwr/Clk	- Voltage Identification
	PWRGOOD    : in  bit;		      		-- Pwr/Clk      - System Power Good
	SLP	: in  bit;		      		-- Pwr/Clk      - Sleep Pin
	RESET	: in  bit;		      		-- Control      - System Reset
	GTLREF1	: linkage bit;	      			-- Analog Pin   - 
 	BCLK	: inout   bit_vector (1 downto 0); 	-- Pwr/Clk	- System bus clock
	D	: inout   bit_vector(63 downto 0); 	-- Data      	- Data bus 
 	DSTBN	: inout   bit_vector( 3 downto 0); 	-- Data      	- Data bus differential probe
 	DSTBP	: inout   bit_vector( 3 downto 0); 	-- Data      	- Data bus differential probe
 	DBI	: inout   bit_vector( 3 downto 0); 	-- Data      	- Dynamic data bus inversion
	COMP	: linkage bit_vector( 1 downto 0); 	-- Pwr/Clk	- Used to configure the AGTL+ drivers
 	DP	: inout   bit_vector( 3 downto 0); 	-- Data      	- Data bus parity on 16-bit granularity
	GTLREF0	: linkage bit;	      		-- Analog Pin  	- 
 	VCCSENSE  : linkage bit;	      	-- Pwr/Clk  		- Sense the Vcc power plane
	VSSSENSE	   : linkage bit;	-- Pwr/Clk		- Sense the Vss power plane
	FERR	: out  bit;		      	-- Compatibility 	- Floating point error
 	A20M	: in  bit;		      	-- Compatibility 	- Address 20 mask
 	SMI	: in  bit;		      	-- Compatibility 	- System management interrupt
 	IGNNE	: in  bit;		      	-- Compatibility 	- Ignore numeric errors
 	THRMTRIP   : out  bit;	      	-- Pwr/Clk		- Thermal sensor
 	PROCHOT    : out  bit;	      	-- Pwr/Clk		- Thermal sensor
	RESERVED : linkage bit_vector(18 downto 0);	      	--Reserved pins
	NC	: linkage bit_vector(68 downto 0);		--No Connect pins
	ODTEN	: in   bit;		      	--Pwr/Clk	-- On Die Termination
	SKTOCC	: out  bit;		      	--Pwr/Clk	-- Socket Occupied
	SMALERT : out  bit;			--SMBus		--SMBus Alert
	SMCLK	: in  bit;			--SMBus		--SMBus Clock
	SMDATA : inout  bit;			--SMBus		--SMBus Data IO
	SMEPA	: in  bit_vector(2 downto 0);	--SMBus		--SMBus EEPROM Address
	SMTSA	: in  bit_vector(1 downto 0);	--SMBus		--SMBus Thermal Sensor Address
	SMVCC	: linkage bit_vector(1 downto 0);		--SMBus		--SMBus Power
	SMWP	: in  bit;			--SMBus		--SMBus Write Protect	
	TESTHI 	: in  bit_vector(6 downto 0);  	-- Reserved	-- Reserved for Intel use
	VCC  	: linkage  bit_vector(154 downto 0);	      	--Pwr/Clk
	VSS   	: linkage  bit_vector(154 downto 0)	      	--Pwr/Clk
);

  use STD_1149_1_1994.all;
  use fstr_cells.all;

  attribute COMPONENT_CONFORMANCE of FSTR_0 : entity is "STD_1149_1_1993" ;

  attribute PIN_MAP of FSTR_0 : entity is PHYSICAL_PIN_MAP;

  constant FSTR_PGAN : PIN_MAP_STRING :=

     " 	TDO	: E25, "  &
     " 	TRST	: F24, "  &
     " 	TMS	: A25, "  &
     " 	TDI	: C24, "  &
     " 	TCK	: E24, "  &
     "	GTLREF2	: F23,"  &
     "	LINT1	: G23,"  &
     " 	LINT0	: B24,"  &
     " 	BPRI	: D23,"  &
     "	DEFER	: C23,"  &
     " 	HITM	: A23,"  &
     " 	HIT	: E22,"  &
     " 	RS	: (F21, D22, E21), "  &
     " 	LOCK 	: A17, "  &
     " 	BR0	: D20,"  &
     " 	ADS	: D19,"  &
     " 	BNR	: F20,"  &
     " 	TRDY	: E19,"  &
     " 	DBSY	: F18,"  &
     " 	DRDY       : E18,"  &
     " 	REQ	: (B22, C20, C21, B21, B19),  "               	& -- REQ4, REQ3,...,REQ0
     " 	A	: (C8, C9, A7, A6, B7, C11, D12, E13, B8,   " & -- A(35):A(27)
     "                  	A9, D13, E14, C12, B11, B10, A10, F15,   " 	& -- A(26):A(24)
     "                    	D15, D16, C14, C15, A12, B13, B14, B16,  " & -- A(23):A(11)
     "                    	A13, D17, C17, A19, C18, B18, A20, A22), " & -- A(10):A(3)
     " 	ADSTB		: (F14, F17), "  &
     "	BR1		: F12, " &
     " 	BR2		: E11, " &
     " 	BR3		: D10, " &
     " 	AP		: (D9, E10), "   &
     " 	RSP		: C6,"   &
     " 	BINIT		: F11,"  &
     " 	MCERR		: D7,"   &
     " 	INIT		: D6,"   &
     " 	STPCLK		: D4,"   &
     " 	IERR		: E5,"   &
     " 	BPM		: (E4, E8, F5, E7, F8, F6) ,"  &
     "	GTLREF3 		: F9,"   &
     "	VCCA		: AB4,"  &
     "	VSSA		: AA5,"  &
     "	VCCIOPLL	: AD4,"  &
     "	VID		:(B3, C3, D3, E3, F3)," &		--VID4:VID0	
     "	PWRGOOD	: AB7,"  &
     "	SLP		: AE6,"  &
     "	RESET		: Y8, "  &
     "	GTLREF1		: W9,"   &
     "	BCLK		: (W5, Y4)," & -- BCLK1, BCLK0
     " 	D          : (AB6, Y9, AA8, AC5, AC6, AE7, AD7, AC8, "  & -- D63:D56
     " 	              AB10, AA10, AA11, AB13, AB12, AC14, AA14, AA13, " & -- D55:D48
     "                          AC9,  AD8, AD10,  AE9, AC11, AE10, AC12, AD11, "  & -- D47:D40
     " 	              AD14, AD13, AB15, AD18, AE13, AC17, AA16, AB16, " & -- D39:D32
     " 	              AB17, AD19, AD21, AE20, AE22, AC21, AC20, AA18, " & -- D31:D24
     " 	              AC23, AE23, AD24, AC24, AE25, AD25, AC26, AE26, " & -- D23:D16
     "                          AA19, AB19, AB22, AB20, AA21, AA22, AB23, AB25, " & -- D15:D8
     " 	             AB26, AA24,  Y23, AD27, AA25,  Y24, AA27,  Y26)," & 	-- D7:D0
     " 	DSTBN		: (Y12,  Y15,  Y18,  Y21) , " 	&
     " 	DSTBP		: (Y11,  Y14,  Y17,  Y20) , "  	&
     " 	DBI		: (AB9, AE12, AD22, AC27) , "  	&	-- DBI3:DBI0
     "	COMP		: (E16, AD16), "  		&
     " 	DP		: (AE17, AC15, AE19, AC18) , "  &
     "	GTLREF0		: W23,"  			&
     "	VCCSENSE	: B27,"			&
     "	VSSSENSE 	: D26,"			&
     "	FERR		: E27,"			&
     " 	A20M		: F27,"			&
     " 	SMI 		: C27,"			&
     " 	IGNNE 		: C26,"			&
     " 	THRMTRIP	: F26,"			&
     " 	PROCHOT	: B25, "			&
     "	ODTEN		: B5,"			&
     "	RESERVED	: (A1, A4, A15, A16, A26, B1, C5, D25, W3, Y3, Y27, Y28, "	&
     "			 AA3, AB3, AC1, AD1, AE4, AE15, AE16),"			&
     "	NC		: (A30, A31, B4, B30, B31, C1, C30, C31, D1, "		&  
     "			 D30, D31, E1, E30, E31, F1, F30, F31, G1, "			&
     "			 G30, G31, H1, H30, H31, J1, J30, J31, K1, K30, K31, L1, "	&
     "			 L30, L31, M1, M30, M31, N1, N30, N31, P1, P30, P31, "	&
     "			 R1, R30, R31, T1, T30, T31, U1, U30, U31, V1, V30, V31, "	&
     "			 W1, W30, W31, Y1, Y30, Y31, AA1, AA30, AA31, AB1, "	&
     "			 AB30, AB31, AC30, AC31, AD30, AD31), "		&
     "	SKTOCC		: A3,"			&
     "	SMALERT	: AD28,"			&
     "	SMCLK		: AC28, "			&
     "	SMDATA		: AC29,"			&
     "	SMEPA		: (AB28, AB29, AA29),"	&	--SM_EP_A2:SM_EP_A0
     "	SMTSA		: (Y29, AA28),"		&	--SM_TS_A1:SM_TS_A0
     "	SMVCC		: (AE29, AE28),"		&
     "	SMWP		: AD29,"			&
     "	TESTHI	: (AE5, AD5, AA7, Y6, W8, W7, W6), "				&
     "	VCC	: (A2, A8, A14, A18, A24, A28, B6, B12, B20, B26, B29, C2, C4, C10, "	&
     "		C16, C22, C28, D8, D14, D18, D24, D29, E2, E6, E12, E20, E26, E28, "	&
     "		F4, F10, F16, F22, F29, G2, G4, G6, G8, G24, G26, G28, H3, H5, H7, "	&
     "		H9, H23, H25, H27, H29, J2, J4, J6, J8, J24, J26, J28, K3, K5, K7, K9, "	&
     "		K23, K25, K27, K29, L2, L4, L6, L8, L24, L26, L28, M3, M5, M7, M9,"	&
     "		M23, M25, M27, M29, N3, N5, N7, N9, N23, N25, N27, N29, P2, P4,"	&
     "		P6, P8, P24, P26, P28, R3, R5, R7, R9, R23, R25, R27, R29, T2, T4, T6,"	&
     "		T8, T24, T26, T28, U3, U5, U7, U9, U23, U25, U27, U29, V2, V4, V6, "	&
     "		V8, V24, V26, V28, W25, W27, W29, Y2, Y10, Y16, Y22, AA4, AA6,"	&
     "		AA12, AA20, AA26, AB2, AB8, AB14, AB18, AB24, AC3, AC4, AC10,"	&
     "		AC16, AC22, AD2, AD6, AD12, AD20, AD26, AE3, AE8, AE14, AE18,"	&
     "		AE24),"							&
     "	VSS	:(A5, A11, A21, A27, A29, B2, B9, B15, B17, B23, B28, C7, C13, C19,"	&
     "		C25, C29, D2, D5, D11, D21, D27, D28, E9, E15, E17, E23, E29, F2,"	&
     "		F7, F13, F19, F25, F28, G3, G5, G7, G9, G25, G27, G29, H2, H4, H6,"	&
     "		H8, H24, H26, H28, J3, J5, J7, J9, J23, J25, J27, J29, K2, K4, K6 , K8,"	&
     "		K24, K26, K28, L3, L5, L7, L9, L23, L25, L27, L29, M2, M4, M6, M8,"	&
     "		M24, M26, M28, N2, N4, N6, N8, N24, N26, N28, P3, P5, P7, P9, P23,"	&
     "		P25, P27, P29, R2, R4, R6, R8, R24, R26, R28, T3, T5, T7, T9, T23,"	&
     "		T25, T27, T29, U2, U4, U6, U8, U24, U26, U28, V3, V5, V7, V9, V23,"	&
     "		V25, V27, V29, W2,W4, W24, W26, W28, Y5, Y7,Y13, Y19, Y25, AA2,"	&
     "		AA9, AA15, AA17, AA23, AB5, AB11, AB21, AB27, AC2, AC7, AC13,"	&
     "		AC19, AC25, AD3, AD9, AD15, AD17, AD23, AE2, AE11, AE21, AE27)"
  ;

--
-- Scan Port Identification
--

  attribute TAP_SCAN_IN    of TDI  : signal is true;
  attribute TAP_SCAN_MODE  of TMS  : signal is true;
  attribute TAP_SCAN_OUT   of TDO  : signal is true;
  attribute TAP_SCAN_RESET of TRST : signal is true;
  attribute TAP_SCAN_CLOCK of TCK  : signal is (16.0e6, both);

  attribute Instruction_Length of FSTR_0: entity is 7;

  attribute Instruction_Opcode  of FSTR_0: entity is

	" EXTEST   ( 0000000 ),					"  &
	" SAMPLE   ( 0000001 ),					"  &
	" IDCODE   ( 0000010 ),					"  &
	" CLAMP    ( 0000100 ),					"  &
	" RUNBIST  ( 0000111 ),					"  &
	" HIGHZ    ( 0001000 ),					"  &
	" BYPASS   ( 1111111 ),					"  &
	" Reserved ( 0000011, 0000101, 0000110, 0001001, 0001010,   "  &
	"            0001011, 0001100, 0001101, 0001110, 0001111,   "  &
	"            0010000, 0010001, 0010010, 0010011, 0010100,   "  &
	"            0010101, 0010110, 0010111, 0011000, 0011001,   "  &
	"            0011010, 0011011, 0011100, 0011101, 0011110,   "  &
	"            0011111, 0100000, 0100001, 0100010, 0100011,   "  &
	"            0100100, 0100101, 0100110, 0100111, 0101000,   "  &
	"            0101001, 0101010, 0101011, 0101100, 0101101,   "  &
	"            0101110, 0101111, 0110000, 0110001, 0110010,   "  &
	"            0110011, 0110100, 0110101, 0110110, 0110111,   "  &
	"            0111000, 0111001, 0111010, 0111011, 0111100,   "  &
	"            0111101, 0111110, 0111111, 1000000, 1000001,   "  &
	"            1000010, 1000011, 1000100, 1000101, 1000110,   "  &
	"            1000111, 1001000, 1001001, 1001100           ) "  ;  

  attribute Instruction_Capture of FSTR_0: entity is "0000001";
  attribute Instruction_Private of FSTR_0: entity is "Reserved";
--
-- FSTR IDCODE Register
--
  attribute Idcode_Register of FSTR_0: entity is
	    "0001"             	&     	-- Version, C-step
	    "1000001100000010"  &     	-- Part number
	    "00000001001"      	&     	-- Manufacturer's identity
	    "1";                     	-- Required by the 1149.1 standard
--
-- FSTR Data Register Access
--
  attribute Register_Access of FSTR_0: entity is

	    "BOUNDARY   (EXTEST, SAMPLE), "       &
	    "RUNBIST[1] (RUNBIST), "              &
	    "DEVICE_ID  (IDCODE), "               &
	    "BYPASS     (CLAMP, HIGHZ, BYPASS)";
--
--  FSTR Boundary Scan cells
--
--    BS_4 : INPUT
--    BC_2 : OUTPUT2
--    BS_G : GTL BIDIR/CONTROL Combo cell
--
--    FSTR Boundary Register Description
--    Cell 0 is closest to TDO
--
  attribute BOUNDARY_LENGTH   of FSTR_0: entity is 164;
  attribute Boundary_Register of FSTR_0 : entity is
--                                 
	     "  163  (  BC_2,   PROCHOT,    output2,    1,      163,      1,      Weak1 ), " & 
 	     "  162  (  BC_2,   THRMTRIP,   output2,    1,      162,	1,      Weak1 ), " &
 	     "  161  (  BS_4,   IGNNE,	input,      X			), " &
 	     "  160  (  BS_4,   SMI,	input,      X			), " &
 	     "  159  (  BS_4,   A20M,	input,      X			), " &
 	     "  158  (  BC_2,   FERR,	output2,    	1,      158,       1,      Weak1 ), " &
 	     "  157  (  BS_G,   D(0),	output2,    	1,       157,	    1,      Weak1 ), " &
 	     "  157  (  BS_G,   D(0),	input,      	1			), " &
 	     "  156  (  BS_G,   D(1),	output2,    	1,      156,      1,     Weak1 ), " &
 	     "  156  (  BS_G,   D(1),	input,      	1			), " &
 	     "  155  (  BS_G,   D(2),	output2,    	1,      155,      1,      Weak1 ), " &
 	     "  155  (  BS_G,   D(2),	input,      	1			), " &
 	     "  154  (  BS_G,   D(3),	output2,    	1,      154,      1,      Weak1 ), " &
 	     "  154  (  BS_G,   D(3),	input,      	1			), " &
 	     "  153  (  BS_G,   D(4),	output2,    1,      153,      1,      Weak1 ), " &
 	     "  153  (  BS_G,   D(4),	input,      1				), " &
 	     "  152  (  BS_G,   D(5),	output2,    1,      152,      1,      Weak1 ), " &
 	     "  152  (  BS_G,   D(5),	input,      1				), " &
 	     "  151  (  BS_G,   D(6),	output2,    1,      151,      1,      Weak1 ), " &
 	     "  151  (  BS_G,   D(6),	input,      1				), " &
 	     "  150  (  BS_G,   D(7),	output2,    1,      150,      1,      Weak1 ), " &
 	     "  150  (  BS_G,   D(7),	input,      1				), " &
 	     "  149  (  BS_G,   DBI(0),	output2,    1,      149,      1,      Weak1 ), " &
 	     "  149  (  BS_G,   DBI(0),	input,      1				), " &
 	     "  148  (  BS_G,   DSTBP(0),   	output2,    1,      148,      1,      Weak1 ), " &
 	     "  148  (  BS_G,   DSTBP(0),   	input,      1				), " &
 	     "  147  (  BS_G,   DSTBN(0),   output2,    1,      147,      1,      Weak1 ), " &
 	     "  147  (  BS_G,   DSTBN(0),   input,      1				), " &
 	     "  146  (  BS_G,   D(8),	output2,    1,      146,      1,      Weak1 ), " &
 	     "  146  (  BS_G,   D(8),	input,      1				), " &
 	     "  145  (  BS_G,   D(9),	output2,    1,      145,      1,      Weak1 ), " &
 	     "  145  (  BS_G,   D(9),	input,      1				), " &
 	     "  144  (  BS_G,   D(10),	output2,    1,      144,      1,      Weak1 ), " &
 	     "  144  (  BS_G,   D(10),	input,      1				), " &
 	     "  143  (  BS_G,   D(11),	output2,    1,      143,      1,      Weak1 ), " &
 	     "  143  (  BS_G,   D(11),	input,      1				), " &
 	     "  142  (  BS_G,   D(12),	output2,    1,      142,      1,      Weak1 ), " &
 	     "  142  (  BS_G,   D(12),	input,      1				), " &
 	     "  141  (  BS_G,   D(13),	output2,    1,      141,      1,      Weak1 ), " &
 	     "  141  (  BS_G,   D(13),	input,      1				), " &
 	     "  140  (  BS_G,   D(14),	output2,    1,      140,      1,      Weak1 ), " &
 	     "  140  (  BS_G,   D(14),	input,      1				), " &
 	     "  139  (  BS_G,   D(15),	output2,    1,      139,      1,      Weak1 ), " &
 	     "  139  (  BS_G,   D(15),	input,      1				), " &
 	     "  138  (  BS_G,   D(16),	output2,    1,      138,      1,      Weak1 ), " &
 	     "  138  (  BS_G,   D(16),	input,      1				), " &
 	     "  137  (  BS_G,   D(17),	output2,    1,      137,      1,      Weak1 ), " &
 	     "  137  (  BS_G,   D(17),	input,      1				), " &
 	     "  136  (  BS_G,   D(18),	output2,    1,      136,      1,      Weak1 ), " &
 	     "  136  (  BS_G,   D(18),	input,      1				), " &
 	     "  135  (  BS_G,   D(19),	output2,    1,      135,      1,      Weak1 ), " &
 	     "  135  (  BS_G,   D(19),	input,      1				), " &
 	     "  134  (  BS_G,   D(20),	output2,    1,      134,      1,      Weak1 ), " &
 	     "  134  (  BS_G,   D(20),	input,      1				), " &
 	     "  133  (  BS_G,   D(21),	output2,    1,      133,      1,      Weak1 ), " &
 	     "  133  (  BS_G,   D(21),	input,      1				), " &
 	     "  132  (  BS_G,   D(22),	output2,    1,      132,      1,      Weak1 ), " &
 	     "  132  (  BS_G,   D(22),	input,      1				), " &
 	     "  131  (  BS_G,   D(23),	output2,    1,      131,      1,      Weak1 ), " &
 	     "  131  (  BS_G,   D(23),	input,      1				), " &
 	     "  130  (  BS_G,   DBI(1),	output2,    1,      130,      1,      Weak1 ), " &
 	     "  130  (  BS_G,   DBI(1),	input,      1				), " &
 	     "  129  (  BS_G,   DSTBP(1),	output2,    1,      129,      1,      Weak1 ), " &
 	     "  129  (  BS_G,   DSTBP(1),	input,      1				), " &
 	     "  128  (  BS_G,   DSTBN(1),	output2,    1,      128,      1,      Weak1 ), " &
 	     "  128  (  BS_G,   DSTBN(1),	input,      1				), " &
 	     "  127  (  BS_G,   D(24),	output2,    1,      127,      1,      Weak1 ), " &
 	     "  127  (  BS_G,   D(24),	input,      1				), " &
 	     "  126  (  BS_G,   D(25),	output2,    1,      126,      1,      Weak1 ), " &
 	     "  126  (  BS_G,   D(25),	input,      1				), " &
 	     "  125  (  BS_G,   D(26),	output2,    1,      125,      1,      Weak1 ), " &
 	     "  125  (  BS_G,   D(26),	input,      1				), " &
 	     "  124  (  BS_G,   D(27),	output2,    1,      124,      1,      Weak1 ), " &
 	     "  124  (  BS_G,   D(27),	input,      1				), " &
 	     "  123  (  BS_G,   D(28),	output2,    1,      123,      1,      Weak1 ), " &
 	     "  123  (  BS_G,   D(28),	input,      1				), " &
 	     "  122  (  BS_G,   D(29),	output2,    1,      122,      1,      Weak1 ), " &
 	     "  122  (  BS_G,   D(29),	input,      1				), " &
 	     "  121  (  BS_G,   D(30),	output2,    1,      121,      1,      Weak1 ), " &
 	     "  121  (  BS_G,   D(30),	input,      1				), " &
 	     "  120  (  BS_G,   D(31),	output2,    1,      120,      1,      Weak1 ), " &
 	     "  120  (  BS_G,   D(31),	input,      1				), " &
 	     "  119  (  BS_G,   DP(0),	output2,    1,      119,      1,      Weak1 ), " &
 	     "  119  (  BS_G,   DP(0),	input,      1				), " &
 	     "  118  (  BS_G,   DP(1),	output2,    1,      118,      1,      Weak1 ), " &
 	     "  118  (  BS_G,   DP(1),	input,      1				), " &
 	     "  117  (  BS_G,   DP(2),	output2,    1,      117,      1,      Weak1 ), " &
 	     "  117  (  BS_G,   DP(2),	input,      1				), " &
 	     "  116  (  BS_G,   DP(3),	output2,    1,      116,      1,      Weak1 ), " &
 	     "  116  (  BS_G,   DP(3),      	input,      1				), " &
 	     "  115  (  BS_G,   D(32),      	output2,    1,      115,      1,      Weak1 ), " &
 	     "  115  (  BS_G,   D(32),      	input,      1				), " &
 	     "  114  (  BS_G,   D(33),      	output2,    1,      114,      1,      Weak1 ), " &
 	     "  114  (  BS_G,   D(33),      	input,      1				), " &
 	     "  113  (  BS_G,   D(34),      	output2,    1,      113,      1,      Weak1 ), " &
 	     "  113  (  BS_G,   D(34),      	input,      1				), " &
 	     "  112  (  BS_G,   D(35),      	output2,    1,      112,      1,      Weak1 ), " &
 	     "  112  (  BS_G,   D(35),      	input,      1				), " &
 	     "  111  (  BS_G,   D(36),      	output2,    1,      111,      1,      Weak1 ), " &
 	     "  111  (  BS_G,   D(36),      	input,      1				), " &
 	     "  110  (  BS_G,   D(37),      	output2,    1,      110,      1,      Weak1 ), " &
 	     "  110  (  BS_G,   D(37),      	input,      1				), " &
 	     "  109  (  BS_G,   D(38),      	output2,    1,      109,      1,      Weak1 ), " &
 	     "  109  (  BS_G,   D(38),      	input,      1				), " &
 	     "  108  (  BS_G,   D(39),      	output2,    1,      108,      1,      Weak1 ), " &
 	     "  108  (  BS_G,   D(39),      	input,      1				), " &
 	     "  107  (  BS_G,   DBI(2),     	output2,    1,      107,      1,      Weak1 ), " &
 	     "  107  (  BS_G,   DBI(2),     	input,      1				), " &
 	     "  106  (  BS_G,   DSTBP(2),   	output2,    1,      106,      1,      Weak1 ), " &
 	     "  106  (  BS_G,   DSTBP(2),   	input,      1				), " &
 	     "  105  (  BS_G,   DSTBN(2),   output2,    1,      105,      1,      Weak1 ), " &
 	     "  105  (  BS_G,   DSTBN(2),   input,      1				), " &
 	     "  104  (  BS_G,   D(40),      	output2,    1,      104,      1,      Weak1 ), " &
 	     "  104  (  BS_G,   D(40),      	input,      1				), " &
 	     "  103  (  BS_G,   D(41),      	output2,    1,      103,      1,      Weak1 ), " &
 	     "  103  (  BS_G,   D(41),      	input,      1				), " &
 	     "  102  (  BS_G,   D(42),      	output2,    1,      102,      1,      Weak1 ), " &
 	     "  102  (  BS_G,   D(42),      	input,      1				        ), " &
 	     "  101  (  BS_G,   D(43),      	output2,    1,      101,      1,      Weak1 ), " &
 	     "  101  (  BS_G,   D(43),      	input,      1				        ), " &
 	     "  100  (  BS_G,   D(44),      	output2,    1,      100,      1,      Weak1 ), " &
 	     "  100  (  BS_G,   D(44),      	input,      1				        ), " &
 	     "   99  (  BS_G,   D(45),      	output2,    1,       99,      1,      Weak1 ), " &
 	     "   99  (  BS_G,   D(45),      	input,      1				        ), " &
 	     "   98  (  BS_G,   D(46),      	output2,    1,       98,      1,      Weak1 ), " &
 	     "   98  (  BS_G,   D(46),      	input,      1	           			  ), " &
 	     "   97  (  BS_G,   D(47),      	output2,    1,       97,      1,      Weak1 ), " &
 	     "   97  (  BS_G,   D(47),      	input,      1				        ), " &
 	     "   96  (  BS_G,   D(48),      	output2,    1,       96,      1,      Weak1 ), " &
 	     "   96  (  BS_G,   D(48),      	input,      1				        ), " &
 	     "   95  (  BS_G,   D(49),      	output2,    1,       95,      1,      Weak1 ), " &
 	     "   95  (  BS_G,   D(49),      	input,      1				        ), " &
 	     "   94  (  BS_G,   D(50),      	output2,    1,       94,      1,      Weak1 ), " &
 	     "   94  (  BS_G,   D(50),      	input,      1                               ), " &
 	     "   93  (  BS_G,   D(51),      	output2,    1,       93,      1,      Weak1 ), " &
 	     "   93  (  BS_G,   D(51),      	input,      1                               ), " &
 	     "   92  (  BS_G,   D(52),      	output2,    1,       92,      1,      Weak1 ), " &
 	     "   92  (  BS_G,   D(52),      	input,      1                               ), " &
 	     "   91  (  BS_G,   D(53),      	output2,    1,       91,      1,      Weak1 ), " &
 	     "   91  (  BS_G,   D(53),      	input,      1                               ), " &
 	     "   90  (  BS_G,   D(54),      	output2,    1,       90,      1,      Weak1 ), " &
 	     "   90  (  BS_G,   D(54),      	input,      1                               ), " &
 	     "   89  (  BS_G,   D(55),      	output2,    1,       89,      1,      Weak1 ), " &
 	     "   89  (  BS_G,   D(55),      	input,      1                               ), " &
 	     "   88  (  BS_G,   DBI(3),     	output2,    1,       88,      1,      Weak1 ), " &
 	     "   88  (  BS_G,   DBI(3),     	input,      1                               ), " &
 	     "   87  (  BS_G,   DSTBP(3),   	output2,    1,       87,      1,      Weak1 ), " &
 	     "   87  (  BS_G,   DSTBP(3),   	input,      1                               ), " &
 	     "   86  (  BS_G,   DSTBN(3),   	output2,    1,       86,      1,      Weak1 ), " &
 	     "   86  (  BS_G,   DSTBN(3),   	input,      1                               ), " &
 	     "   85  (  BS_G,   D(56),      	output2,    1,       85,      1,      Weak1 ), " &
 	     "   85  (  BS_G,   D(56),      	input,      1                               ), " &
 	     "   84  (  BS_G,   D(57),     	output2,    1,       84,      1,      Weak1 ), " &
 	     "   84  (  BS_G,   D(57),      	input,      1                               ), " &
 	     "   83  (  BS_G,   D(58),      	output2,    1,       83,      1,      Weak1 ), " &
 	     "   83  (  BS_G,   D(58),      	input,      1                               ), " &
 	     "   82  (  BS_G,   D(59),      	output2,    1,       82,      1,      Weak1 ), " &
 	     "   82  (  BS_G,   D(59),      	input,      1                               ), " &
 	     "   81  (  BS_G,   D(60),      	output2,    1,       81,      1,      Weak1 ), " &
 	     "   81  (  BS_G,   D(60),      	input,      1                               ), " &
 	     "   80  (  BS_G,   D(61),      	output2,    1,       80,      1,      Weak1 ), " &
 	     "   80  (  BS_G,   D(61),      	input,      1                               ), " &
 	     "   79  (  BS_G,   D(62),      	output2,    1,       79,      1,      Weak1 ), " &
 	     "   79  (  BS_G,   D(62),      	input,      1                               ), " &
 	     "   78  (  BS_G,   D(63),      	output2,    1,       78,      1,      Weak1 ), " &
 	     "   78  (  BS_G,   D(63),      	input,      1                               ), " &
	     "   77  (  BS_G,   RESET,      	input,      1                               ), " &
	     "   76  (  BS_G,   SLP,        	input,      1                               ), " &
	     "   75  (  BS_G,   PWRGOOD,  input,      1                               ), " &
 	     "   74  (  BS_G,   BCLK(1),	output2,    1,       74,      1,      Weak1 ), " &
	     "   74  (  BS_G,   BCLK(1),    	input,      1                               ), " &
  	     "   73  (  BS_G,   BCLK(0),    	output2,    1,       73,      1,      Weak1 ), " &
	     "   73  (  BS_G,   BCLK(0),    	input,      1                               ), " &
	     "   72  (  BS_G,   BPM(0),     	output2,    1,       72,      1,      Weak1 ), " &
 	     "   72  (  BS_G,   BPM(0),     	input,      1                               ), " &
 	     "   71  (  BS_G,   BPM(1),     	output2,    1,       71,      1,      Weak1 ), " &
 	     "   71  (  BS_G,   BPM(1),     	input,      1                               ), " &
 	     "   70  (  BS_G,   BPM(2),     	output2,    1,       70,      1,      Weak1 ), " &
 	     "   70  (  BS_G,   BPM(2),     	input,      1                               ), " &
 	     "   69  (  BS_G,   BPM(3),     	output2,    1,       69,      1,      Weak1 ), " &
 	     "   69  (  BS_G,   BPM(3),     	input,      1                               ), " &
 	     "   68  (  BS_G,   BPM(4),     	output2,    1,       68,      1,      Weak1 ), " &
 	     "   68  (  BS_G,   BPM(4),     	input,      1                               ), " &
 	     "   67  (  BS_G,   BPM(5),     	output2,    1,       67,      1,      Weak1 ), " &
 	     "   67  (  BS_G,   BPM(5),     	input,      1                               ), " &
 	     "   66  (  BC_2,   IERR,       	output2,    1,       66,      1,      Weak1 ), " &
 	     "   65  (  BS_4,   STPCLK,     	input,      X                               ), " &
 	     "   64  (  BS_4,   INIT,	input,      X                               ), " &
 	     "   63  (  BS_G,   MCERR,      	output2,    1,       63,      1,      Weak1 ), " &
 	     "   63  (  BS_G,   MCERR,      	input,      1                               ), " &
 	     "   62  (  BS_G,   BINIT,      	output2,    1,       62,      1,      Weak1 ), " &
 	     "   62  (  BS_G,   BINIT,      	input,      1                               ), " &
 	     "   61  (  BS_4,   RSP,        	input,      X                               ), " &
 	     "   60  (  BS_G,   AP(0),      	output2,    1,       60,      1,      Weak1 ), " &
 	     "   60  (  BS_G,   AP(0),      	input,      1                               ), " &
 	     "   59  (  BS_G,   AP(1),      	output2,    1,       59,      1,      Weak1 ), " &
 	     "   59  (  BS_G,   AP(1),      	input,      1                               ), " &
 	     "   58  (  BS_4,   BR3,        	input,      X                               ), " &
 	     "   57  (  BS_4,   BR2,        	input,      X                               ), " &
 	     "   56  (  BS_4,   BR1,        	input,      X                               ), " &
 	     "   55  (  BS_G,   A(35),      	output2,    1,       55,      1,      Weak1 ), " &
 	     "   55  (  BS_G,   A(35),      	input,      1                               ), " &
 	     "   54  (  BS_G,   A(34),      	output2,    1,       54,      1,      Weak1 ), " &
 	     "   54  (  BS_G,   A(34),      	input,      1                               ), " &
 	     "   53  (  BS_G,   A(33),      	output2,    1,       53,      1,      Weak1 ), " &
 	     "   53  (  BS_G,   A(33),      	input,      1                               ), " &
 	     "   52  (  BS_G,   A(32),      	output2,    1,       52,      1,      Weak1 ), " &
 	     "   52  (  BS_G,   A(32),      	input,      1                               ), " &
 	     "   51  (  BS_G,   A(31),      	output2,    1,       51,      1,      Weak1 ), " &
 	     "   51  (  BS_G,   A(31),      	input,      1                               ), " &
 	     "   50  (  BS_G,   A(30),      	output2,    1,       50,      1,      Weak1 ), " &
 	     "   50  (  BS_G,   A(30),      	input,      1                               ), " &
 	     "   49  (  BS_G,   A(29),      	output2,    1,       49,      1,      Weak1 ), " &
 	     "   49  (  BS_G,   A(29),      	input,      1                               ), " &
 	     "   48  (  BS_G,   A(28),      	output2,    1,       48,      1,      Weak1 ), " &
 	     "   48  (  BS_G,   A(28),      	input,      1                               ), " &
 	     "   47  (  BS_G,   A(27),      	output2,    1,       47,      1,      Weak1 ), " &
 	     "   47  (  BS_G,   A(27),      	input,      1                               ), " &
 	     "   46  (  BS_G,   ADSTB(1),   output2,    1,       46,      1,      Weak1 ), " &
 	     "   46  (  BS_G,   ADSTB(1),   input,      1                               ), " &
 	     "   45  (  BS_G,   A(26),      	output2,    1,       45,      1,      Weak1 ), " &
 	     "   45  (  BS_G,   A(26),      	input,      1                               ), " &
 	     "   44  (  BS_G,   A(25),      	output2,    1,       44,      1,      Weak1 ), " &
 	     "   44  (  BS_G,   A(25),      	input,      1                               ), " &
 	     "   43  (  BS_G,   A(24),      	output2,    1,       43,      1,      Weak1 ), " &
 	     "   43  (  BS_G,   A(24),      	input,      1                               ), " &
 	     "   42  (  BS_G,   A(23),      	output2,    1,       42,      1,      Weak1 ), " &
 	     "   42  (  BS_G,   A(23),      	input,      1                               ), " &
 	     "   41  (  BS_G,   A(22),      	output2,    1,       41,      1,      Weak1 ), " &
 	     "   41  (  BS_G,   A(22),      	input,      1                               ), " &
 	     "   40  (  BS_G,   A(21),      	output2,    1,       40,      1,      Weak1 ), " &
 	     "   40  (  BS_G,   A(21),      	input,      1                               ), " &
 	     "   39  (  BS_G,   A(20),      	output2,    1,       39,      1,      Weak1 ), " &
 	     "   39  (  BS_G,   A(20),      	input,      1                               ), " &
 	     "   38  (  BS_G,   A(19),      	output2,    1,       38,      1,      Weak1 ), " &
 	     "   38  (  BS_G,   A(19),      	input,      1                               ), " &
 	     "   37  (  BS_G,   A(18),      	output2,    1,       37,      1,      Weak1 ), " &
 	     "   37  (  BS_G,   A(18),      	input,      1                               ), " &
 	     "   36  (  BS_G,   A(17),      	output2,    1,       36,      1,      Weak1 ), " &
 	     "   36  (  BS_G,   A(17),      	input,      1                               ), " &
 	     "   35  (  BS_G,   A(16),      	output2,    1,       35,      1,      Weak1 ), " &
 	     "   35  (  BS_G,   A(16),      	input,      1                               ), " &
 	     "   34  (  BS_G,   A(15),      	output2,    1,       34,      1,      Weak1 ), " &
 	     "   34  (  BS_G,   A(15),      	input,      1                               ), " &
 	     "   33  (  BS_G,   A(14),      	output2,    1,       33,      1,      Weak1 ), " &
 	     "   33  (  BS_G,   A(14),      	input,      1                               ), " &
 	     "   32  (  BS_G,   A(13),      	output2,    1,       32,      1,      Weak1 ), " &
 	     "   32  (  BS_G,   A(13),      	input,      1                               ), " &
 	     "   31  (  BS_G,   A(12),      	output2,    1,       31,      1,      Weak1 ), " &
 	     "   31  (  BS_G,   A(12),      	input,      1                               ), " &
 	     "   30  (  BS_G,   A(11),      	output2,    1,       30,      1,      Weak1 ), " &
 	     "   30  (  BS_G,   A(11),      	input,      1                               ), " &
 	     "   29  (  BS_G,   A(10),      	output2,    1,       29,      1,      Weak1 ), " &
 	     "   29  (  BS_G,   A(10),      	input,      1                               ), " &
 	     "   28  (  BS_G,   A(9),       	output2,    1,       28,      1,      Weak1 ), " &
 	     "   28  (  BS_G,   A(9),       	input,      1                               ), " &
 	     "   27  (  BS_G,   A(8),       	output2,    1,       27,      1,      Weak1 ), " &
 	     "   27  (  BS_G,   A(8),       	input,      1                               ), " &
 	     "   26  (  BS_G,   ADSTB(0),   	output2,    1,       26,      1,      Weak1 ), " &
 	     "   26  (  BS_G,   ADSTB(0),   	input,      1                               ), " &
 	     "   25  (  BS_G,   A(7),       output2,    1,       25,      1,      Weak1 ), " &
 	     "   25  (  BS_G,   A(7),       input,      1                               ), " &
 	     "   24  (  BS_G,   A(6),       output2,    1,       24,      1,      Weak1 ), " &
 	     "   24  (  BS_G,   A(6),       input,      1                               ), " &
 	     "   23  (  BS_G,   A(5),       output2,    1,       23,      1,      Weak1 ), " &
 	     "   23  (  BS_G,   A(5),       input,      1                               ), " &
 	     "   22  (  BS_G,   A(4),       output2,    1,       22,      1,      Weak1 ), " &
 	     "   22  (  BS_G,   A(4),       input,      1                               ), " &
 	     "   21  (  BS_G,   A(3),       output2,    1,       21,      1,      Weak1 ), " &
 	     "   21  (  BS_G,   A(3),       input,      1                               ), " &
 	     "   20  (  BS_G,   REQ(0),     output2,    1,       20,      1,      Weak1 ), " &
 	     "   20  (  BS_G,   REQ(0),     input,      1                               ), " &
 	     "   19  (  BS_G,   REQ(1),     output2,    1,       19,      1,      Weak1 ), " &
 	     "   19  (  BS_G,   REQ(1),     input,      1                               ), " &
 	     "   18  (  BS_G,   REQ(2),     output2,    1,       18,      1,      Weak1 ), " &
 	     "   18  (  BS_G,   REQ(2),     input,      1                               ), " &
 	     "   17  (  BS_G,   REQ(3),     output2,    1,       17,      1,      Weak1 ), " &
 	     "   17  (  BS_G,   REQ(3),     input,      1                               ), " &
 	     "   16  (  BS_G,   REQ(4),     output2,    1,       16,      1,      Weak1 ), " &
 	     "   16  (  BS_G,   REQ(4),     input,      1                               ), " &
 	     "   15  (  BS_G,   DRDY,       output2,    1,       15,      1,      Weak1 ), " &
 	     "   15  (  BS_G,   DRDY,       input,      1                               ), " &
 	     "   14  (  BS_G,   DBSY,       output2,    1,       14,      1,      Weak1 ), " &
 	     "   14  (  BS_G,   DBSY,       input,      1                               ), " &
 	     "   13  (  BS_4,   TRDY,       input,      X                               ), " &
 	     "   12  (  BS_G,   BNR,        output2,    1,       12,      1,      Weak1 ), " &
 	     "   12  (  BS_G,   BNR,        input,      1                               ), " &
 	     "   11  (  BS_G,   ADS,        output2,    1,       11,      1,      Weak1 ), " &
 	     "   11  (  BS_G,   ADS,        input,      1                               ), " &
 	     "   10  (  BS_G,   BR0,        output2,    1,       10,      1,      Weak1 ), " &
 	     "   10  (  BS_G,   BR0,        input,      1                               ), " &
 	     "    9  (  BS_G,   LOCK,       output2,    1,        9,      1,      Weak1 ), " &
 	     "    9  (  BS_G,   LOCK,       input,      1                               ), " &
 	     "    8  (  BS_4,   RS(0),      input,      X                               ), " &
 	     "    7  (  BS_4,   RS(1),      input,      X                               ), " &
 	     "    6  (  BS_4,   RS(2),      input,      X                               ), " &
 	     "    5  (  BS_G,   HIT,        output2,    1,        5,      1,      Weak1 ), " &
 	     "    5  (  BS_G,   HIT,        input,      1                               ), " &
 	     "    4  (  BS_G,   HITM,       output2,    1,        4,      1,      Weak1 ), " &
 	     "    4  (  BS_G,   HITM,       input,      1                               ), " &
 	     "    3  (  BS_4,   DEFER,      input,      X                               ), " &
 	     "    2  (  BS_4,   BPRI,       input,      X                               ), " &
 	     "    1  (  BS_4,   LINT0,      input,      X                               ), " &
 	     "    0  (  BS_4,   LINT1,      input,      X                               ) " ;

end FSTR_0;

This library contains 7815 BSDL files (for 6182 distinct entities) from 66 vendors
Last BSDL model (PIC24FJ64GA002) was added on Nov 10, 2017 08:41
info@bsdl.info