--------------------------------------------------------------------------- -- This model was created at IDT's SYDNEY DESIGN CENTER -- Part: IDT72V253BC (SSII+ 4096 words x 18bits) -- Ver: 0.0 Created by: DSG Date: 4/3/02 -- Ver: 1.0 Created by: DJR Date: 27th June 2002 -- Ver: 2.0 Corrected by: DJR Date: 9th March 2004 -- Ver: 3.0 Corrected by: DJR Date: 8th March 2005 -- Customization created on: Tue Dec 13 10:11:18 2005 --------------------------------------------------------------------------- entity IDT72V253BC is -- Generic parameter generic (PHYSICAL_PIN_MAP: string := "BC100"); -- Logical port description port ( D : in bit_vector(0 to 17); IW : in bit; SENB : in bit; WENB : in bit; WCLK : in bit; PRSB : in bit; MRSB : in bit; RM : in bit; ASYRB : in bit; ASYWB : in bit; LDB : in bit; FWFTSI : in bit; FF : buffer bit; PAF : buffer bit; OW : in bit; FSEL : in bit_vector(0 to 1); HF : buffer bit; BEB : in bit; IP : in bit; PAE : buffer bit; PFM : in bit; EF : buffer bit; RCLK : in bit; RENB : in bit; RTB : in bit; OEB : in bit; Q : buffer bit_vector(0 to 17); TCK : in bit; TMS : in bit; TDI : in bit; TRSTB : in bit; TDO : out bit; GND : linkage bit_vector(0 to 15); VCC : linkage bit_vector(0 to 16) ); -- Standard use STD_1149_1_1994.all; -- Component conformance attribute COMPONENT_CONFORMANCE of IDT72V253BC: entity is "STD_1149_1_1993"; -- Device package pin mappings attribute PIN_MAP of IDT72V253BC: entity is PHYSICAL_PIN_MAP; -- Pin-port map for package BC100 constant BC100: PIN_MAP_STRING := "D : (J4, K4, J3, K3, K2, K1, J1, J2, H1, " & "H2, H3, G1, G2, F1, F2, E2, E1, D1), " & "IW : D2, " & "SENB : C2, " & "WENB : B1, " & "WCLK : A1, " & "PRSB : A2, " & "MRSB : B2, " & "RM : A9, " & "ASYRB : A7, " & "ASYWB : C1, " & "LDB : A3, " & "FWFTSI : B3, " & "FF : C3, " & "PAF : A4, " & "OW : B4, " & "FSEL : (A5, B6), " & "HF : B5, " & "BEB : A6, " & "IP : B7, " & "PAE : B8, " & "PFM : A8, " & "EF : B9, " & "RCLK : B10, " & "RENB : A10, " & "RTB : C9, " & "OEB : C10, " & "Q : (K7, H8, J8, K8, J9, K9, K10, J10, H10, " & "H9, G10, G9, F10, F9, E9, E10, D9, D10), " & "TCK : J6, " & "TMS : J5, " & "TDI : K6, " & "TRSTB : K5, " & "TDO : J7, " & "GND : (D4, D5, D6, D7, E4, E5, E6, E7, " & "F4, F5, F6, F7, G4, G5, G6, G7), " & "VCC : (C4, C5, C6, C7, C8, D3, D8, E3, E8, " & "F3, F8, G3, G8, H4, H5, H6, H7) "; -- Scan port identification attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, LOW); attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_RESET of TRSTB : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; -- Compliance patterns attribute COMPLIANCE_PATTERNS of IDT72V253BC: entity is "(OEB, IW, OW) (000)"; -- Instruction register description attribute INSTRUCTION_LENGTH of IDT72V253BC: entity is 4; attribute INSTRUCTION_OPCODE of IDT72V253BC: entity is "EXTEST (0000)," & "SAMPLE (0001)," & "IDCODE (0010)," & "HIGHZ (0011)," & "BYPASS (1111)," & "PRIVATE (0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110)"; attribute INSTRUCTION_CAPTURE of IDT72V253BC: entity is "1101"; attribute INSTRUCTION_PRIVATE of IDT72V253BC: entity is "PRIVATE"; -- Optional register description attribute IDCODE_REGISTER of IDT72V253BC: entity is "0001" & -- version "0000010011101100" & -- part number "00000110011" & -- manufacturer's identity "1"; -- required by 1149.1 -- Register access description attribute REGISTER_ACCESS of IDT72V253BC: entity is "BYPASS (BYPASS, HIGHZ), " & "BOUNDARY (SAMPLE, EXTEST), " & "DEVICE_ID (IDCODE)"; -- Boundary-Scan register description attribute BOUNDARY_LENGTH of IDT72V253BC: entity is 62; attribute BOUNDARY_REGISTER of IDT72V253BC: entity is -- -- num cell port function safe [ccell disval rslt] -- "0 (BC_1, Q(0), output2, X), " & "1 (BC_1, Q(1), output2, X), " & "2 (BC_1, Q(2), output2, X), " & "3 (BC_1, Q(3), output2, X), " & "4 (BC_1, Q(4), output2, X), " & "5 (BC_1, Q(5), output2, X), " & "6 (BC_1, Q(6), output2, X), " & "7 (BC_1, Q(7), output2, X), " & "8 (BC_1, Q(8), output2, X), " & "9 (BC_1, Q(9), output2, X), " & "10 (BC_1, Q(10), output2, X), " & "11 (BC_1, Q(11), output2, X), " & "12 (BC_1, Q(12), output2, X), " & "13 (BC_1, Q(13), output2, X), " & "14 (BC_1, Q(14), output2, X), " & "15 (BC_1, Q(15), output2, X), " & "16 (BC_1, Q(16), output2, X), " & "17 (BC_1, Q(17), output2, X), " & -- "18 (BC_4, OEB, input, X), " & "18 (BC_4, *, internal, X), " & "19 (BC_4, RTB, input, X), " & "20 (BC_4, RENB, input, X), " & "21 (BC_4, RCLK, clock, X), " & "22 (BC_4, RM, input, X), " & "23 (BC_1, EF, output2, X), " & "24 (BC_4, PFM, input, X), " & "25 (BC_1, PAE, output2, X), " & "26 (BC_4, ASYRB, input, X), " & "27 (BC_4, IP, input, X), " & "28 (BC_4, BEB, input, X), " & "29 (BC_4, FSEL(1), input, X), " & "30 (BC_1, HF, output2, X), " & "31 (BC_4, FSEL(0), input, X), " & -- "32 (BC_4, OW, input, X), " & "32 (BC_4, *, internal, X), " & "33 (BC_1, PAF, output2, X), " & "34 (BC_1, FF, output2, X), " & "35 (BC_4, FWFTSI, input, X), " & "36 (BC_4, LDB, input, X), " & "37 (BC_4, MRSB, input, X), " & "38 (BC_4, PRSB, input, X), " & "39 (BC_4, WCLK, clock, X), " & "40 (BC_4, WENB, input, X), " & "41 (BC_4, ASYWB, input, X), " & "42 (BC_4, SENB, input, X), " & -- "43 (BC_4, IW, input, X), " & "43 (BC_4, *, internal, X), " & "44 (BC_4, D(17), input, X), " & "45 (BC_4, D(16), input, X), " & "46 (BC_4, D(15), input, X), " & "47 (BC_4, D(14), input, X), " & "48 (BC_4, D(13), input, X), " & "49 (BC_4, D(12), input, X), " & "50 (BC_4, D(11), input, X), " & "51 (BC_4, D(10), input, X), " & "52 (BC_4, D(9), input, X), " & "53 (BC_4, D(8), input, X), " & "54 (BC_4, D(7), input, X), " & "55 (BC_4, D(6), input, X), " & "56 (BC_4, D(5), input, X), " & "57 (BC_4, D(4), input, X), " & "58 (BC_4, D(3), input, X), " & "59 (BC_4, D(2), input, X), " & "60 (BC_4, D(1), input, X), " & "61 (BC_4, D(0), input, X)"; end IDT72V253BC;