--$ XILINX$RCSfile: xcr5128_vq100.bsd,v $
--$ XILINX$Revision: 1.1 $
--
-- BSDL file for device XCR5128, package VQ100
-- Xilinx, Inc. $State: ADVANCED $ $Date: 2000-07-27 10:02:08-07 $
-- Generated by
--
-- For technical support, contact Xilinx at
--
-- http://support.xilinx.com
--
-- or as follow:
-- North America 1-800-255-7778 hotline@xilinx.com
-- United Kingdom (44) 1932 820821 ukhelp@xilinx.com
-- France (33) 1 3463 0100 frhelp@xilinx.com
-- Germany (49) 89 991 54930 dlhelp@xilinx.com
-- Japan (81) 3-3297-9163 jhotline@xilinx.com
--
entity XCR5128_VQ100 is
generic (PHYSICAL_PIN_MAP : string := "xcr5128p");
port (din : in bit_vector (0 to 3); -- Tim pin type IN
TDI : in bit; -- Tim pin type TDI
TMS : in bit; -- Tim pin type TMS
TCK : in bit; -- Tim pin type TCK
TDO : out bit; -- Tim pin type TDO
ioA : inout bit_vector (0 to 9); -- Tim pin type IOO
ioB : inout bit_vector (0 to 8); -- Tim pin type IOO
ioC : inout bit_vector (0 to 8); -- Tim pin type IOO
ioD : inout bit_vector (0 to 9); -- Tim pin type IOO
ioE : inout bit_vector (0 to 9); -- Tim pin type IOO
ioF : inout bit_vector (0 to 8); -- Tim pin type IOO
ioG : inout bit_vector (0 to 8); -- Tim pin type IOO
ioH : inout bit_vector (0 to 9); -- Tim pin type IOO
Vcc : linkage bit_vector (1 to 8);
Gnd : linkage bit_vector (1 to 8)
);
use STD_1149_1_1994.ALL;
attribute COMPONENT_CONFORMANCE of XCR5128_VQ100 : entity is
"std_1149_1_1993";
attribute PIN_MAP of XCR5128_VQ100 : entity is PHYSICAL_PIN_MAP;
constant xcr5128p : PIN_MAP_STRING :=
"din : ( 87, 89, 88, 90)," &
"TDI : 4," &
"TMS : 15," &
"TCK : 62," &
"TDO : 73," &
"ioA : ( 2, 1, 100, 99, 98, 97, 96, 94, 93, 92), " &
"ioB : ( 14, 13, 12, 10, 9, 8, 7, 6, 5), " &
"ioC : ( 25, 24, 23, 22, 21, 20, 19, 17, 16), " &
"ioD : ( 37, 36, 35, 33, 32, 31, 30, 29, 28, 27), " &
"ioE : ( 40, 41, 42, 44, 45, 46, 47, 48, 49, 50), " &
"ioF : ( 52, 53, 54, 55, 56, 57, 58, 60, 61), " &
"ioG : ( 63, 64, 65, 67, 68, 69, 70, 71, 72), " &
"ioH : ( 75, 76, 77, 78, 79, 80, 81, 83, 84, 85), " &
"Vcc : ( 3, 18, 34, 39, 51, 66, 82, 91), " &
"Gnd : ( 11, 26, 38, 43, 59, 74, 86, 95) ";
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, both);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
-- Instruction Register Definitions
attribute INSTRUCTION_LENGTH of XCR5128_VQ100 : entity is 4;
attribute INSTRUCTION_OPCODE of XCR5128_VQ100 : entity is
"EXTEST (0000)," &
"IDCODE (0001)," &
"SAMPLE (0010)," &
"STCTEST (0100)," &
"HIGHZ (0101)," &
"BYPASS (1111)," &
"ENABLEOTF (1000)," &
"ENABLE (1001)," &
"ERASE (1010)," &
"PROGRAM (1011)," &
"VERIFY (1100)," &
"INIT (1101)";
attribute INSTRUCTION_CAPTURE of XCR5128_VQ100 : entity is "0001";
attribute IDCODE_REGISTER of XCR5128_VQ100 : entity is
"XXXX" & -- Version
"000" & -- Architecture
"000" & -- Technology
"001000" & -- Part number
"0" & -- Voltage
"100" & -- Package
"00000010101" & -- Manufacturer
"1"; -- mandatory
attribute REGISTER_ACCESS of XCR5128_VQ100 : entity is
"BOUNDARY (EXTEST)," &
"DEVICE_ID (IDCODE)," &
"BOUNDARY (SAMPLE)," &
"STC[280] (STCTEST CAPTURES 00010000000010000100000000101011" &
"00000000000000000000000000000000000000000000000000000000000000000" &
"00000000000000000000000000000000000000000000000000000000000000000" &
"00000000000000000000000000000000000000000000000000000000000000000" &
"00000000000000000000000000000000000000000000000000000)," &
"BYPASS (HIGHZ)," &
"BYPASS (BYPASS)," &
"DATAREG[5] (ENABLEOTF)," &
"DATAREG[5] (ENABLE)," &
"DATAREG[5] (ERASE)," &
"DATAREG[5] (PROGRAM)," &
"DATAREG[5] (VERIFY)," &
"BYPASS (INIT)";
attribute BOUNDARY_LENGTH of XCR5128_VQ100 : entity is 280;
attribute BOUNDARY_REGISTER of XCR5128_VQ100 : entity is
--
-- num cell port function safe [ccell disval rslt]
--
"279 (BC_1, ioB(0), OUTPUT3, X, 278, 0, Z)," &
"278 (BC_1, *, CONTROL, 0)," &
"277 (BC_1, ioB(1), OUTPUT3, X, 276, 0, Z)," &
"276 (BC_1, *, CONTROL, 0)," &
"275 (BC_1, ioB(2), OUTPUT3, X, 274, 0, Z)," &
"274 (BC_1, *, CONTROL, 0)," &
"273 (BC_1, ioB(3), OUTPUT3, X, 272, 0, Z)," &
"272 (BC_1, *, CONTROL, 0)," &
"271 (BC_4, *, internal, X)," &
"270 (BC_4, *, internal, X)," &
"269 (BC_1, ioB(4), OUTPUT3, X, 268, 0, Z)," &
"268 (BC_1, *, CONTROL, 0)," &
"267 (BC_0, ioB(0), INPUT, X)," &
"266 (BC_0, ioB(1), INPUT, X)," &
"265 (BC_0, ioB(2), INPUT, X)," &
"264 (BC_0, ioB(3), INPUT, X)," &
"263 (BC_4, *, internal, X)," &
"262 (BC_0, ioB(4), INPUT, X)," &
"261 (BC_0, ioB(5), INPUT, X)," &
"260 (BC_0, ioB(6), INPUT, X)," &
"259 (BC_0, ioB(7), INPUT, X)," &
"258 (BC_0, ioB(8), INPUT, X)," &
"257 (BC_4, *, internal, X)," &
"256 (BC_1, ioB(5), OUTPUT3, X, 255, 0, Z)," &
"255 (BC_1, *, CONTROL, 0)," &
"254 (BC_1, ioB(6), OUTPUT3, X, 253, 0, Z)," &
"253 (BC_1, *, CONTROL, 0)," &
"252 (BC_1, ioB(7), OUTPUT3, X, 251, 0, Z)," &
"251 (BC_1, *, CONTROL, 0)," &
"250 (BC_1, ioB(8), OUTPUT3, X, 249, 0, Z)," &
"249 (BC_1, *, CONTROL, 0)," &
"248 (BC_4, *, internal, X)," &
"247 (BC_4, *, internal, X)," &
"246 (BC_1, *, CONTROL, 0)," &
"245 (BC_1, ioA(9), OUTPUT3, X, 246, 0, Z)," &
"244 (BC_4, *, internal, X)," &
"243 (BC_4, *, internal, X)," &
"242 (BC_1, *, CONTROL, 0)," &
"241 (BC_1, ioA(8), OUTPUT3, X, 242, 0, Z)," &
"240 (BC_1, *, CONTROL, 0)," &
"239 (BC_1, ioA(7), OUTPUT3, X, 240, 0, Z)," &
"238 (BC_1, *, CONTROL, 0)," &
"237 (BC_1, ioA(6), OUTPUT3, X, 238, 0, Z)," &
"236 (BC_1, *, CONTROL, 0)," &
"235 (BC_1, ioA(5), OUTPUT3, X, 236, 0, Z)," &
"234 (BC_0, ioA(9), INPUT, X)," &
"233 (BC_4, *, internal, X)," &
"232 (BC_0, ioA(8), INPUT, X)," &
"231 (BC_0, ioA(7), INPUT, X)," &
"230 (BC_0, ioA(6), INPUT, X)," &
"229 (BC_0, ioA(5), INPUT, X)," &
"228 (BC_0, ioA(4), INPUT, X)," &
"227 (BC_4, *, internal, X)," &
"226 (BC_0, ioA(3), INPUT, X)," &
"225 (BC_0, ioA(2), INPUT, X)," &
"224 (BC_0, ioA(1), INPUT, X)," &
"223 (BC_0, ioA(0), INPUT, X)," &
"222 (BC_1, *, CONTROL, 0)," &
"221 (BC_1, ioA(4), OUTPUT3, X, 222, 0, Z)," &
"220 (BC_4, *, internal, X)," &
"219 (BC_4, *, internal, X)," &
"218 (BC_1, *, CONTROL, 0)," &
"217 (BC_1, ioA(3), OUTPUT3, X, 218, 0, Z)," &
"216 (BC_1, *, CONTROL, 0)," &
"215 (BC_1, ioA(2), OUTPUT3, X, 216, 0, Z)," &
"214 (BC_1, *, CONTROL, 0)," &
"213 (BC_1, ioA(1), OUTPUT3, X, 214, 0, Z)," &
"212 (BC_1, *, CONTROL, 0)," &
"211 (BC_1, ioA(0), OUTPUT3, X, 212, 0, Z)," &
"210 (BC_1, ioC(0), OUTPUT3, X, 209, 0, Z)," &
"209 (BC_1, *, CONTROL, 0)," &
"208 (BC_1, ioC(1), OUTPUT3, X, 207, 0, Z)," &
"207 (BC_1, *, CONTROL, 0)," &
"206 (BC_1, ioC(2), OUTPUT3, X, 205, 0, Z)," &
"205 (BC_1, *, CONTROL, 0)," &
"204 (BC_1, ioC(3), OUTPUT3, X, 203, 0, Z)," &
"203 (BC_1, *, CONTROL, 0)," &
"202 (BC_4, *, internal, X)," &
"201 (BC_4, *, internal, X)," &
"200 (BC_1, ioC(4), OUTPUT3, X, 199, 0, Z)," &
"199 (BC_1, *, CONTROL, 0)," &
"198 (BC_0, ioC(0), INPUT, X)," &
"197 (BC_0, ioC(1), INPUT, X)," &
"196 (BC_0, ioC(2), INPUT, X)," &
"195 (BC_0, ioC(3), INPUT, X)," &
"194 (BC_4, *, internal, X)," &
"193 (BC_0, ioC(4), INPUT, X)," &
"192 (BC_0, ioC(5), INPUT, X)," &
"191 (BC_0, ioC(6), INPUT, X)," &
"190 (BC_0, ioC(7), INPUT, X)," &
"189 (BC_0, ioC(8), INPUT, X)," &
"188 (BC_4, *, internal, X)," &
"187 (BC_1, ioC(5), OUTPUT3, X, 186, 0, Z)," &
"186 (BC_1, *, CONTROL, 0)," &
"185 (BC_1, ioC(6), OUTPUT3, X, 184, 0, Z)," &
"184 (BC_1, *, CONTROL, 0)," &
"183 (BC_1, ioC(7), OUTPUT3, X, 182, 0, Z)," &
"182 (BC_1, *, CONTROL, 0)," &
"181 (BC_1, ioC(8), OUTPUT3, X, 180, 0, Z)," &
"180 (BC_1, *, CONTROL, 0)," &
"179 (BC_4, *, internal, X)," &
"178 (BC_4, *, internal, X)," &
"177 (BC_1, *, CONTROL, 0)," &
"176 (BC_1, ioD(9), OUTPUT3, X, 177, 0, Z)," &
"175 (BC_4, *, internal, X)," &
"174 (BC_4, *, internal, X)," &
"173 (BC_1, *, CONTROL, 0)," &
"172 (BC_1, ioD(8), OUTPUT3, X, 173, 0, Z)," &
"171 (BC_1, *, CONTROL, 0)," &
"170 (BC_1, ioD(7), OUTPUT3, X, 171, 0, Z)," &
"169 (BC_1, *, CONTROL, 0)," &
"168 (BC_1, ioD(6), OUTPUT3, X, 169, 0, Z)," &
"167 (BC_1, *, CONTROL, 0)," &
"166 (BC_1, ioD(5), OUTPUT3, X, 167, 0, Z)," &
"165 (BC_0, ioD(9), INPUT, X)," &
"164 (BC_4, *, internal, X)," &
"163 (BC_0, ioD(8), INPUT, X)," &
"162 (BC_0, ioD(7), INPUT, X)," &
"161 (BC_0, ioD(6), INPUT, X)," &
"160 (BC_0, ioD(5), INPUT, X)," &
"159 (BC_0, ioD(4), INPUT, X)," &
"158 (BC_4, *, internal, X)," &
"157 (BC_0, ioD(3), INPUT, X)," &
"156 (BC_0, ioD(2), INPUT, X)," &
"155 (BC_0, ioD(1), INPUT, X)," &
"154 (BC_0, ioD(0), INPUT, X)," &
"153 (BC_0, din(3), INPUT, X)," &
"152 (BC_0, din(1), INPUT, X)," &
"151 (BC_1, *, CONTROL, 0)," &
"150 (BC_1, ioD(4), OUTPUT3, X, 151, 0, Z)," &
"149 (BC_4, *, internal, X)," &
"148 (BC_4, *, internal, X)," &
"147 (BC_1, *, CONTROL, 0)," &
"146 (BC_1, ioD(3), OUTPUT3, X, 147, 0, Z)," &
"145 (BC_1, *, CONTROL, 0)," &
"144 (BC_1, ioD(2), OUTPUT3, X, 145, 0, Z)," &
"143 (BC_1, *, CONTROL, 0)," &
"142 (BC_1, ioD(1), OUTPUT3, X, 143, 0, Z)," &
"141 (BC_1, *, CONTROL, 0)," &
"140 (BC_1, ioD(0), OUTPUT3, X, 141, 0, Z)," &
"139 (BC_1, ioH(0), OUTPUT3, X, 138, 0, Z)," &
"138 (BC_1, *, CONTROL, 0)," &
"137 (BC_1, ioH(1), OUTPUT3, X, 136, 0, Z)," &
"136 (BC_1, *, CONTROL, 0)," &
"135 (BC_1, ioH(2), OUTPUT3, X, 134, 0, Z)," &
"134 (BC_1, *, CONTROL, 0)," &
"133 (BC_1, ioH(3), OUTPUT3, X, 132, 0, Z)," &
"132 (BC_1, *, CONTROL, 0)," &
"131 (BC_4, *, internal, X)," &
"130 (BC_4, *, internal, X)," &
"129 (BC_1, ioH(4), OUTPUT3, X, 128, 0, Z)," &
"128 (BC_1, *, CONTROL, 0)," &
"127 (BC_0, din(0), INPUT, X)," &
"126 (BC_0, din(2), INPUT, X)," &
"125 (BC_0, ioH(0), INPUT, X)," &
"124 (BC_0, ioH(1), INPUT, X)," &
"123 (BC_0, ioH(2), INPUT, X)," &
"122 (BC_0, ioH(3), INPUT, X)," &
"121 (BC_4, *, internal, X)," &
"120 (BC_0, ioH(4), INPUT, X)," &
"119 (BC_0, ioH(5), INPUT, X)," &
"118 (BC_0, ioH(6), INPUT, X)," &
"117 (BC_0, ioH(7), INPUT, X)," &
"116 (BC_0, ioH(8), INPUT, X)," &
"115 (BC_4, *, internal, X)," &
"114 (BC_0, ioH(9), INPUT, X)," &
"113 (BC_1, ioH(5), OUTPUT3, X, 112, 0, Z)," &
"112 (BC_1, *, CONTROL, 0)," &
"111 (BC_1, ioH(6), OUTPUT3, X, 110, 0, Z)," &
"110 (BC_1, *, CONTROL, 0)," &
"109 (BC_1, ioH(7), OUTPUT3, X, 108, 0, Z)," &
"108 (BC_1, *, CONTROL, 0)," &
"107 (BC_1, ioH(8), OUTPUT3, X, 106, 0, Z)," &
"106 (BC_1, *, CONTROL, 0)," &
"105 (BC_4, *, internal, X)," &
"104 (BC_4, *, internal, X)," &
"103 (BC_1, ioH(9), OUTPUT3, X, 102, 0, Z)," &
"102 (BC_1, *, CONTROL, 0)," &
"101 (BC_1, *, CONTROL, 0)," &
"100 (BC_1, ioE(9), OUTPUT3, X, 101, 0, Z)," &
"99 (BC_4, *, internal, X)," &
"98 (BC_4, *, internal, X)," &
"97 (BC_1, *, CONTROL, 0)," &
"96 (BC_1, ioE(8), OUTPUT3, X, 97, 0, Z)," &
"95 (BC_1, *, CONTROL, 0)," &
"94 (BC_1, ioE(7), OUTPUT3, X, 95, 0, Z)," &
"93 (BC_1, *, CONTROL, 0)," &
"92 (BC_1, ioE(6), OUTPUT3, X, 93, 0, Z)," &
"91 (BC_1, *, CONTROL, 0)," &
"90 (BC_1, ioE(5), OUTPUT3, X, 91, 0, Z)," &
"89 (BC_0, ioE(9), INPUT, X)," &
"88 (BC_4, *, internal, X)," &
"87 (BC_0, ioE(8), INPUT, X)," &
"86 (BC_0, ioE(7), INPUT, X)," &
"85 (BC_0, ioE(6), INPUT, X)," &
"84 (BC_0, ioE(5), INPUT, X)," &
"83 (BC_0, ioE(4), INPUT, X)," &
"82 (BC_4, *, internal, X)," &
"81 (BC_0, ioE(3), INPUT, X)," &
"80 (BC_0, ioE(2), INPUT, X)," &
"79 (BC_0, ioE(1), INPUT, X)," &
"78 (BC_0, ioE(0), INPUT, X)," &
"77 (BC_1, *, CONTROL, 0)," &
"76 (BC_1, ioE(4), OUTPUT3, X, 77, 0, Z)," &
"75 (BC_4, *, internal, X)," &
"74 (BC_4, *, internal, X)," &
"73 (BC_1, *, CONTROL, 0)," &
"72 (BC_1, ioE(3), OUTPUT3, X, 73, 0, Z)," &
"71 (BC_1, *, CONTROL, 0)," &
"70 (BC_1, ioE(2), OUTPUT3, X, 71, 0, Z)," &
"69 (BC_1, *, CONTROL, 0)," &
"68 (BC_1, ioE(1), OUTPUT3, X, 69, 0, Z)," &
"67 (BC_1, *, CONTROL, 0)," &
"66 (BC_1, ioE(0), OUTPUT3, X, 67, 0, Z)," &
"65 (BC_1, ioG(0), OUTPUT3, X, 64, 0, Z)," &
"64 (BC_1, *, CONTROL, 0)," &
"63 (BC_1, ioG(1), OUTPUT3, X, 62, 0, Z)," &
"62 (BC_1, *, CONTROL, 0)," &
"61 (BC_1, ioG(2), OUTPUT3, X, 60, 0, Z)," &
"60 (BC_1, *, CONTROL, 0)," &
"59 (BC_1, ioG(3), OUTPUT3, X, 58, 0, Z)," &
"58 (BC_1, *, CONTROL, 0)," &
"57 (BC_4, *, internal, X)," &
"56 (BC_4, *, internal, X)," &
"55 (BC_1, ioG(4), OUTPUT3, X, 54, 0, Z)," &
"54 (BC_1, *, CONTROL, 0)," &
"53 (BC_0, ioG(0), INPUT, X)," &
"52 (BC_0, ioG(1), INPUT, X)," &
"51 (BC_0, ioG(2), INPUT, X)," &
"50 (BC_0, ioG(3), INPUT, X)," &
"49 (BC_4, *, internal, X)," &
"48 (BC_0, ioG(4), INPUT, X)," &
"47 (BC_0, ioG(5), INPUT, X)," &
"46 (BC_0, ioG(6), INPUT, X)," &
"45 (BC_0, ioG(7), INPUT, X)," &
"44 (BC_0, ioG(8), INPUT, X)," &
"43 (BC_4, *, internal, X)," &
"42 (BC_1, ioG(5), OUTPUT3, X, 41, 0, Z)," &
"41 (BC_1, *, CONTROL, 0)," &
"40 (BC_1, ioG(6), OUTPUT3, X, 39, 0, Z)," &
"39 (BC_1, *, CONTROL, 0)," &
"38 (BC_1, ioG(7), OUTPUT3, X, 37, 0, Z)," &
"37 (BC_1, *, CONTROL, 0)," &
"36 (BC_1, ioG(8), OUTPUT3, X, 35, 0, Z)," &
"35 (BC_1, *, CONTROL, 0)," &
"34 (BC_4, *, internal, X)," &
"33 (BC_4, *, internal, X)," &
"32 (BC_4, *, internal, X)," &
"31 (BC_4, *, internal, X)," &
"30 (BC_1, *, CONTROL, 0)," &
"29 (BC_1, ioF(8), OUTPUT3, X, 30, 0, Z)," &
"28 (BC_1, *, CONTROL, 0)," &
"27 (BC_1, ioF(7), OUTPUT3, X, 28, 0, Z)," &
"26 (BC_1, *, CONTROL, 0)," &
"25 (BC_1, ioF(6), OUTPUT3, X, 26, 0, Z)," &
"24 (BC_1, *, CONTROL, 0)," &
"23 (BC_1, ioF(5), OUTPUT3, X, 24, 0, Z)," &
"22 (BC_4, *, internal, X)," &
"21 (BC_0, ioF(8), INPUT, X)," &
"20 (BC_0, ioF(7), INPUT, X)," &
"19 (BC_0, ioF(6), INPUT, X)," &
"18 (BC_0, ioF(5), INPUT, X)," &
"17 (BC_0, ioF(4), INPUT, X)," &
"16 (BC_4, *, internal, X)," &
"15 (BC_0, ioF(3), INPUT, X)," &
"14 (BC_0, ioF(2), INPUT, X)," &
"13 (BC_0, ioF(1), INPUT, X)," &
"12 (BC_0, ioF(0), INPUT, X)," &
"11 (BC_1, *, CONTROL, 0)," &
"10 (BC_1, ioF(4), OUTPUT3, X, 11, 0, Z)," &
"9 (BC_4, *, internal, X)," &
"8 (BC_4, *, internal, X)," &
"7 (BC_1, *, CONTROL, 0)," &
"6 (BC_1, ioF(3), OUTPUT3, X, 7, 0, Z)," &
"5 (BC_1, *, CONTROL, 0)," &
"4 (BC_1, ioF(2), OUTPUT3, X, 5, 0, Z)," &
"3 (BC_1, *, CONTROL, 0)," &
"2 (BC_1, ioF(1), OUTPUT3, X, 3, 0, Z)," &
"1 (BC_1, *, CONTROL, 0)," &
"0 (BC_1, ioF(0), OUTPUT3, X, 1, 0, Z)";
end XCR5128_VQ100;