BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: mira_top

-- *****************************************************************************

--   BSDL file for design mira_top

--   Created by Synopsys Version D-2010.03-SP2 (May 31, 2010)

--   Designer: 
--   Company:  

--   Date: Mon Dec 20 12:10:19 2010

-- *****************************************************************************


 entity mira_top is
   
-- This section identifies the default device package selected.
   
   generic (PHYSICAL_PIN_MAP: string:= "PEX_8603");
   
-- This section declares all the ports in the design.
   
   port ( 
          I2C_ADDR0             : in       bit;
          I2C_ADDR1             : in       bit;
          I2C_ADDR2             : in       bit;
          JTAG_TCK              : in       bit;
          JTAG_TDI              : in       bit;
          JTAG_TMS              : in       bit;
          JTAG_TRSTn            : in       bit;
          PEX_HP_PRSNT_n         : in       bit;
          PEX_URIDn0            : in       bit;
          PEX_URIDn1            : in       bit;
          PEX_URIDn2            : in       bit;
          PEX_URIDp0            : in       bit;
          PEX_URIDp1            : in       bit;
          PEX_URIDp2            : in       bit;
          STRAP_FAST_BRINGUP_n   : in       bit;
          STRAP_RC_MODE         : in       bit;
          STRAP_SERDES_MODE_EN_n : in       bit;
          STRAP_SMBUS_EN_n       : in       bit;
          STRAP_UPCFG_TIMER_EN_n : in       bit;
          CPU_RXD               : inout    bit;
          CPU_TXD               : inout    bit;
          FATAL_ERR_n            : inout    bit;
          I2C_SCL0              : inout    bit;
          I2C_SDA0              : inout    bit;
          PEX_INTA_n             : inout    bit;
          PEX_LANE_GOOD0_n       : inout    bit;
          PEX_LANE_GOOD1_n       : inout    bit;
          PEX_LANE_GOOD2_n       : inout    bit;
          PEX_LANE_GOOD3_n       : inout    bit;
          PEX_WAKE_n             : inout    bit;
          JTAG_TDO              : out      bit;
          PEX_UTODn0            : out      bit;
          PEX_UTODn1            : out      bit;
          PEX_UTODn2            : out      bit;
          PEX_UTODp0            : out      bit;
          PEX_UTODp1            : out      bit;
          PEX_UTODp2            : out      bit;
          EE_CS_n                : linkage  bit;
          EE_DI                 : linkage  bit;
          EE_DO                 : linkage  bit;
          EE_SK                 : linkage  bit;
          PEX_PERST_n            : linkage  bit;
          PEX_REFCLK_INn0       : linkage  bit;
          PEX_REFCLK_INp0       : linkage  bit;
          PEX_REFCLK_OUTn1      : linkage  bit;
          PEX_REFCLK_OUTn2      : linkage  bit;
          PEX_REFCLK_OUTn3      : linkage  bit;
          PEX_REFCLK_OUTp1      : linkage  bit;
          PEX_REFCLK_OUTp2      : linkage  bit;
          PEX_REFCLK_OUTp3      : linkage  bit;
          PEX_REFCLK_OUT_BIAS   : linkage  bit;
          PEX_REFCLK_OUT_RREF   : linkage  bit;
          PEX_VDDA_P0             : linkage  bit;
          PEX_VDDA_P1             : linkage  bit;
          PEX_VDDA_P2             : linkage  bit;
          PEX_VDDD0_P0            : linkage  bit;
          PEX_VDDD0_P1            : linkage  bit;
          PEX_VDDD0_P2            : linkage  bit;
          PEX_VDDD1_P0            : linkage  bit;
          PEX_VDDD1_P1            : linkage  bit;
          PEX_VDDD1_P2            : linkage  bit;
          PEX_VSSA_P0             : linkage  bit;
          PEX_VSSA_P1             : linkage  bit;
          PEX_VSSA_P2             : linkage  bit;
          PEX_VSSD0_P0            : linkage  bit;
          PEX_VSSD0_P1            : linkage  bit;
          PEX_VSSD0_P2            : linkage  bit;
          PEX_VSSD1_P0            : linkage  bit;
          PEX_VSSD1_P1            : linkage  bit;
          PEX_VSSD1_P2            : linkage  bit;
          PLL1_AGND               : linkage  bit;
          PLL1_AVDD               : linkage  bit;
          STRAP_TESTMODE0               : linkage  bit;
          STRAP_TESTMODE1               : linkage  bit;
          STRAP_TESTMODE2               : linkage  bit;
          STRAP_TESTMODE3               : linkage  bit;
          STRAP_SSC_CENTER_n               : linkage  bit;
          STRAP_PLL_BYPASS_n               : linkage  bit;
          STRAP_LEGACY               : linkage  bit;
          PROCMON               : linkage  bit;
          PWRON_RSTn            : in  bit;
          STRAP_DEBUG_SELn      : in  bit;
          STRAP_PORTCFG0        : linkage  bit;
          STRAP_PROBE_MODEn     : in  bit;
          N_C               : linkage    bit_vector (0 to 24);
          VDD_IO                : linkage  bit_vector (0 to 6);
          VDD_CORE                : linkage  bit_vector (0 to 5);
          VSS                : linkage  bit_vector (0 to 6);
          VAUX_IO                : linkage  bit_vector (0 to 1);
          VAUX_CORE                : linkage  bit_vector (0 to 2);
          XTAL_IN               : linkage  bit;
          XTAL_OUT              : linkage  bit
   );
   
   use STD_1149_1_2001.all;
   use STD_1149_6_2003.all;
   
   attribute COMPONENT_CONFORMANCE of mira_top: entity is "STD_1149_1_2001";
   
   attribute PIN_MAP of mira_top: entity is PHYSICAL_PIN_MAP;
   
-- This section specifies the pin map for each port. This information is 
-- extracted from the port-to-pin map file that was read in using the 
-- "read_pin_map" command.
   
     constant PEX_8603: PIN_MAP_STRING := 
"PEX_VSSD1_P0 			:B4,  " &
"PEX_URIDp0 			:A5,  " &
"PEX_URIDn0 			:A6,  " &
"PEX_VSSD0_P0 			:B5,  " &
"PEX_VDDD1_P0 			:A7,  " &
"PEX_UTODp0 			:B6,  " &
"PEX_UTODn0 			:A8,  " &
"PEX_VDDD0_P0 			:B7,  " &
"PEX_VSSA_P0 			:A9,  " &
"PEX_VDDA_P0 			:B8,  " &
"PEX_VSSD1_P1 			:B9,  " &
"PEX_URIDp1 			:A11,  " &
"PEX_URIDn1 			:B10,  " &
"PEX_VSSD0_P1 			:A12,  " &
"PEX_VDDD1_P1 			:A13,  " &
"PEX_UTODp1 			:B11,  " &
"PEX_UTODn1 			:A14,  " &
"PEX_VDDD0_P1 			:B12,  " &
"PEX_VSSA_P1 			:A15,  " &
"PEX_VDDA_P1 			:B13,  " &
"STRAP_PROBE_MODEn 			:C3,  " &
"PEX_LANE_GOOD1_n 			:A16,  " &
"PWRON_RSTn 			:B14,  " &
"STRAP_DEBUG_SELn 			:C4,  " &
"PEX_PERST_n 			:B15,  " &
"PEX_LANE_GOOD3_n 			:B16,  " &
"PEX_LANE_GOOD0_n 			:A19,  " &
"PEX_REFCLK_OUTp3 			:A20,  " &
"PEX_REFCLK_OUTn3 			:A21,  " &
"PEX_REFCLK_OUTp2 			:A22,  " &
"PEX_REFCLK_OUTn2 			:A23,  " &
"PEX_REFCLK_OUTp1 			:A24,  " &
"PEX_REFCLK_OUTn1 			:B21,  " &
"PEX_REFCLK_OUT_BIAS 			:B22,  " &
"PEX_REFCLK_OUT_RREF 			:B23,  " &
"PEX_REFCLK_INp0 			:A27,  " &
"PEX_REFCLK_INn0 			:B24,  " &
"STRAP_UPCFG_TIMER_EN_n 			:A28,  " &
"PEX_HP_PRSNT_n 			:B25,  " &
"PLL1_AVDD 			:A31,  " &
"PLL1_AGND 			:B27,  " &
"STRAP_TESTMODE0 			:C7,  " &
"STRAP_SMBUS_EN_n 			:B28,  " &
"STRAP_TESTMODE1 			:C8,  " &
"STRAP_TESTMODE2 			:C9,  " &
"JTAG_TDO 			:B29,  " &
"JTAG_TRSTn 			:A34,  " &
"STRAP_TESTMODE3 			:C10,  " &
"XTAL_IN 			:B30,  " &
"XTAL_OUT 			:A35,  " &
"EE_DI 			:A36,  " &
"EE_CS_n 			:B32,  " &
"EE_SK 			:A38,  " &
"EE_DO 			:B33,  " &
"STRAP_SERDES_MODE_EN_n 			:A39,  " &
"PEX_INTA_n 			:B34,  " &
"STRAP_FAST_BRINGUP_n 			:A40,  " &
"STRAP_RC_MODE 			:B35,  " &
"I2C_ADDR2 			:A41,  " &
"I2C_ADDR1 			:B36,  " &
"I2C_ADDR0 			:A42,  " &
"STRAP_PORTCFG0 			:B37,  " &
"CPU_RXD 			:B38,  " &
"CPU_TXD 			:A44,  " &
"I2C_SCL0 			:A45,  " &
"I2C_SDA0 			:B39,  " &
"FATAL_ERR_n 			:B40,  " &
"JTAG_TDI 			:A47,  " &
"STRAP_SSC_CENTER_n 			:C11,  " &
"JTAG_TCK 			:A48,  " &
"JTAG_TMS 			:B42,  " &
"STRAP_PLL_BYPASS_n 			:C12,  " &
"STRAP_LEGACY 			:C13,  " &
"PROCMON 			:C14,  " &
"PEX_VDDA_P2 			:B44,  " &
"PEX_VSSA_P2 			:A51,  " &
"PEX_VDDD0_P2 			:B45,  " &
"PEX_UTODn2 			:A52,  " &
"PEX_UTODp2 			:A53,  " &
"PEX_VDDD1_P2 			:B46,  " &
"PEX_VSSD0_P2 			:A54,  " &
"PEX_URIDn2 			:B47,  " &
"PEX_URIDp2 			:A55,  " &
"PEX_VSSD1_P2 			:B48,  " &
"PEX_LANE_GOOD2_n 			:B55,  " &
"PEX_WAKE_n 			:B56,  " &
"VAUX_CORE 			: (A10, B49,  A57), " &
"VAUX_IO 			: (A18, A64),  " &
"VDD_CORE 			:(A29, B26, A37, A46, B43, A50),  " &
"VDD_IO 			: (B3, B31, A43, b41, A30, A26, B19),  " &
"N_C 			: (B50, A49, A33, A58, B51, A59, A60, B52, "&
                          "B53, A61, A62, B54, A1, C1, B1, A2, C2, "&
                          "B2, A17, A3, A4, C5, C6, C15, C16), "&
"VSS 			: (B17,  B18, B20, A25, A32, A56, A63 )" ; 
-- This section specifies the differential IO port groupings.
   
   attribute PORT_GROUPING of mira_top: entity is 
      "Differential_Voltage ( " &
          "(PEX_URIDp0,PEX_URIDn0)," &
          "(PEX_URIDp1,PEX_URIDn1)," &
          "(PEX_URIDp2,PEX_URIDn2)," &
          "(PEX_UTODp0,PEX_UTODn0)," &
          "(PEX_UTODp1,PEX_UTODn1)," &
          "(PEX_UTODp2,PEX_UTODn2))" ;

-- This section specifies the TAP ports. For the TAP TCK port, the parameters in 
-- the brackets are:
--        First Field : Maximum  TCK frequency.
--        Second Field: Allowable states TCK may be stopped in.
   
   attribute TAP_SCAN_CLOCK of JTAG_TCK  : signal is (5.000000e+06, BOTH);
   attribute TAP_SCAN_IN    of JTAG_TDI  : signal is true;
   attribute TAP_SCAN_MODE  of JTAG_TMS  : signal is true;
   attribute TAP_SCAN_OUT   of JTAG_TDO  : signal is true;
   attribute TAP_SCAN_RESET of JTAG_TRSTn: signal is true;
   
-- Specifies the compliance enable patterns for the design. It lists a set of 
-- design ports and the values that they should be set to, in order to enable 
-- compliance to IEEE Std 1149.1
   
   attribute COMPLIANCE_PATTERNS of mira_top: entity is 
   "( PWRON_RSTn, STRAP_DEBUG_SELn, STRAP_PROBE_MODEn) (001)";
   

-- Specifies the number of bits in the instruction register.
   
   attribute INSTRUCTION_LENGTH of mira_top: entity is 4;
   
-- Specifies the boundary-scan instructions implemented in the design and their 
-- opcodes.
   
   attribute INSTRUCTION_OPCODE of mira_top: entity is 
     "BYPASS       (1111)," &
     "EXTEST       (0010)," &
     "SAMPLE       (0011)," &
     "PRELOAD      (0011)," &
     "EXTEST_PULSE (1001)," &
     "EXTEST_TRAIN (1000)," &
     "CLAMP        (0110)," &
     "HIGHZ        (0101)," &
     "IDCODE       (1110)";
   
-- Specifies the bit pattern that is loaded into the instruction register when 
-- the TAP controller passes through the Capture-IR state. The standard mandates 
-- that the two LSBs must be "01". The remaining bits are design specific.
   
   attribute INSTRUCTION_CAPTURE of mira_top: entity is "0001";
   
-- Specifies the bit pattern that is loaded into the DEVICE_ID register during 
-- the IDCODE instruction when the TAP controller passes through the Capture-DR 
-- state.
   
   attribute IDCODE_REGISTER of mira_top: entity is 
     "0000" &                  
 -- 4-bit version number
     "1000011000000011" &      
 -- 16-bit part number
     "00111001101" &           
 -- 11-bit identity of the manufacturer
     "1";                      
 -- Required by IEEE Std 1149.1
   
-- This section specifies the test data register placed between TDI and TDO for 
-- each implemented instruction.
   
   attribute REGISTER_ACCESS of mira_top: entity is 
        "BYPASS          (BYPASS, CLAMP, HIGHZ)," &
        "BOUNDARY        (EXTEST, SAMPLE, PRELOAD, EXTEST_PULSE, " &
        "EXTEST_TRAIN)," &
        "DEVICE_ID       (IDCODE)";
   
-- Specifies the length of the boundary scan register.
   
   attribute BOUNDARY_LENGTH of mira_top: entity is 61;
   
-- The following list specifies the characteristics of each cell in the boundary 
-- scan register from TDI to TDO. The following is a description of the label 
-- fields:
--      num     : Is the cell number.
--      cell    : Is the cell type as defined by the standard.
--      port    : Is the design port name. Control cells do not have a port 
--                name.
--      function: Is the function of the cell as defined by the standard. Is one 
--                of input, output2, output3, bidir, control or controlr.
--      safe    : Specifies the value that the BSR cell should be loaded with 
--                for safe operation when the software might otherwise choose a 
--                random value.
--      ccell   : The control cell number. Specifies the control cell that 
--                drives the output enable for this port.
--      disval  : Specifies the value that is loaded into the control cell to 
--                disable the output enable for the corresponding port.
--      rslt    : Resulting state. Shows the state of the driver when it is 
--                disabled.
   
   attribute BOUNDARY_REGISTER of mira_top: entity is 
--     
--    num   cell   port                     function      safe  [ccell  disval  
--    rslt]
--     
     "60   (BC_4,  PEX_URIDp0,            observe_only, " &
     "X),                        " &
     "59   (BC_4,  PEX_URIDp0,            observe_only, " &
     "X),                        " &
     "58   (BC_4,  PEX_URIDn0,            observe_only, " &
     "X),                        " &
     "57   (BC_2,  *,                       control,      " &
     "0),                        " &
     "56   (AC_1,  PEX_UTODp0,            output3,      X,    57,     " &
     "0,      Z),  " &
     "55   (AC_SELX,*,                       internal,     " &
     "0),                        " &
     "54   (BC_4,  PEX_URIDp1,            observe_only, " &
     "X),                        " &
     "53   (BC_4,  PEX_URIDp1,            observe_only, " &
     "X),                        " &
     "52   (BC_4,  PEX_URIDn1,            observe_only, " &
     "X),                        " &
     "51   (BC_2,  *,                       control,      " &
     "0),                        " &
     "50   (AC_1,  PEX_UTODp1,            output3,      X,    51,     " &
     "0,      Z),  " &
     "49   (AC_SELX,*,                       internal,     " &
     "0),                        " &
     "48   (BC_2,  *,                       control,      " &
     "0),                        " &
     "47   (BC_7,  PEX_LANE_GOOD1_n,       bidir,        X,    48,     " &
     "0,      WEAK1)," &
     "46   (BC_2,  *,                       control,      " &
     "0),                        " &
     "45   (BC_7,  PEX_LANE_GOOD3_n,       bidir,        X,    46,     " &
     "0,      WEAK1)," &
     "44   (BC_2,  *,                       control,      " &
     "0),                        " &
     "43   (BC_7,  PEX_LANE_GOOD0_n,       bidir,        X,    44,     " &
     "0,      WEAK1)," &
     "42   (BC_2,  STRAP_UPCFG_TIMER_EN_n, input,        " &
     "X),                        " &
     "41   (BC_2,  PEX_HP_PRSNT_n,         input,        " &
     "X),                        " &
     "40   (BC_2,  STRAP_SMBUS_EN_n,       input,        " &
     "X),                        " &
     "39   (BC_2,  *,          internal , X ) , " &
     "38   (BC_2,  STRAP_SERDES_MODE_EN_n, input,        " &
     "X),                        " &
     "37   (BC_2,  *,                       control,      " &
     "0),                        " &
     "36   (BC_7,  PEX_INTA_n,             bidir,        X,    37,     " &
     "0,      WEAK1)," &
     "35   (BC_2,  STRAP_FAST_BRINGUP_n,   input,        " &
     "X),                        " &
     "34   (BC_2,  STRAP_RC_MODE,         input,        " &
     "X),                        " &
     "33   (BC_2,  I2C_ADDR2,             input,        " &
     "X),                        " &
     "32   (BC_2,  I2C_ADDR1,             input,        " &
     "X),                        " &
     "31   (BC_2,  I2C_ADDR0,             input,        " &
     "X),                        " &
     "30   (BC_2,  *,                       control,      " &
     "0),                        " &
     "29   (BC_7,  CPU_RXD,               bidir,        X,    30,     " &
     "0,      WEAK1)," &
     "28   (BC_2,  *,                       control,      " &
     "0),                        " &
     "27   (BC_7,  CPU_TXD,               bidir,        X,    28,     " &
     "0,      WEAK1)," &
     "26   (BC_2,  *,                       control,      " &
     "0),                        " &
     "25   (BC_7,  I2C_SCL0,              bidir,        X,    26,     " &
     "0,      Z),  " &
     "24   (BC_2,  *,                       control,      " &
     "0),                        " &
     "23   (BC_7,  I2C_SDA0,              bidir,        X,    24,     " &
     "0,      Z),  " &
     "22   (BC_2,  *,                       control,      " &
     "0),                        " &
     "21   (BC_7,  FATAL_ERR_n,            bidir,        X,    22,     " &
     "0,      Z),  " &
     "20   (BC_2,  *,          internal , X ) , " &
     "19   (BC_2,  *,          internal , X ) , " &
     "18   (BC_4,  *,          internal , X ) , " &
     "17   (BC_2,  *,          internal , X ) , " &
     "16   (BC_4,  *,          internal , X ) , " &
     "15   (BC_2,  *,                       control,      " &
     "0),   " &
     "14   (AC_1,  PEX_UTODp2,            output3,      X,    15,     " &
     "0,      Z),  " &
     "13   (AC_SELX,*,                       internal,     " &
     "0),                        " &
     "12   (BC_4,  PEX_URIDn2,            observe_only, " &
     "X),                        " &
     "11   (BC_4,  PEX_URIDp2,            observe_only, " &
     "X),                        " &
     "10   (BC_4,  PEX_URIDp2,            observe_only, " &
     "X), " &
     "9    (BC_2,  *,          internal , X ) , " &
     "8    (BC_4,  *,          internal , X ) , " &
     "7    (AC_SELX,*,                       internal,     " & "0),                        " &
     "6    (BC_4,  *,          internal , X ) , " &
     "5    (BC_4,  *,          internal , X ) , " &
     "4    (BC_4,  *,          internal , X ) , " &
     "3    (BC_2,  *,                       control,      " &
     "0),                        " &
     "2    (BC_7,  PEX_LANE_GOOD2_n,       bidir,        X,    3,      " &
     "0,      WEAK1)," &
     "1    (BC_2,  *,                       control,      " &
     "0),                        " &
     "0    (BC_7,  PEX_WAKE_n,             bidir,        X,    1,      " &
     "0,      Z)   ";
   
-- Advanced I/O Description
   
   attribute AIO_COMPONENT_CONFORMANCE of mira_top: entity is "STD_1149_6_2003"
 ;
   
   attribute AIO_EXTEST_Pulse_Execution of mira_top: entity is 
   "Wait_Duration 6.200000e-9";
   
   attribute AIO_EXTEST_Train_Execution of mira_top: entity is 
   "train 30, maximum_time 6.200000e-9";
   
   attribute AIO_Pin_Behavior of mira_top: entity is 
   " PEX_URIDp2[10], PEX_URIDp1[53], PEX_URIDp0[59] : " &
   "LP_time=5.000000e-9 HP_time=15.000000e-9 ;" &
   "PEX_UTODp2 : AC_Select=13 ;" &
   "PEX_UTODp1 : AC_Select=49 ;" &
   "PEX_UTODp0 : AC_Select=55  ";
 
 end mira_top;