-------------------------------------------------------------------------------
-- TI TMS320C40 Parallel-Processing 32-bit Floating-point DSP --
-------------------------------------------------------------------------------
-- Created by : Texas Instruments Incorporated --
-- Documentation : TMS320C40 Users Guide (SPRU063) and TMS320C40 Test Port --
-- and Boundary Scan Technical Reference (Rev *) --
-- BSDL revision : 1.0 --
-- BSDL status : Production --
-- Date created : 08/08/95 --
-- --
-- IMPORTANT NOTICE --
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-- accordance with TI's standard warranty. Testing and other quality control--
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-- Copyright (c) 1994, Texas Instruments Incorporated --
--
--Technical Note for Texas Instruments TI320C4x Devices
--
--Incorrect Operation of JTAG Logic during Capture-DR state
--
--Overview:
--
--The TI320C4x devices exhibit a non-compliant behavior during the Capture-DR state. This behavior --causes the capturing of cell data to occur 1/2 TCK clock later than the JTAG specification requires.
--
--Detailed Description:
--
--When performing a Data Register (DR) scan of the boundary register the Test Access Port (TAP) of each --device passes through a state called Capture-DR. During the rising edge of TCK while the device is in --this state the values of all the boundary register cells must be loaded with a value. This value will be --scanned out during the Shift-DR states. For input and bi-directional input pins the value of the device's --pin is latched into the cell. The TI320C4x devices perform the DR scan correctly.
--
--The problem is that the latching of input data occurs 1/2 TCK later than required. Instead of latching on
--the rising edge in the Capture-DR state it latches on the falling edge in the Shift-DR state.
--
--Work Around:
--
--This behavior must be considered during development of device and board level tests. The tester must --maintain the input pins value for an additional 1/2 TCK. This usually is not a problem.
--
--For board level JTAG interconnect tests this will not present any problems. The input pin values for the --TI320C4x will be provided by output pins of other devices. These devices will be setup during the prior --Update-DR state and remain until the next Update-DR state.
--This covers the 1/2 TCK late capture problem.
--
--Device or in-circuit testing could be a problem if the tester does not maintain input pin values past the --Capture-DR state. If the tester does not maintain the input values then the test program must be modified.
--
-------------------------------------------------------------------------------
entity tms320c40 is
generic (PHYSICAL_PIN_MAP : string := "GFL");
port (A:out bit_vector(0 to 30);
AE_NEG:in bit;
C0D:inout bit_vector(0 to 7);
C1D:inout bit_vector(0 to 7);
C2D:inout bit_vector(0 to 7);
C3D:inout bit_vector(0 to 7);
C4D:inout bit_vector(0 to 7);
C5D:inout bit_vector(0 to 7);
CACK_NEG:inout bit_vector(0 to 5);
CE_NEG:in bit_vector(0 to 1);
CRDY_NEG:inout bit_vector(0 to 5);
CREQ_NEG:inout bit_vector(0 to 5);
CSTRB_NEG:inout bit_vector(0 to 5);
CVSS:linkage bit_vector(1 to 15);
D:inout bit_vector(0 to 31);
DE_NEG:in bit;
DVDD:linkage bit_vector(1 to 13);
DVSS:linkage bit_vector(1 to 15);
EMU:inout bit_vector(0 to 1);
GADVDD:linkage bit_vector(1 to 3);
GDDVDD:linkage bit_vector(1 to 3);
H1:out bit;
H3:out bit;
IACK_NEG:out bit;
IIOF:inout bit_vector(0 to 3);
IVSS:linkage bit_vector(1 to 6);
LA:out bit_vector(0 to 30);
LADVDD:linkage bit_vector(1 to 3);
LAE_NEG:in bit;
LCE_NEG:in bit_vector(0 to 1);
LD:inout bit_vector(0 to 31);
LDDVDD:linkage bit_vector(1 to 3);
LDE_NEG:in bit;
LLOCK_NEG:out bit;
LOCK_NEG:out bit;
LPAGE:out bit_vector(0 to 1);
LRDY_NEG:in bit_vector(0 to 1);
LR_W_NEG:out bit_vector(0 to 1);
LSTAT:out bit_vector(0 to 3);
LSTRB_NEG:out bit_vector(0 to 1);
NMI_NEG:in bit;
PAGE:out bit_vector(0 to 1);
RDY_NEG:in bit_vector(0 to 1);
RESETLOC:in bit_vector(0 to 1);
RESET_NEG:in bit;
ROMEN:in bit;
R_W_NEG:out bit_vector(0 to 1);
STAT:out bit_vector(0 to 3);
STRB_NEG:out bit_vector(0 to 1);
SUBS:linkage bit;
TCK:in bit;
TCLK:inout bit_vector(0 to 1);
TDO:out bit;
TDI:in bit;
TMS:in bit;
TRST_NEG:in bit;
VDDL:linkage bit_vector(1 to 4);
VSSL:linkage bit_vector(1 to 4);
X1:linkage bit;
X2CLKIN:linkage bit);
use STD_1149_1_1990.all; -- Get standard attributes and definitions
use TI_BIDIR.all; -- Get bidirectional cell type
-- This package type TI_BIDIR must be available to your toolset.
-- In most cases this text should be placed in a separate file that
-- is referenced via the 'use' statement.
--
-- package TI_BIDIR is
-- use STD_1149_1_1990.all; -- Comment out for ASSET tool
-- constant BC_BIDIR : CELL_INFO;
-- end TI_BIDIR;
--
-- package body TI_BIDIR is
-- constant BC_BIDIR : CELL_INFO :=
-- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PI),
-- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
-- (BIDIR_IN, INTEST, PI), (BIDIR_OUT, INTEST, PI));
-- end TI_BIDIR;
attribute PIN_MAP of tms320c40 : entity is PHYSICAL_PIN_MAP;
constant GFL : PIN_MAP_STRING :=
" A:(D32,B32,D30,C29,B30,F28,F24,E29,C27,D28,B28, "&
" F26,C25,E27,B26,D26,C23,B24,E25,C21,D24,B22, "&
" E23,C19,D22,B20,E21,B18,C17,D20,B16), "&
" AE_NEG:AG31, "&
" C0D:(AP4, AL5, AN5, AM4, AP6, AM6, AN7, AK8), "&
" C1D:(AL7, AP8, AM8, AK12,AK10,AN9, AL9, AP10), "&
" C2D:(AM18,AN19,AL19,AP20,AM20,AN21,AL21,AP22), "&
" C3D:(AM22,AN23,AL23,AP24,AM24,AN25,AL25,AP26), "&
" C4D:(AN27,AM26,AK24,AL27,AP28,AK26,AN29,AM28), "&
" C5D:(AL29,AP30,AK28,AN31,AM30,AP32,AM32,AL31), "&
" CACK_NEG:(AN11,AN13,AM14,AM16,AK32,AJ31), "&
" CE_NEG:(AA33,V34), "&
" CRDY_NEG: (AP12,AP14,AL15,AL17,AH30,AH32), "&
" CREQ_NEG: (AM10,AM12,AN15,AN17,AN33,AL33), "&
" CSTRB_NEG:(AL11,AL13,AP16,AP18,AM34,AK34), "&
" CVSS:(AR19,AR7,N1,AL35,A27,A9,E1,J35,E35, "&
" AR25,AE1,AR13,A19,R35,AL1), "&
" D:(U33,V32,T34,U31,R33,P34,T32,N33,R31,M34, "&
" P32,L33,N31,K34,M32,J33,L31,M30,K32,H34,J31, "&
" G33,K30,F34,H32,E33,D34,G31,C33,H30,E31,F32), "&
" DE_NEG:AA31, "&
" DVDD:(AR11,AR29,A13,A7,A17,L35,AR23,A29,L1,AC1, "&
" AR17,A23,AJ1), "&
" DVSS:(AJ35,A21,A25,G35,A11,AG1,AM2,R1,AR21, "&
" AR15,A15,AR27,G1,N35,AR9), "&
" EMU:(AA35,AD34), "&
" GADVDD:(B2,AR1,U35), GDDVDD:(V2,A35,A1), "&
" H1:AC3, H3:AC5, IACK_NEG:W3, "&
" IIOF:(AN3,AL3,AH6,AK2), "&
" IVSS:(AR5,AR31,AG35,A31,J1,A5), "&
" LA:(D2,D4,E3,F4,H6,F2,G5,G3,H4,H2,K6,M6,J5,J3,K4, "&
" K2,L3,L5,M2,M4,N3,N5,P2,P4,R3,R5,T2,U3,T4,V4,U5), "&
" LADVDD:(B34,AB2,AP34), "&
" LAE_NEG:AB4, LCE_NEG:(AG5,AF2), "&
" LD:(E19,C15,D18,B14,E17,D16,C13,E15,B12,D14,C11, "&
" E13,B10,D12,C9,E11,F12,D10,B8,E9,C7,F10,B6, "&
" D8,C5,E7,B4,F8,D6,C3,E5,F6), "&
" LDDVDD:(AR35,AP2,U1), LDE_NEG:AD4, "&
" LLOCK_NEG:AA5, LOCK_NEG:W33, "&
" LPAGE:(AH2,AG3), LRDY_NEG:(AF6,AE5), "&
" LR_W_NEG:(AH4,AF4), LSTAT:(AA3,Y4,Y2,W5), "&
" LSTRB_NEG:(AJ3,AD6), NMI_NEG:AJ5, "&
" PAGE:(AG33,AB32), RDY_NEG:(Y32,W31), "&
" RESETLOC:(AF30,AH34), RESET_NEG:AJ33, "&
" ROMEN:AK4, R_W_NEG:(AF32,AC31), "&
" STAT:(AD32,AE33,AF34,AE31), "&
" STRB_NEG:(AD30,AC33), SUBS:C31, "&
" TCLK:(AE3,AD2), "&
" TCK:Y34, TDO:AB34, TDI:AC35, "&
" TMS:W35, TRST_NEG:AE35, "&
" VDDL:(AN1,AN35,C35,C1), VSSL:(A3,AR3,AR33,A33), "&
" X1:W1, X2CLKIN:AA1 ";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRST_NEG : signal is true;
-- unconfirmed TCK Fmax
attribute TAP_SCAN_CLOCK of TCK : signal is (20.00e6, BOTH);
attribute INSTRUCTION_LENGTH of tms320c40 : entity is 8;
attribute INSTRUCTION_OPCODE of tms320c40 : entity is
"EXTEST (00000000), "&
"BYPASS (11111111), "&
"SAMPLE (00000010), "&
"HIGHZ (00000110), "&
"PRIVATE1 (00000011), "& -- Use of PRIVATE opcodes could
"PRIVATE2 (00100000), "& -- cause the device to operate
"PRIVATE3 (00100001), "& -- in an unexpected manner.
"PRIVATE4 (00100010), "&
"PRIVATE5 (00100011), "&
"PRIVATE6 (00100100), "&
"PRIVATE7 (00100101), "&
"PRIVATE8 (00100110), "&
"PRIVATE9 (00100111), "&
"PRIVATE10 (00101000), "&
"PRIVATE11 (00101001) ";
attribute INSTRUCTION_CAPTURE of tms320c40 : entity is "0XXXXX01";
-- Instruction capture value is dependent upon the
-- silicon revision level (PG revision).
-- PG-1 (0000XX01)
-- PG-2 (0001XX01)
-- PG-3 (0001XX01)
-- PG-5 (0010XX01)
attribute INSTRUCTION_DISABLE of tms320c40 : entity is "HIGHZ";
attribute INSTRUCTION_PRIVATE of tms320c40 : entity is
"PRIVATE1, PRIVATE2, PRIVATE3, "&
"PRIVATE4, PRIVATE5, PRIVATE6, "&
"PRIVATE7, PRIVATE8, PRIVATE9, "&
"PRIVATE10, PRIVATE11 ";
attribute REGISTER_ACCESS of tms320c40 : entity is
"BOUNDARY (EXTEST, SAMPLE), "&
"BYPASS (BYPASS, HIGHZ) ";
attribute BOUNDARY_CELLS of tms320c40 : entity is "BC_1, BC_BIDIR";
attribute BOUNDARY_LENGTH of tms320c40 : entity is 306;
attribute BOUNDARY_REGISTER of tms320c40 : entity is
"0 (BC_1 , * ,internal, 1 ), "&
"1 (BC_1 , * , control, 1 ), "&
"2 (BC_BIDIR, EMU(0) , bidir , X, 1, 1, Z), "&
"3 (BC_1 , * , control, 1 ), "&
"4 (BC_BIDIR, EMU(1) , bidir , X, 3, 1, Z), "&
"5 (BC_1 , * , control, 1 ), "&
"6 (BC_1 , PAGE(1) , output3, X, 5, 1, Z), "&
"7 (BC_1 , * , control, 1 ), "&
"8 (BC_1 , R_W_NEG(1) , output3, X, 7, 1, Z), "&
"9 (BC_1 , * , control, 1 ), "&
"10 (BC_1 , STRB_NEG(1) , output3, X, 9, 1, Z), "&
"11 (BC_1 , STAT(0) , output3, X, 15, 1, Z), "&
"12 (BC_1 , STAT(1) , output3, X, 15, 1, Z), "&
"13 (BC_1 , STAT(2) , output3, X, 15, 1, Z), "&
"14 (BC_1 , STAT(3) , output3, X, 15, 1, Z), "&
"15 (BC_1 , * , control, 1 ), "&
"16 (BC_1 , * , control, 1 ), "&
"17 (BC_1 , PAGE(0) , output3, X, 16, 1, Z), "&
"18 (BC_1 , * , control, 1 ), "&
"19 (BC_1 , R_W_NEG(0) , output3, X, 18, 1, Z), "&
"20 (BC_1 , * , control, 1 ), "&
"21 (BC_1 , STRB_NEG(0) , output3, X, 20, 1, Z), "&
"22 (BC_1 , AE_NEG , input , X ), "&
"23 (BC_1 , RESETLOC(1) , input , X ), "&
"24 (BC_1 , RESETLOC(0) , input , X ), "&
"25 (BC_1 , RESET_NEG , input , X ), "&
"26 (BC_1 , * , control, 1 ), "&
"27 (BC_BIDIR, CRDY_NEG(5) , bidir , X, 26, 1, Z), "&
"28 (BC_1 , * , control, 1 ), "&
"29 (BC_BIDIR, CSTRB_NEG(5), bidir , X, 28, 1, Z), "&
"30 (BC_1 , * , control, 1 ), "&
"31 (BC_BIDIR, CACK_NEG(5) , bidir , X, 30, 1, Z), "&
"32 (BC_1 , * , control, 1 ), "&
"33 (BC_BIDIR, CREQ_NEG(5) , bidir , X, 32, 1, Z), "&
"34 (BC_1 , * , control, 1 ), "&
"35 (BC_BIDIR, CRDY_NEG(4) , bidir , X, 34, 1, Z), "&
"36 (BC_1 , * , control, 1 ), "&
"37 (BC_BIDIR, CSTRB_NEG(4), bidir , X, 36, 1, Z), "&
"38 (BC_1 , * , control, 1 ), "&
"39 (BC_BIDIR, CACK_NEG(4) , bidir , X, 38, 1, Z), "&
"40 (BC_1 , * , control, 1 ), "&
"41 (BC_BIDIR, CREQ_NEG(4) , bidir , X, 40, 1, Z), "&
"42 (BC_BIDIR, C5D(7) , bidir , X, 50, 1, Z), "&
"43 (BC_BIDIR, C5D(6) , bidir , X, 50, 1, Z), "&
"44 (BC_BIDIR, C5D(5) , bidir , X, 50, 1, Z), "&
"45 (BC_BIDIR, C5D(4) , bidir , X, 50, 1, Z), "&
"46 (BC_BIDIR, C5D(3) , bidir , X, 50, 1, Z), "&
"47 (BC_BIDIR, C5D(2) , bidir , X, 50, 1, Z), "&
"48 (BC_BIDIR, C5D(1) , bidir , X, 50, 1, Z), "&
"49 (BC_BIDIR, C5D(0) , bidir , X, 50, 1, Z), "&
"50 (BC_1 , * , control, 1 ), "&
"51 (BC_BIDIR, C4D(7) , bidir , X, 59, 1, Z), "&
"52 (BC_BIDIR, C4D(6) , bidir , X, 59, 1, Z), "&
"53 (BC_BIDIR, C4D(5) , bidir , X, 59, 1, Z), "&
"54 (BC_BIDIR, C4D(4) , bidir , X, 59, 1, Z), "&
"55 (BC_BIDIR, C4D(3) , bidir , X, 59, 1, Z), "&
"56 (BC_BIDIR, C4D(2) , bidir , X, 59, 1, Z), "&
"57 (BC_BIDIR, C4D(1) , bidir , X, 59, 1, Z), "&
"58 (BC_BIDIR, C4D(0) , bidir , X, 59, 1, Z), "&
"59 (BC_1 , * , control, 1 ), "&
"60 (BC_BIDIR, C3D(7) , bidir , X, 68, 1, Z), "&
"61 (BC_BIDIR, C3D(6) , bidir , X, 68, 1, Z), "&
"62 (BC_BIDIR, C3D(5) , bidir , X, 68, 1, Z), "&
"63 (BC_BIDIR, C3D(4) , bidir , X, 68, 1, Z), "&
"64 (BC_BIDIR, C3D(3) , bidir , X, 68, 1, Z), "&
"65 (BC_BIDIR, C3D(2) , bidir , X, 68, 1, Z), "&
"66 (BC_BIDIR, C3D(1) , bidir , X, 68, 1, Z), "&
"67 (BC_BIDIR, C3D(0) , bidir , X, 68, 1, Z), "&
"68 (BC_1 , * , control, 1 ), "&
"69 (BC_BIDIR, C2D(7) , bidir , X, 77, 1, Z), "&
"70 (BC_BIDIR, C2D(6) , bidir , X, 77, 1, Z), "&
"71 (BC_BIDIR, C2D(5) , bidir , X, 77, 1, Z), "&
"72 (BC_BIDIR, C2D(4) , bidir , X, 77, 1, Z), "&
"73 (BC_BIDIR, C2D(3) , bidir , X, 77, 1, Z), "&
"74 (BC_BIDIR, C2D(2) , bidir , X, 77, 1, Z), "&
"75 (BC_BIDIR, C2D(1) , bidir , X, 77, 1, Z), "&
"76 (BC_BIDIR, C2D(0) , bidir , X, 77, 1, Z), "&
"77 (BC_1 , * , control, 1 ), "&
"78 (BC_1 , * , control, 1 ), "&
"79 (BC_BIDIR, CRDY_NEG(3) , bidir , X, 78, 1, Z), "&
"80 (BC_1 , * , control, 1 ), "&
"81 (BC_BIDIR, CSTRB_NEG(3), bidir , X, 80, 1, Z), "&
"82 (BC_1 , * , control, 1 ), "&
"83 (BC_BIDIR, CACK_NEG(3) , bidir , X, 82, 1, Z), "&
"84 (BC_1 , * , control, 1 ), "&
"85 (BC_BIDIR, CREQ_NEG(3) , bidir , X, 84, 1, Z), "&
"86 (BC_1 , * , control, 1 ), "&
"87 (BC_BIDIR, CRDY_NEG(2) , bidir , X, 86, 1, Z), "&
"88 (BC_1 , * , control, 1 ), "&
"89 (BC_BIDIR, CSTRB_NEG(2), bidir , X, 88, 1, Z), "&
"90 (BC_1 , * , control, 1 ), "&
"91 (BC_BIDIR, CACK_NEG(2) , bidir , X, 90, 1, Z), "&
"92 (BC_1 , * , control, 1 ), "&
"93 (BC_BIDIR, CREQ_NEG(2) , bidir , X, 92, 1, Z), "&
"94 (BC_1 , * , control, 1 ), "&
"95 (BC_BIDIR, CRDY_NEG(1) , bidir , X, 94, 1, Z), "&
"96 (BC_1 , * , control, 1 ), "&
"97 (BC_BIDIR, CSTRB_NEG(1), bidir , X, 96, 1, Z), "&
"98 (BC_1 , * , control, 1 ), "&
"99 (BC_BIDIR, CACK_NEG(1) , bidir , X, 98, 1, Z), "&
"100 (BC_1 , * , control, 1 ), "&
"101 (BC_BIDIR, CREQ_NEG(1) , bidir , X, 100, 1, Z), "&
"102 (BC_1 , * , control, 1 ), "&
"103 (BC_BIDIR, CRDY_NEG(0) , bidir , X, 102, 1, Z), "&
"104 (BC_1 , * , control, 1 ), "&
"105 (BC_BIDIR, CSTRB_NEG(0), bidir , X, 104, 1, Z), "&
"106 (BC_1 , * , control, 1 ), "&
"107 (BC_BIDIR, CACK_NEG(0) , bidir , X, 106, 1, Z), "&
"108 (BC_1 , * , control, 1 ), "&
"109 (BC_BIDIR, CREQ_NEG(0) , bidir , X, 108, 1, Z), "&
"110 (BC_BIDIR, C1D(7) , bidir , X, 118, 1, Z), "&
"111 (BC_BIDIR, C1D(6) , bidir , X, 118, 1, Z), "&
"112 (BC_BIDIR, C1D(5) , bidir , X, 118, 1, Z), "&
"113 (BC_BIDIR, C1D(4) , bidir , X, 118, 1, Z), "&
"114 (BC_BIDIR, C1D(3) , bidir , X, 118, 1, Z), "&
"115 (BC_BIDIR, C1D(2) , bidir , X, 118, 1, Z), "&
"116 (BC_BIDIR, C1D(1) , bidir , X, 118, 1, Z), "&
"117 (BC_BIDIR, C1D(0) , bidir , X, 118, 1, Z), "&
"118 (BC_1 , * , control, 1 ), "&
"119 (BC_BIDIR, C0D(7) , bidir , X, 127, 1, Z), "&
"120 (BC_BIDIR, C0D(6) , bidir , X, 127, 1, Z), "&
"121 (BC_BIDIR, C0D(5) , bidir , X, 127, 1, Z), "&
"122 (BC_BIDIR, C0D(4) , bidir , X, 127, 1, Z), "&
"123 (BC_BIDIR, C0D(3) , bidir , X, 127, 1, Z), "&
"124 (BC_BIDIR, C0D(2) , bidir , X, 127, 1, Z), "&
"125 (BC_BIDIR, C0D(1) , bidir , X, 127, 1, Z), "&
"126 (BC_BIDIR, C0D(0) , bidir , X, 127, 1, Z), "&
"127 (BC_1 , * , control, 1 ), "&
"128 (BC_1 , ROMEN , input , X ), "&
"129 (BC_1 , * , control, 1 ), "&
"130 (BC_BIDIR, IIOF(0) , bidir , X, 129, 1, Z), "&
"131 (BC_1 , * , control, 1 ), "&
"132 (BC_BIDIR, IIOF(1) , bidir , X, 131, 1, Z), "&
"133 (BC_1 , * , control, 1 ), "&
"134 (BC_BIDIR, IIOF(2) , bidir , X, 133, 1, Z), "&
"135 (BC_1 , * , control, 1 ), "&
"136 (BC_BIDIR, IIOF(3) , bidir , X, 135, 1, Z), "&
"137 (BC_1 , NMI_NEG , input , X ), "&
"138 (BC_1 , * , control, 1 ), "&
"139 (BC_1 , LSTRB_NEG(0), output3, X, 138, 1, Z), "&
"140 (BC_1 , * , control, 1 ), "&
"141 (BC_1 , LR_W_NEG(0) , output3, X, 140, 1, Z), "&
"142 (BC_1 , * , control, 1 ), "&
"143 (BC_1 , LPAGE(0) , output3, X, 142, 1, Z), "&
"144 (BC_1 , LRDY_NEG(0) , input , X ), "&
"145 (BC_1 , LCE_NEG(0) , input , X ), "&
"146 (BC_1 , * , control, 1 ), "&
"147 (BC_1 , LSTRB_NEG(1), output3, X, 146, 1, Z), "&
"148 (BC_1 , * , control, 1 ), "&
"149 (BC_1 , LR_W_NEG(1) , output3, X, 148, 1, Z), "&
"150 (BC_1 , * , control, 1 ), "&
"151 (BC_1 , LPAGE(1) , output3, X, 150, 1, Z), "&
"152 (BC_1 , LRDY_NEG(1) , input , X ), "&
"153 (BC_1 , LCE_NEG(1) , input , X ), "&
"154 (BC_1 , LDE_NEG , input , X ), "&
"155 (BC_1 , * , control, 1 ), "&
"156 (BC_BIDIR, TCLK(0) , bidir , X, 155, 1, Z), "&
"157 (BC_1 , * , control, 1 ), "&
"158 (BC_BIDIR, TCLK(1) , bidir , X, 157, 1, Z), "&
"159 (BC_1 , H3 , output3, X, 169, 1, Z), "&
"160 (BC_1 , H1 , output3, X, 169, 1, Z), "&
"161 (BC_1 , LAE_NEG , input , X ), "&
"162 (BC_1 , LLOCK_NEG , output3, X, 167, 1, Z), "&
"163 (BC_1 , LSTAT(0) , output3, X, 167, 1, Z), "&
"164 (BC_1 , LSTAT(1) , output3, X, 167, 1, Z), "&
"165 (BC_1 , LSTAT(2) , output3, X, 167, 1, Z), "&
"166 (BC_1 , LSTAT(3) , output3, X, 167, 1, Z), "&
"167 (BC_1 , * , control, 1 ), "&
"168 (BC_1 , IACK_NEG , output3, X, 169, 1, Z), "&
"169 (BC_1 , * , control, 1 ), "&
"170 (BC_1 , LA(30) , output3, X, 201, 1, Z), "&
"171 (BC_1 , LA(29) , output3, X, 201, 1, Z), "&
"172 (BC_1 , LA(28) , output3, X, 201, 1, Z), "&
"173 (BC_1 , LA(27) , output3, X, 201, 1, Z), "&
"174 (BC_1 , LA(26) , output3, X, 201, 1, Z), "&
"175 (BC_1 , LA(25) , output3, X, 201, 1, Z), "&
"176 (BC_1 , LA(24) , output3, X, 201, 1, Z), "&
"177 (BC_1 , LA(23) , output3, X, 201, 1, Z), "&
"178 (BC_1 , LA(22) , output3, X, 201, 1, Z), "&
"179 (BC_1 , LA(21) , output3, X, 201, 1, Z), "&
"180 (BC_1 , LA(20) , output3, X, 201, 1, Z), "&
"181 (BC_1 , LA(19) , output3, X, 201, 1, Z), "&
"182 (BC_1 , LA(18) , output3, X, 201, 1, Z), "&
"183 (BC_1 , LA(17) , output3, X, 201, 1, Z), "&
"184 (BC_1 , LA(16) , output3, X, 201, 1, Z), "&
"185 (BC_1 , LA(15) , output3, X, 201, 1, Z), "&
"186 (BC_1 , LA(14) , output3, X, 201, 1, Z), "&
"187 (BC_1 , LA(13) , output3, X, 201, 1, Z), "&
"188 (BC_1 , LA(12) , output3, X, 201, 1, Z), "&
"189 (BC_1 , LA(11) , output3, X, 201, 1, Z), "&
"190 (BC_1 , LA(10) , output3, X, 201, 1, Z), "&
"191 (BC_1 , LA(9) , output3, X, 201, 1, Z), "&
"192 (BC_1 , LA(8) , output3, X, 201, 1, Z), "&
"193 (BC_1 , LA(7) , output3, X, 201, 1, Z), "&
"194 (BC_1 , LA(6) , output3, X, 201, 1, Z), "&
"195 (BC_1 , LA(5) , output3, X, 201, 1, Z), "&
"196 (BC_1 , LA(4) , output3, X, 201, 1, Z), "&
"197 (BC_1 , LA(3) , output3, X, 201, 1, Z), "&
"198 (BC_1 , LA(2) , output3, X, 201, 1, Z), "&
"199 (BC_1 , LA(1) , output3, X, 201, 1, Z), "&
"200 (BC_1 , LA(0) , output3, X, 201, 1, Z), "&
"201 (BC_1 , * , control, 1 ), "&
"202 (BC_BIDIR, LD(31) , bidir , X, 234, 1, Z), "&
"203 (BC_BIDIR, LD(30) , bidir , X, 234, 1, Z), "&
"204 (BC_BIDIR, LD(29) , bidir , X, 234, 1, Z), "&
"205 (BC_BIDIR, LD(28) , bidir , X, 234, 1, Z), "&
"206 (BC_BIDIR, LD(27) , bidir , X, 234, 1, Z), "&
"207 (BC_BIDIR, LD(26) , bidir , X, 234, 1, Z), "&
"208 (BC_BIDIR, LD(25) , bidir , X, 234, 1, Z), "&
"209 (BC_BIDIR, LD(24) , bidir , X, 234, 1, Z), "&
"210 (BC_BIDIR, LD(23) , bidir , X, 234, 1, Z), "&
"211 (BC_BIDIR, LD(22) , bidir , X, 234, 1, Z), "&
"212 (BC_BIDIR, LD(21) , bidir , X, 234, 1, Z), "&
"213 (BC_BIDIR, LD(20) , bidir , X, 234, 1, Z), "&
"214 (BC_BIDIR, LD(19) , bidir , X, 234, 1, Z), "&
"215 (BC_BIDIR, LD(18) , bidir , X, 234, 1, Z), "&
"216 (BC_BIDIR, LD(17) , bidir , X, 234, 1, Z), "&
"217 (BC_BIDIR, LD(16) , bidir , X, 234, 1, Z), "&
"218 (BC_BIDIR, LD(15) , bidir , X, 234, 1, Z), "&
"219 (BC_BIDIR, LD(14) , bidir , X, 234, 1, Z), "&
"220 (BC_BIDIR, LD(13) , bidir , X, 234, 1, Z), "&
"221 (BC_BIDIR, LD(12) , bidir , X, 234, 1, Z), "&
"222 (BC_BIDIR, LD(11) , bidir , X, 234, 1, Z), "&
"223 (BC_BIDIR, LD(10) , bidir , X, 234, 1, Z), "&
"224 (BC_BIDIR, LD(9) , bidir , X, 234, 1, Z), "&
"225 (BC_BIDIR, LD(8) , bidir , X, 234, 1, Z), "&
"226 (BC_BIDIR, LD(7) , bidir , X, 234, 1, Z), "&
"227 (BC_BIDIR, LD(6) , bidir , X, 234, 1, Z), "&
"228 (BC_BIDIR, LD(5) , bidir , X, 234, 1, Z), "&
"229 (BC_BIDIR, LD(4) , bidir , X, 234, 1, Z), "&
"230 (BC_BIDIR, LD(3) , bidir , X, 234, 1, Z), "&
"231 (BC_BIDIR, LD(2) , bidir , X, 234, 1, Z), "&
"232 (BC_BIDIR, LD(1) , bidir , X, 234, 1, Z), "&
"233 (BC_BIDIR, LD(0) , bidir , X, 234, 1, Z), "&
"234 (BC_1 , * , control, 1 ), "&
"235 (BC_1 , A(30) , output3, X, 266, 1, Z), "&
"236 (BC_1 , A(29) , output3, X, 266, 1, Z), "&
"237 (BC_1 , A(28) , output3, X, 266, 1, Z), "&
"238 (BC_1 , A(27) , output3, X, 266, 1, Z), "&
"239 (BC_1 , A(26) , output3, X, 266, 1, Z), "&
"240 (BC_1 , A(25) , output3, X, 266, 1, Z), "&
"241 (BC_1 , A(24) , output3, X, 266, 1, Z), "&
"242 (BC_1 , A(23) , output3, X, 266, 1, Z), "&
"243 (BC_1 , A(22) , output3, X, 266, 1, Z), "&
"244 (BC_1 , A(21) , output3, X, 266, 1, Z), "&
"245 (BC_1 , A(20) , output3, X, 266, 1, Z), "&
"246 (BC_1 , A(19) , output3, X, 266, 1, Z), "&
"247 (BC_1 , A(18) , output3, X, 266, 1, Z), "&
"248 (BC_1 , A(17) , output3, X, 266, 1, Z), "&
"249 (BC_1 , A(16) , output3, X, 266, 1, Z), "&
"250 (BC_1 , A(15) , output3, X, 266, 1, Z), "&
"251 (BC_1 , A(14) , output3, X, 266, 1, Z), "&
"252 (BC_1 , A(13) , output3, X, 266, 1, Z), "&
"253 (BC_1 , A(12) , output3, X, 266, 1, Z), "&
"254 (BC_1 , A(11) , output3, X, 266, 1, Z), "&
"255 (BC_1 , A(10) , output3, X, 266, 1, Z), "&
"256 (BC_1 , A(9) , output3, X, 266, 1, Z), "&
"257 (BC_1 , A(8) , output3, X, 266, 1, Z), "&
"258 (BC_1 , A(7) , output3, X, 266, 1, Z), "&
"259 (BC_1 , A(6) , output3, X, 266, 1, Z), "&
"260 (BC_1 , A(5) , output3, X, 266, 1, Z), "&
"261 (BC_1 , A(4) , output3, X, 266, 1, Z), "&
"262 (BC_1 , A(3) , output3, X, 266, 1, Z), "&
"263 (BC_1 , A(2) , output3, X, 266, 1, Z), "&
"264 (BC_1 , A(1) , output3, X, 266, 1, Z), "&
"265 (BC_1 , A(0) , output3, X, 266, 1, Z), "&
"266 (BC_1 , * , control, 1 ), "&
"267 (BC_BIDIR, D(31) , bidir , X, 299, 1, Z), "&
"268 (BC_BIDIR, D(30) , bidir , X, 299, 1, Z), "&
"269 (BC_BIDIR, D(29) , bidir , X, 299, 1, Z), "&
"270 (BC_BIDIR, D(28) , bidir , X, 299, 1, Z), "&
"271 (BC_BIDIR, D(27) , bidir , X, 299, 1, Z), "&
"272 (BC_BIDIR, D(26) , bidir , X, 299, 1, Z), "&
"273 (BC_BIDIR, D(25) , bidir , X, 299, 1, Z), "&
"274 (BC_BIDIR, D(24) , bidir , X, 299, 1, Z), "&
"275 (BC_BIDIR, D(23) , bidir , X, 299, 1, Z), "&
"276 (BC_BIDIR, D(22) , bidir , X, 299, 1, Z), "&
"277 (BC_BIDIR, D(21) , bidir , X, 299, 1, Z), "&
"278 (BC_BIDIR, D(20) , bidir , X, 299, 1, Z), "&
"279 (BC_BIDIR, D(19) , bidir , X, 299, 1, Z), "&
"280 (BC_BIDIR, D(18) , bidir , X, 299, 1, Z), "&
"281 (BC_BIDIR, D(17) , bidir , X, 299, 1, Z), "&
"282 (BC_BIDIR, D(16) , bidir , X, 299, 1, Z), "&
"283 (BC_BIDIR, D(15) , bidir , X, 299, 1, Z), "&
"284 (BC_BIDIR, D(14) , bidir , X, 299, 1, Z), "&
"285 (BC_BIDIR, D(13) , bidir , X, 299, 1, Z), "&
"286 (BC_BIDIR, D(12) , bidir , X, 299, 1, Z), "&
"287 (BC_BIDIR, D(11) , bidir , X, 299, 1, Z), "&
"288 (BC_BIDIR, D(10) , bidir , X, 299, 1, Z), "&
"289 (BC_BIDIR, D(9) , bidir , X, 299, 1, Z), "&
"290 (BC_BIDIR, D(8) , bidir , X, 299, 1, Z), "&
"291 (BC_BIDIR, D(7) , bidir , X, 299, 1, Z), "&
"292 (BC_BIDIR, D(6) , bidir , X, 299, 1, Z), "&
"293 (BC_BIDIR, D(5) , bidir , X, 299, 1, Z), "&
"294 (BC_BIDIR, D(4) , bidir , X, 299, 1, Z), "&
"295 (BC_BIDIR, D(3) , bidir , X, 299, 1, Z), "&
"296 (BC_BIDIR, D(2) , bidir , X, 299, 1, Z), "&
"297 (BC_BIDIR, D(1) , bidir , X, 299, 1, Z), "&
"298 (BC_BIDIR, D(0) , bidir , X, 299, 1, Z), "&
"299 (BC_1 , * , control, 1 ), "&
"300 (BC_1 , CE_NEG(1) , input , X ), "&
"301 (BC_1 , RDY_NEG(1) , input , X ), "&
"302 (BC_1 , LOCK_NEG , output3, X, 15, 1, Z), "&
"303 (BC_1 , CE_NEG(0) , input , X ), "&
"304 (BC_1 , RDY_NEG(0) , input , X ), "&
"305 (BC_1 , DE_NEG , input , X ) ";
end tms320c40;
