----------------------------------------------------------------------
-- Filename: VSC7558_v0.1.bsdl --
-- Version: 0.1 --
-- Date: Jul 03 2020 --
-- Chip: VSC7558 --
-- Project: --
-- Generated by: jsa (Jorgen Abrahamsen) --
-- Notes: --
-- THIS FILE IS AUTO-GENERATED! --
-- IF YOU FIND ANY ERRORS OR EMMISIONS, PLEASE --
-- CONTACT THE PERSON LISTED ABOVE. --
-- --
-- Note. The following pins may not be toggled during JTAG test: --
-- JTAG_SEL_0, JTAG_SEL_0. --
-- JTAG_SEL_0, JTAG_SEL_0 must be driven HIGH during test. --
-- --
----------------------------------------------------------------------
-- [DISCLAIMER] --
-- Absolutely no guarantees, for modeling purposes only --
-- --
-- (C) Copyright Microchip Corporation 2020 --
-- All Rights Reserved --
-- --
-- --
-- Microchip Corporation hereby grants the user of this BSDL --
-- model a non-exclusive, nontransferable license to use this --
-- BSDL model under the following terms. --
-- Before using this BSDL model, the user should read this --
-- license. If the user does not accept these terms, the --
-- BSDL model should be returned to Microchip within 30 days. --
-- --
-- The user is granted this license only to use the --
-- BSDL model and is not granted rights to sell, load, rent, --
-- lease or license the BSDL model in whole or in part, or in --
-- modified form to anyone other than user. User may modify --
-- the BSDL model to suit its specific applications but rights --
-- to derivative works and such modifications shall belong to --
-- Vitesse. --
-- --
-- This BSDL model is provided on an "AS IS" basis and --
-- Microchip makes absolutely no warranty with respect to the --
-- information contained herein. --
-- MICROCHIP DISCLAIMS AND CUSTOMER WAIVES ALL WARRANTIES, --
-- EXPRESS OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY --
-- OR FITNESS FOR A PARTICULAR PURPOSE. --
-- The entire risk as to quality and performance is with the --
-- Customer. --
-- ACCORDINGLY, IN NO EVENT SHALL THE COMPANY BE LIABLE FOR --
-- ANY DAMAGES, WHETHER IN CONTRACT OR TORT,INCLUDING ANY LOST --
-- PROFITS OR OTHER INCIDENTAL,CONSEQUENTIAL, EXEMPLARY, OR --
-- PUNITIVE DAMAGES ARISING OUT OF THE USE OR APPLICATION OF --
-- THE BSDL MODEL PROVIDED IN THIS PACKAGE. --
-- Further, Microchip reserves the right to make changes without --
-- notice to any product herein to improve reliability, --
-- function, or design. Microchip does not convey any license --
-- under patent rights or any other intellectual property --
-- rights, including those of third parties. --
-- --
-- Microchip is not obligated to provide maintenance or support --
-- for the licensed BSDL model. --
-- --
-- [Copyright] Microchip Inc. --
----------------------------------------------------------------------
-- Generated by Tessent Shell 2018.2 Wed May 16 20:56:02 GMT 2018 on 10/29/18 09:41:15
-- BSDL Version 2001
----------------------------------------------------------------------
entity VSC7558 is
generic (PHYSICAL_PIN_MAP : string := "BGA888");
port (
-- Port List
nRESET : in bit;
RESERVED_0 : linkage bit;
S0_TXP : buffer bit;
S1_TXP : buffer bit;
S2_TXP : buffer bit;
S3_TXP : buffer bit;
S4_TXP : buffer bit;
S5_TXP : buffer bit;
S6_TXP : buffer bit;
S7_TXP : buffer bit;
S8_TXP : buffer bit;
S9_TXP : buffer bit;
S10_TXP : buffer bit;
S11_TXP : buffer bit;
S12_TXP : buffer bit;
S0_TXN : buffer bit;
S1_TXN : buffer bit;
S2_TXN : buffer bit;
S3_TXN : buffer bit;
S4_TXN : buffer bit;
S5_TXN : buffer bit;
S6_TXN : buffer bit;
S7_TXN : buffer bit;
S8_TXN : buffer bit;
S9_TXN : buffer bit;
S10_TXN : buffer bit;
S11_TXN : buffer bit;
S12_TXN : buffer bit;
S0_RXN : in bit;
S1_RXN : in bit;
S2_RXN : in bit;
S3_RXN : in bit;
S4_RXN : in bit;
S5_RXN : in bit;
S6_RXN : in bit;
S7_RXN : in bit;
S8_RXN : in bit;
S9_RXN : in bit;
S10_RXN : in bit;
S11_RXN : in bit;
S12_RXN : in bit;
S0_RXP : in bit;
S1_RXP : in bit;
S2_RXP : in bit;
S3_RXP : in bit;
S4_RXP : in bit;
S5_RXP : in bit;
S6_RXP : in bit;
S7_RXP : in bit;
S8_RXP : in bit;
S9_RXP : in bit;
S10_RXP : in bit;
S11_RXP : in bit;
S12_RXP : in bit;
S13_TXP : buffer bit;
S14_TXP : buffer bit;
S15_TXP : buffer bit;
S16_TXP : buffer bit;
S17_TXP : buffer bit;
S18_TXP : buffer bit;
S19_TXP : buffer bit;
S20_TXP : buffer bit;
S21_TXP : buffer bit;
S22_TXP : buffer bit;
S23_TXP : buffer bit;
S24_TXP : buffer bit;
S25_TXP : buffer bit;
S26_TXP : buffer bit;
S27_TXP : buffer bit;
S28_TXP : buffer bit;
S29_TXP : buffer bit;
S30_TXP : buffer bit;
S31_TXP : buffer bit;
S32_TXP : buffer bit;
S13_TXN : buffer bit;
S14_TXN : buffer bit;
S15_TXN : buffer bit;
S16_TXN : buffer bit;
S17_TXN : buffer bit;
S18_TXN : buffer bit;
S19_TXN : buffer bit;
S20_TXN : buffer bit;
S21_TXN : buffer bit;
S22_TXN : buffer bit;
S23_TXN : buffer bit;
S24_TXN : buffer bit;
S25_TXN : buffer bit;
S26_TXN : buffer bit;
S27_TXN : buffer bit;
S28_TXN : buffer bit;
S29_TXN : buffer bit;
S30_TXN : buffer bit;
S31_TXN : buffer bit;
S32_TXN : buffer bit;
S13_RXN : in bit;
S14_RXN : in bit;
S15_RXN : in bit;
S16_RXN : in bit;
S17_RXN : in bit;
S18_RXN : in bit;
S19_RXN : in bit;
S20_RXN : in bit;
S21_RXN : in bit;
S22_RXN : in bit;
S23_RXN : in bit;
S24_RXN : in bit;
S25_RXN : in bit;
S26_RXN : in bit;
S27_RXN : in bit;
S28_RXN : in bit;
S29_RXN : in bit;
S30_RXN : in bit;
S31_RXN : in bit;
S32_RXN : in bit;
S13_RXP : in bit;
S14_RXP : in bit;
S15_RXP : in bit;
S16_RXP : in bit;
S17_RXP : in bit;
S18_RXP : in bit;
S19_RXP : in bit;
S20_RXP : in bit;
S21_RXP : in bit;
S22_RXP : in bit;
S23_RXP : in bit;
S24_RXP : in bit;
S25_RXP : in bit;
S26_RXP : in bit;
S27_RXP : in bit;
S28_RXP : in bit;
S29_RXP : in bit;
S30_RXP : in bit;
S31_RXP : in bit;
S32_RXP : in bit;
PCIE_TXP : buffer bit;
PCIE_TXN : buffer bit;
PCIE_RXP : in bit;
PCIE_RXN : in bit;
RESERVED_5 : linkage bit;
RESERVED_6 : linkage bit;
REFCLK0_P : linkage bit;
REFCLK0_N : linkage bit;
REFCLK1_P : linkage bit;
REFCLK1_N : linkage bit;
REFCLK3_P : linkage bit;
REFCLK3_N : linkage bit;
RESERVED_9 : linkage bit;
RESERVED_7 : linkage bit;
REFCLK2_N : linkage bit;
REFCLK2_P : linkage bit;
RESERVED_8 : linkage bit;
JTAG_TCK : in bit;
JTAG_TDI : in bit;
JTAG_TDO : out bit;
JTAG_TMS : in bit;
JTAG_nTRST : in bit;
JTAG_CPU_nRST : linkage bit;
JTAG_SEL0 : linkage bit;
JTAG_SEL1 : linkage bit;
THERMDA : linkage bit;
THERMDC : linkage bit;
RESERVED_1 : linkage bit;
SI_CLK : inout bit;
SI_D0 : inout bit;
SI_D1 : inout bit;
SI_nCS0 : inout bit;
MDC0 : inout bit;
MDIO0 : inout bit;
GPIO_0 : inout bit;
GPIO_1 : inout bit;
GPIO_2 : inout bit;
GPIO_3 : inout bit;
GPIO_4 : inout bit;
GPIO_5 : inout bit;
GPIO_6 : inout bit;
GPIO_7 : inout bit;
GPIO_8 : inout bit;
GPIO_9 : inout bit;
GPIO_10 : inout bit;
GPIO_11 : inout bit;
GPIO_12 : inout bit;
GPIO_13 : inout bit;
GPIO_14 : inout bit;
GPIO_15 : inout bit;
GPIO_16 : inout bit;
GPIO_17 : inout bit;
GPIO_18 : inout bit;
GPIO_19 : inout bit;
GPIO_20 : inout bit;
GPIO_21 : inout bit;
GPIO_22 : inout bit;
GPIO_23 : inout bit;
GPIO_24 : inout bit;
GPIO_25 : inout bit;
GPIO_26 : inout bit;
GPIO_27 : inout bit;
GPIO_28 : inout bit;
GPIO_29 : inout bit;
GPIO_30 : inout bit;
GPIO_31 : inout bit;
GPIO_32 : inout bit;
GPIO_33 : inout bit;
GPIO_34 : inout bit;
GPIO_35 : inout bit;
GPIO_36 : inout bit;
GPIO_37 : inout bit;
GPIO_38 : inout bit;
GPIO_39 : inout bit;
GPIO_40 : inout bit;
GPIO_41 : inout bit;
GPIO_42 : inout bit;
GPIO_43 : inout bit;
GPIO_44 : inout bit;
GPIO_45 : inout bit;
GPIO_46 : inout bit;
GPIO_47 : inout bit;
GPIO_48 : inout bit;
GPIO_49 : inout bit;
GPIO_50 : inout bit;
GPIO_51 : inout bit;
GPIO_52 : inout bit;
GPIO_53 : inout bit;
GPIO_54 : inout bit;
GPIO_55 : inout bit;
GPIO_56 : inout bit;
GPIO_57 : inout bit;
GPIO_58 : inout bit;
GPIO_59 : inout bit;
GPIO_60 : inout bit;
GPIO_61 : inout bit;
GPIO_62 : inout bit;
GPIO_63 : inout bit;
DDR_RESETn : inout bit;
DDR_CK_t : inout bit;
DDR_CK_c : inout bit;
DDR_CKE1 : inout bit;
DDR_CKE0 : inout bit;
DDR_ODT1 : inout bit;
DDR_ODT0 : inout bit;
DDR_CS_n1 : inout bit;
DDR_CS_n0 : inout bit;
DDR_ACT_n : inout bit;
DDR_BG1 : inout bit;
DDR_BG0 : inout bit;
DDR_BA1 : inout bit;
DDR_BA0 : inout bit;
DDR_A17 : inout bit;
DDR_A16 : inout bit;
DDR_A15 : inout bit;
DDR_A14 : inout bit;
DDR_A13 : inout bit;
DDR_A12 : inout bit;
DDR_A11 : inout bit;
DDR_A10 : inout bit;
DDR_A9 : inout bit;
DDR_A8 : inout bit;
DDR_A7 : inout bit;
DDR_A6 : inout bit;
DDR_A5 : inout bit;
DDR_A4 : inout bit;
DDR_A3 : inout bit;
DDR_A2 : inout bit;
DDR_A1 : inout bit;
DDR_A0 : inout bit;
DDR_PAR : inout bit;
DDR_ALERT_n : inout bit;
DDR_DQS_t4 : inout bit;
DDR_DQS_t3 : inout bit;
DDR_DQS_t2 : inout bit;
DDR_DQS_t1 : inout bit;
DDR_DQS_t0 : inout bit;
DDR_DQS_c4 : inout bit;
DDR_DQS_c3 : inout bit;
DDR_DQS_c2 : inout bit;
DDR_DQS_c1 : inout bit;
DDR_DQS_c0 : inout bit;
DDR_DM4 : inout bit;
DDR_DM3 : inout bit;
DDR_DM2 : inout bit;
DDR_DM1 : inout bit;
DDR_DM0 : inout bit;
DDR_DQ39 : inout bit;
DDR_DQ38 : inout bit;
DDR_DQ37 : inout bit;
DDR_DQ36 : inout bit;
DDR_DQ35 : inout bit;
DDR_DQ34 : inout bit;
DDR_DQ33 : inout bit;
DDR_DQ32 : inout bit;
DDR_DQ31 : inout bit;
DDR_DQ30 : inout bit;
DDR_DQ29 : inout bit;
DDR_DQ28 : inout bit;
DDR_DQ27 : inout bit;
DDR_DQ26 : inout bit;
DDR_DQ25 : inout bit;
DDR_DQ24 : inout bit;
DDR_DQ23 : inout bit;
DDR_DQ22 : inout bit;
DDR_DQ21 : inout bit;
DDR_DQ20 : inout bit;
DDR_DQ19 : inout bit;
DDR_DQ18 : inout bit;
DDR_DQ17 : inout bit;
DDR_DQ16 : inout bit;
DDR_DQ15 : inout bit;
DDR_DQ14 : inout bit;
DDR_DQ13 : inout bit;
DDR_DQ12 : inout bit;
DDR_DQ11 : inout bit;
DDR_DQ10 : inout bit;
DDR_DQ9 : inout bit;
DDR_DQ8 : inout bit;
DDR_DQ7 : inout bit;
DDR_DQ6 : inout bit;
DDR_DQ5 : inout bit;
DDR_DQ4 : inout bit;
DDR_DQ3 : inout bit;
DDR_DQ2 : inout bit;
DDR_DQ1 : inout bit;
DDR_DQ0 : inout bit;
DDR_RZQ : linkage bit;
RESERVED_2 : linkage bit;
RESERVED_4 : out bit;
RESERVED_3 : out bit;
-- NoBall : linkage bit_vector(1 to 12);
VDD : linkage bit_vector(1 to 112);
VDDH18 : linkage bit_vector(1 to 14);
VDDHS2 : linkage bit_vector(1 to 16);
VDDHS : linkage bit_vector(1 to 34);
VDDHV2 : linkage bit_vector(1 to 4);
VDDHV : linkage bit_vector(1 to 10);
VDDIO18 : linkage bit_vector(1 to 6);
VDDIO33 : linkage bit_vector(1 to 19);
VDDIODDR : linkage bit_vector(1 to 12);
VDDPLLDDR : linkage bit_vector(1 to 4);
VSS : linkage bit_vector(1 to 328);
DDR_ZCTRL : linkage bit;
DDR_VREFODQ : linkage bit;
DDR_VREFOCA : linkage bit;
RESERVED_10 : linkage bit);
use STD_1149_1_2001.all;
-- use TS_BSCAN_CELLS.all;
attribute COMPONENT_CONFORMANCE of VSC7558: entity is "STD_1149_1_2001";
--Pin mappings
attribute PIN_MAP of VSC7558: entity is PHYSICAL_PIN_MAP;
constant BGA888: PIN_MAP_STRING :=
"nRESET: K1, " &
"RESERVED_0: K4, " &
"S0_TXP: AJ6, " &
"S1_TXP: AH7, " &
"S2_TXP: AJ8, " &
"S3_TXP: AH9, " &
"S4_TXP: AJ10, " &
"S5_TXP: AH11, " &
"S6_TXP: AJ12, " &
"S7_TXP: AH13, " &
"S8_TXP: AJ14, " &
"S9_TXP: AH15, " &
"S10_TXP: AJ16, " &
"S11_TXP: AH17, " &
"S12_TXP: AJ18, " &
"S0_TXN: AK6, " &
"S1_TXN: AJ7, " &
"S2_TXN: AK8, " &
"S3_TXN: AJ9, " &
"S4_TXN: AK10, " &
"S5_TXN: AJ11, " &
"S6_TXN: AK12, " &
"S7_TXN: AJ13, " &
"S8_TXN: AK14, " &
"S9_TXN: AJ15, " &
"S10_TXN: AK16, " &
"S11_TXN: AJ17, " &
"S12_TXN: AK18, " &
"S0_RXN: AG6, " &
"S1_RXN: AF7, " &
"S2_RXN: AG8, " &
"S3_RXN: AF9, " &
"S4_RXN: AG10, " &
"S5_RXN: AF11, " &
"S6_RXN: AG12, " &
"S7_RXN: AF13, " &
"S8_RXN: AG14, " &
"S9_RXN: AF15, " &
"S10_RXN: AG16, " &
"S11_RXN: AF17, " &
"S12_RXN: AG18, " &
"S0_RXP: AF6, " &
"S1_RXP: AE7, " &
"S2_RXP: AF8, " &
"S3_RXP: AE9, " &
"S4_RXP: AF10, " &
"S5_RXP: AE11, " &
"S6_RXP: AF12, " &
"S7_RXP: AE13, " &
"S8_RXP: AF14, " &
"S9_RXP: AE15, " &
"S10_RXP: AF16, " &
"S11_RXP: AE17, " &
"S12_RXP: AF18, " &
"S13_TXP: AJ20, " &
"S14_TXP: AH21, " &
"S15_TXP: AJ22, " &
"S16_TXP: AH23, " &
"S17_TXP: C24, " &
"S18_TXP: B23, " &
"S19_TXP: C22, " &
"S20_TXP: B21, " &
"S21_TXP: C20, " &
"S22_TXP: B19, " &
"S23_TXP: C18, " &
"S24_TXP: B17, " &
"S25_TXP: B15, " &
"S26_TXP: B13, " &
"S27_TXP: B11, " &
"S28_TXP: B9, " &
"S29_TXP: B7, " &
"S30_TXP: B5, " &
"S31_TXP: B3, " &
"S32_TXP: B1, " &
"S13_TXN: AK20, " &
"S14_TXN: AJ21, " &
"S15_TXN: AK22, " &
"S16_TXN: AJ23, " &
"S17_TXN: B24, " &
"S18_TXN: A23, " &
"S19_TXN: B22, " &
"S20_TXN: A21, " &
"S21_TXN: B20, " &
"S22_TXN: A19, " &
"S23_TXN: B18, " &
"S24_TXN: A17, " &
"S25_TXN: A15, " &
"S26_TXN: A13, " &
"S27_TXN: A11, " &
"S28_TXN: A9, " &
"S29_TXN: A7, " &
"S30_TXN: A5, " &
"S31_TXN: A3, " &
"S32_TXN: A1, " &
"S13_RXN: AG20, " &
"S14_RXN: AF21, " &
"S15_RXN: AG22, " &
"S16_RXN: AF23, " &
"S17_RXN: E24, " &
"S18_RXN: D23, " &
"S19_RXN: E22, " &
"S20_RXN: D21, " &
"S21_RXN: E20, " &
"S22_RXN: D19, " &
"S23_RXN: E18, " &
"S24_RXN: D17, " &
"S25_RXN: D15, " &
"S26_RXN: D13, " &
"S27_RXN: D11, " &
"S28_RXN: D9, " &
"S29_RXN: D7, " &
"S30_RXN: D5, " &
"S31_RXN: D3, " &
"S32_RXN: D1, " &
"S13_RXP: AF20, " &
"S14_RXP: AE21, " &
"S15_RXP: AF22, " &
"S16_RXP: AE23, " &
"S17_RXP: F24, " &
"S18_RXP: E23, " &
"S19_RXP: F22, " &
"S20_RXP: E21, " &
"S21_RXP: F20, " &
"S22_RXP: E19, " &
"S23_RXP: F18, " &
"S24_RXP: E17, " &
"S25_RXP: E15, " &
"S26_RXP: E13, " &
"S27_RXP: E11, " &
"S28_RXP: E9, " &
"S29_RXP: E7, " &
"S30_RXP: E5, " &
"S31_RXP: E3, " &
"S32_RXP: E1, " &
"PCIE_TXP: B26, " &
"PCIE_TXN: A26, " &
"PCIE_RXP: B28, " &
"PCIE_RXN: A28, " &
"RESERVED_5: AF26, " &
"RESERVED_6: J2, " &
"REFCLK0_P: AJ30, " &
"REFCLK0_N: AK30, " &
"REFCLK1_P: AG5, " &
"REFCLK1_N: AH5, " &
"REFCLK3_P: B30, " &
"REFCLK3_N: A30, " &
"RESERVED_9: AE4, " &
"RESERVED_7: D29, " &
"REFCLK2_N: G1, " &
"REFCLK2_P: H1, " &
"RESERVED_8: G4, " &
"JTAG_TCK: AJ3, " &
"JTAG_TDI: AK2, " &
"JTAG_TDO: AH2, " &
"JTAG_TMS: AJ2, " &
"JTAG_nTRST: AH3, " &
"JTAG_CPU_nRST: AG3, " &
"JTAG_SEL0: AG2, " &
"JTAG_SEL1: AK3, " &
"THERMDA: J3, " &
"THERMDC: J4, " &
"RESERVED_1: AG29, " &
"SI_CLK: AG1, " &
"SI_D0: AH1, " &
"SI_D1: AJ1, " &
"SI_nCS0: AK1, " &
"MDC0: K2, " &
"MDIO0: K3, " &
"GPIO_0: AC1, " &
"GPIO_1: AC2, " &
"GPIO_2: AC3, " &
"GPIO_3: AC4, " &
"GPIO_4: AB1, " &
"GPIO_5: AB2, " &
"GPIO_6: AB3, " &
"GPIO_7: AB4, " &
"GPIO_8: AG25, " &
"GPIO_9: AH25, " &
"GPIO_10: AA1, " &
"GPIO_11: AA2, " &
"GPIO_12: AA3, " &
"GPIO_13: AA4, " &
"GPIO_14: Y1, " &
"GPIO_15: Y2, " &
"GPIO_16: Y3, " &
"GPIO_17: Y4, " &
"GPIO_18: W1, " &
"GPIO_19: W2, " &
"GPIO_20: W3, " &
"GPIO_21: W4, " &
"GPIO_22: V1, " &
"GPIO_23: V2, " &
"GPIO_24: V3, " &
"GPIO_25: V4, " &
"GPIO_26: U1, " &
"GPIO_27: U2, " &
"GPIO_28: U3, " &
"GPIO_29: U4, " &
"GPIO_30: T1, " &
"GPIO_31: T2, " &
"GPIO_32: T3, " &
"GPIO_33: T4, " &
"GPIO_34: R1, " &
"GPIO_35: R2, " &
"GPIO_36: R3, " &
"GPIO_37: R4, " &
"GPIO_38: AJ25, " &
"GPIO_39: AK25, " &
"GPIO_40: AJ26, " &
"GPIO_41: AK26, " &
"GPIO_42: AJ27, " &
"GPIO_43: AK27, " &
"GPIO_44: AJ28, " &
"GPIO_45: AK28, " &
"GPIO_46: AJ29, " &
"GPIO_47: AK29, " &
"GPIO_48: P1, " &
"GPIO_49: P2, " &
"GPIO_50: P3, " &
"GPIO_51: P4, " &
"GPIO_52: N1, " &
"GPIO_53: N2, " &
"GPIO_54: N3, " &
"GPIO_55: N4, " &
"GPIO_56: M1, " &
"GPIO_57: M2, " &
"GPIO_58: M3, " &
"GPIO_59: M4, " &
"GPIO_60: L1, " &
"GPIO_61: L2, " &
"GPIO_62: L3, " &
"GPIO_63: L4, " &
"DDR_RESETn: AG28, " &
"DDR_CK_t: P28, " &
"DDR_CK_c: P27, " &
"DDR_CKE1: Y28, " &
"DDR_CKE0: AA27, " &
"DDR_ODT1: W28, " &
"DDR_ODT0: Y27, " &
"DDR_CS_n1: R27, " &
"DDR_CS_n0: R28, " &
"DDR_ACT_n: AA28, " &
"DDR_BG1: L27, " &
"DDR_BG0: AF28, " &
"DDR_BA1: L28, " &
"DDR_BA0: AG27, " &
"DDR_A17: V28, " &
"DDR_A16: K27, " &
"DDR_A15: T27, " &
"DDR_A14: AF27, " &
"DDR_A13: N28, " &
"DDR_A12: T28, " &
"DDR_A11: AE28, " &
"DDR_A10: AB27, " &
"DDR_A9: W27, " &
"DDR_A8: AE27, " &
"DDR_A7: N27, " &
"DDR_A6: AC28, " &
"DDR_A5: M27, " &
"DDR_A4: AB28, " &
"DDR_A3: U27, " &
"DDR_A2: AD27, " &
"DDR_A1: U28, " &
"DDR_A0: AC27, " &
"DDR_PAR: AD28, " &
"DDR_ALERT_n: M28, " &
"DDR_DQS_t4: H28, " &
"DDR_DQS_t3: J29, " &
"DDR_DQS_t2: P30, " &
"DDR_DQS_t1: Y30, " &
"DDR_DQS_t0: AF29, " &
"DDR_DQS_c4: J27, " &
"DDR_DQS_c3: J30, " &
"DDR_DQS_c2: R29, " &
"DDR_DQS_c1: AA29, " &
"DDR_DQS_c0: AF30, " &
"DDR_DM4: D27, " &
"DDR_DM3: D30, " &
"DDR_DM2: K29, " &
"DDR_DM1: T29, " &
"DDR_DM0: AA30, " &
"DDR_DQ39: F27, " &
"DDR_DQ38: F28, " &
"DDR_DQ37: E28, " &
"DDR_DQ36: G27, " &
"DDR_DQ35: E27, " &
"DDR_DQ34: G28, " &
"DDR_DQ33: D28, " &
"DDR_DQ32: H27, " &
"DDR_DQ31: F30, " &
"DDR_DQ30: G29, " &
"DDR_DQ29: F29, " &
"DDR_DQ28: G30, " &
"DDR_DQ27: E30, " &
"DDR_DQ26: H29, " &
"DDR_DQ25: E29, " &
"DDR_DQ24: H30, " &
"DDR_DQ23: M29, " &
"DDR_DQ22: M30, " &
"DDR_DQ21: L30, " &
"DDR_DQ20: N29, " &
"DDR_DQ19: L29, " &
"DDR_DQ18: N30, " &
"DDR_DQ17: K30, " &
"DDR_DQ16: P29, " &
"DDR_DQ15: V29, " &
"DDR_DQ14: V30, " &
"DDR_DQ13: U30, " &
"DDR_DQ12: W29, " &
"DDR_DQ11: U29, " &
"DDR_DQ10: W30, " &
"DDR_DQ9: T30, " &
"DDR_DQ8: Y29, " &
"DDR_DQ7: AC29, " &
"DDR_DQ6: AD29, " &
"DDR_DQ5: AB29, " &
"DDR_DQ4: AD30, " &
"DDR_DQ3: AC30, " &
"DDR_DQ2: AE29, " &
"DDR_DQ1: AB30, " &
"DDR_DQ0: AE30, " &
"DDR_RZQ: K28, " &
"RESERVED_2: G26, " &
"RESERVED_4: J26, " &
"RESERVED_3: H26, " &
-- "NoBall : (A18,A20,A22,A24,AK7,AK9,AK11,AK13,AK15,AK17,AK21,AK23) , " &
"VDD : (J8,J9,J12,J13,J18,J19,J22,J23,K8,K9,K12,K13,K18,K19,K22,K23, " &
" L8,L9,L12,L13,L18,L19,L22,L23,M8,M9,M12,M13,M18,M19,M22,M23, " &
" N8,N9,N12,N13,N18,N19,N22,N23,P8,P9,P12,P13,P18,P19,P22,P23, " &
" R8,R9,R12,R13,R18,R19,R22,R23,T8,T9,T12,T13,T18,T19,T22,T23, " &
" U8,U9,U12,U13,U18,U19,U22,U23,V8,V9,V12,V13,V18,V19,V22,V23, " &
" W8,W9,W12,W13,W18,W19,W22,W23,Y8,Y9,Y12,Y13,Y18,Y19,Y22,Y23, " &
" AA8,AA9,AA12,AA13,AA18,AA19,AA22,AA23,AB8,AB9,AB12,AB13,AB18,AB19,AB22, AB23) , " &
"VDDH18 : (F10,F12,F14,F16,G10,G12,G14,G16,AE5,AE19,AF5,AF19,AF24,AG24) , " &
"VDDHS2 : (A2,A4,A6,A8,A10,A12,A14,A16,B2,B4,B6,B8,B10,B12,B14,B16) , " &
"VDDHS : (A25,B25,D25,E25,F17,F19,F21,F23,F25,G17,G19,G21,G23,G25,AD6, " &
" AD8,AD10,AD12,AD14,AD16,AD18,AD20,AD22,AD24,AE6,AE8,AE10,AE12, " &
" AE14,AE16,AE18,AE20,AE22,AE24) , " &
"VDDHV2 : (F6,F8,G6,G8) , " &
"VDDHV : (A27,A29,B27,B29,AJ5,AJ19,AJ24,AK5,AK19,AK24) , " &
"VDDIO18 : (J5,K5,AD1,AD2,AE25,AF25) , " &
"VDDIO33 : (L5,M5,N5,P5,R5,T5,U5,V5,W5,Y5,AA5,AB5,AC5,AF1,AF2,AF3,AH26,AH28,AH30) , " &
"VDDIODDR : (M26,N26,P26,R26,T26,U26,V26,W26,Y26,AA26,AB26,AC26) , " &
"VDDPLLDDR : (K26,L26,AD26,AE26) , " &
"VSS : (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11,C12,C13,C14,C15,C16,C17,C19,C21,C23,C25,C26, " &
" C27,C28,C29,C30,D2,D4,D6,D8,D10,D12,D14,D16,D18,D20,D22,D24,D26,E2,E4,E6,E8,E10, " &
" E12,E14,E16,E26,F1,F2,F3,F4,F5,F7,F9,F11,F13,F15,G2,G3,G5,G7,G9,G11,G13,G15,G18, " &
" G20,G22,G24,H2,H3,H4,H5,H6,H7,H8,H9,H10,H11,H12,H13,H14,H15,H16,H17,H18,H19,H20, " &
" H21,H22,H23,H24,H25,J1,J6,J7,J10,J11,J14,J15,J16,J17,J20,J21,J24,J25,K6,K7,K10, " &
" K11,K14,K15,K16,K17,K20,K21,K24,K25,L6,L7,L10,L11,L14,L15,L16,L17,L20,L21,L24, " &
" L25,M6,M7,M10,M11,M14,M15,M16,M17,M20,M21,M24,M25,N6,N7,N10,N11,N14,N15,N16,N17, " &
" N20,N21,N24,N25,P6,P7,P10,P11,P14,P15,P16,P17,P20,P21,P24,P25,R6,R7,R10,R11,R14, " &
" R15,R16,R17,R20,R21,R24,R25,T6,T7,T10,T11,T14,T15,T16,T17,T20,T21,T24,T25,U6,U7, " &
" U10,U11,U14,U15,U16,U17,U20,U21,U24,U25,V6,V7,V10,V11,V14,V15,V16,V17,V20,V21, " &
" V24,V25,W6,W7,W10,W11,W14,W15,W16,W17,W20,W21,W24,W25,Y6,Y7,Y10,Y11,Y14,Y15,Y16, " &
" Y17,Y20,Y21,Y24,Y25,AA6,AA7,AA10,AA11,AA14,AA15,AA16,AA17,AA20,AA21,AA24,AA25, " &
" AB6,AB7,AB10,AB11,AB14,AB15,AB16,AB17,AB20,AB21,AB24,AB25,AC6,AC7,AC8,AC9,AC10, " &
" AC11,AC12,AC13,AC14,AC15,AC16,AC17,AC18,AC19,AC20,AC21,AC22,AC23,AC24,AC25,AD3, " &
" AD4,AD5,AD7,AD9,AD11,AD13,AD15,AD17,AD19,AD21,AD23,AD25,AE1,AE2,AE3,AF4,AG4,AG7, " &
" AG9,AG11,AG13,AG15,AG17,AG19,AG21,AG23,AG26,AG30,AH4,AH6,AH8,AH10,AH12,AH14,AH16, " &
" AH18,AH19,AH20,AH22,AH24,AH27,AH29,AJ4,AK4) , " &
"DDR_ZCTRL: J28, " &
"DDR_VREFODQ: R30, " &
"DDR_VREFOCA: V27, " &
"RESERVED_10: F26" ;
attribute PORT_GROUPING of VSC7558 : entity is
"Differential_Voltage ( (S0_TXP, S0_TXN), " &
"(S1_TXP, S1_TXN), " &
"(S2_TXP, S2_TXN), " &
"(S3_TXP, S3_TXN), " &
"(S4_TXP, S4_TXN), " &
"(S5_TXP, S5_TXN), " &
"(S6_TXP, S6_TXN), " &
"(S7_TXP, S7_TXN), " &
"(S8_TXP, S8_TXN), " &
"(S9_TXP, S9_TXN), " &
"(S10_TXP, S10_TXN), " &
"(S11_TXP, S11_TXN), " &
"(S12_TXP, S12_TXN), " &
"(S0_RXN, S0_RXP), " &
"(S1_RXN, S1_RXP), " &
"(S2_RXN, S2_RXP), " &
"(S3_RXN, S3_RXP), " &
"(S4_RXN, S4_RXP), " &
"(S5_RXN, S5_RXP), " &
"(S6_RXN, S6_RXP), " &
"(S7_RXN, S7_RXP), " &
"(S8_RXN, S8_RXP), " &
"(S9_RXN, S9_RXP), " &
"(S10_RXN, S10_RXP), " &
"(S11_RXN, S11_RXP), " &
"(S12_RXN, S12_RXP), " &
"(S13_TXP, S13_TXN), " &
"(S14_TXP, S14_TXN), " &
"(S15_TXP, S15_TXN), " &
"(S16_TXP, S16_TXN), " &
"(S17_TXP, S17_TXN), " &
"(S18_TXP, S18_TXN), " &
"(S19_TXP, S19_TXN), " &
"(S20_TXP, S20_TXN), " &
"(S21_TXP, S21_TXN), " &
"(S22_TXP, S22_TXN), " &
"(S23_TXP, S23_TXN), " &
"(S24_TXP, S24_TXN), " &
"(S25_TXP, S25_TXN), " &
"(S26_TXP, S26_TXN), " &
"(S27_TXP, S27_TXN), " &
"(S28_TXP, S28_TXN), " &
"(S29_TXP, S29_TXN), " &
"(S30_TXP, S30_TXN), " &
"(S31_TXP, S31_TXN), " &
"(S32_TXP, S32_TXN), " &
"(S13_RXN, S13_RXP), " &
"(S14_RXN, S14_RXP), " &
"(S15_RXN, S15_RXP), " &
"(S16_RXN, S16_RXP), " &
"(S17_RXN, S17_RXP), " &
"(S18_RXN, S18_RXP), " &
"(S19_RXN, S19_RXP), " &
"(S20_RXN, S20_RXP), " &
"(S21_RXN, S21_RXP), " &
"(S22_RXN, S22_RXP), " &
"(S23_RXN, S23_RXP), " &
"(S24_RXN, S24_RXP), " &
"(S25_RXN, S25_RXP), " &
"(S26_RXN, S26_RXP), " &
"(S27_RXN, S27_RXP), " &
"(S28_RXN, S28_RXP), " &
"(S29_RXN, S29_RXP), " &
"(S30_RXN, S30_RXP), " &
"(S31_RXN, S31_RXP), " &
"(S32_RXN, S32_RXP), " &
"(PCIE_TXP, PCIE_TXN), " &
"(PCIE_RXP, PCIE_RXN)) " ;
attribute TAP_SCAN_RESET of JTAG_nTRST : signal is true;
attribute TAP_SCAN_IN of JTAG_TDI : signal is true;
attribute TAP_SCAN_MODE of JTAG_TMS : signal is true;
attribute TAP_SCAN_OUT of JTAG_TDO : signal is true;
attribute TAP_SCAN_CLOCK of JTAG_TCK : signal is (2.5000000000000000000e+07, BOTH);
attribute INSTRUCTION_LENGTH of VSC7558: entity is 4;
attribute INSTRUCTION_OPCODE of VSC7558: entity is
"IDCODE (1000)," &
"BYPASS (1111)," &
"EXTEST (0001)," &
"SAMPLE (0101)," &
"PRELOAD (0101)," &
"HIGHZ (0110)," &
"CLAMP (0000) " ;
attribute INSTRUCTION_CAPTURE of VSC7558: entity is "0001";
attribute IDCODE_REGISTER of VSC7558: entity is
"0001" & -- version
"0000001010000001" & -- part number
"01000100010" & -- manufacturer's identity
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of VSC7558: entity is
"DEVICE_ID ( IDCODE )," &
"BOUNDARY ( SAMPLE, PRELOAD, EXTEST )," &
"BYPASS ( HIGHZ, CLAMP, BYPASS ) " ;
--Boundary scan definition
attribute BOUNDARY_LENGTH of VSC7558: entity is 340;
attribute BOUNDARY_REGISTER of VSC7558: entity is
-- num cell port function safe [ccell disval rslt]
" 339 (BC_4 , nRESET , observe_only , X ) ,"&
" 338 (BC_2 , S12_TXP , output2 , X ) ,"&
" 337 (BC_2 , S11_TXP , output2 , X ) ,"&
" 336 (BC_2 , S10_TXP , output2 , X ) ,"&
" 335 (BC_2 , S9_TXP , output2 , X ) ,"&
" 334 (BC_2 , S8_TXP , output2 , X ) ,"&
" 333 (BC_2 , S7_TXP , output2 , X ) ,"&
" 332 (BC_2 , S6_TXP , output2 , X ) ,"&
" 331 (BC_2 , S5_TXP , output2 , X ) ,"&
" 330 (BC_2 , S4_TXP , output2 , X ) ,"&
" 329 (BC_2 , S3_TXP , output2 , X ) ,"&
" 328 (BC_2 , S2_TXP , output2 , X ) ,"&
" 327 (BC_2 , S1_TXP , output2 , X ) ,"&
" 326 (BC_2 , S0_TXP , output2 , X ) ,"&
" 325 (BC_4 , S12_RXP , observe_only , X ) ,"&
" 324 (BC_4 , S12_RXN , observe_only , X ) ,"&
" 323 (BC_4 , S11_RXP , observe_only , X ) ,"&
" 322 (BC_4 , S11_RXN , observe_only , X ) ,"&
" 321 (BC_4 , S10_RXP , observe_only , X ) ,"&
" 320 (BC_4 , S10_RXN , observe_only , X ) ,"&
" 319 (BC_4 , S9_RXP , observe_only , X ) ,"&
" 318 (BC_4 , S9_RXN , observe_only , X ) ,"&
" 317 (BC_4 , S8_RXP , observe_only , X ) ,"&
" 316 (BC_4 , S8_RXN , observe_only , X ) ,"&
" 315 (BC_4 , S7_RXP , observe_only , X ) ,"&
" 314 (BC_4 , S7_RXN , observe_only , X ) ,"&
" 313 (BC_4 , S6_RXP , observe_only , X ) ,"&
" 312 (BC_4 , S6_RXN , observe_only , X ) ,"&
" 311 (BC_4 , S5_RXP , observe_only , X ) ,"&
" 310 (BC_4 , S5_RXN , observe_only , X ) ,"&
" 309 (BC_4 , S4_RXP , observe_only , X ) ,"&
" 308 (BC_4 , S4_RXN , observe_only , X ) ,"&
" 307 (BC_4 , S3_RXP , observe_only , X ) ,"&
" 306 (BC_4 , S3_RXN , observe_only , X ) ,"&
" 305 (BC_4 , S2_RXP , observe_only , X ) ,"&
" 304 (BC_4 , S2_RXN , observe_only , X ) ,"&
" 303 (BC_4 , S1_RXP , observe_only , X ) ,"&
" 302 (BC_4 , S1_RXN , observe_only , X ) ,"&
" 301 (BC_4 , S0_RXP , observe_only , X ) ,"&
" 300 (BC_4 , S0_RXN , observe_only , X ) ,"&
" 299 (BC_2 , S16_TXP , output2 , X ) ,"&
" 298 (BC_2 , S15_TXP , output2 , X ) ,"&
" 297 (BC_2 , S14_TXP , output2 , X ) ,"&
" 296 (BC_2 , S13_TXP , output2 , X ) ,"&
" 295 (BC_4 , S16_RXP , observe_only , X ) ,"&
" 294 (BC_4 , S16_RXN , observe_only , X ) ,"&
" 293 (BC_4 , S15_RXP , observe_only , X ) ,"&
" 292 (BC_4 , S15_RXN , observe_only , X ) ,"&
" 291 (BC_4 , S14_RXP , observe_only , X ) ,"&
" 290 (BC_4 , S14_RXN , observe_only , X ) ,"&
" 289 (BC_4 , S13_RXP , observe_only , X ) ,"&
" 288 (BC_4 , S13_RXN , observe_only , X ) ,"&
" 287 (BC_2 , S32_TXP , output2 , X ) ,"&
" 286 (BC_2 , S31_TXP , output2 , X ) ,"&
" 285 (BC_2 , S30_TXP , output2 , X ) ,"&
" 284 (BC_2 , S29_TXP , output2 , X ) ,"&
" 283 (BC_2 , S28_TXP , output2 , X ) ,"&
" 282 (BC_2 , S27_TXP , output2 , X ) ,"&
" 281 (BC_2 , S26_TXP , output2 , X ) ,"&
" 280 (BC_2 , S25_TXP , output2 , X ) ,"&
" 279 (BC_2 , S24_TXP , output2 , X ) ,"&
" 278 (BC_2 , S23_TXP , output2 , X ) ,"&
" 277 (BC_2 , S22_TXP , output2 , X ) ,"&
" 276 (BC_2 , S21_TXP , output2 , X ) ,"&
" 275 (BC_2 , S20_TXP , output2 , X ) ,"&
" 274 (BC_2 , S19_TXP , output2 , X ) ,"&
" 273 (BC_2 , S18_TXP , output2 , X ) ,"&
" 272 (BC_2 , S17_TXP , output2 , X ) ,"&
" 271 (BC_4 , S32_RXP , observe_only , X ) ,"&
" 270 (BC_4 , S32_RXN , observe_only , X ) ,"&
" 269 (BC_4 , S31_RXP , observe_only , X ) ,"&
" 268 (BC_4 , S31_RXN , observe_only , X ) ,"&
" 267 (BC_4 , S30_RXP , observe_only , X ) ,"&
" 266 (BC_4 , S30_RXN , observe_only , X ) ,"&
" 265 (BC_4 , S29_RXP , observe_only , X ) ,"&
" 264 (BC_4 , S29_RXN , observe_only , X ) ,"&
" 263 (BC_4 , S28_RXP , observe_only , X ) ,"&
" 262 (BC_4 , S28_RXN , observe_only , X ) ,"&
" 261 (BC_4 , S27_RXP , observe_only , X ) ,"&
" 260 (BC_4 , S27_RXN , observe_only , X ) ,"&
" 259 (BC_4 , S26_RXP , observe_only , X ) ,"&
" 258 (BC_4 , S26_RXN , observe_only , X ) ,"&
" 257 (BC_4 , S25_RXP , observe_only , X ) ,"&
" 256 (BC_4 , S25_RXN , observe_only , X ) ,"&
" 255 (BC_4 , S24_RXP , observe_only , X ) ,"&
" 254 (BC_4 , S24_RXN , observe_only , X ) ,"&
" 253 (BC_4 , S23_RXP , observe_only , X ) ,"&
" 252 (BC_4 , S23_RXN , observe_only , X ) ,"&
" 251 (BC_4 , S22_RXP , observe_only , X ) ,"&
" 250 (BC_4 , S22_RXN , observe_only , X ) ,"&
" 249 (BC_4 , S21_RXP , observe_only , X ) ,"&
" 248 (BC_4 , S21_RXN , observe_only , X ) ,"&
" 247 (BC_4 , S20_RXP , observe_only , X ) ,"&
" 246 (BC_4 , S20_RXN , observe_only , X ) ,"&
" 245 (BC_4 , S19_RXP , observe_only , X ) ,"&
" 244 (BC_4 , S19_RXN , observe_only , X ) ,"&
" 243 (BC_4 , S18_RXP , observe_only , X ) ,"&
" 242 (BC_4 , S18_RXN , observe_only , X ) ,"&
" 241 (BC_4 , S17_RXP , observe_only , X ) ,"&
" 240 (BC_4 , S17_RXN , observe_only , X ) ,"&
" 239 (BC_4 , PCIE_RXN , observe_only , X ) ,"&
" 238 (BC_4 , PCIE_RXP , observe_only , X ) ,"&
" 237 (BC_2 , PCIE_TXP , output2 , X ) ,"&
" 236 (BC_2 , * , control , 0 ) ,"&
" 235 (BC_7 , GPIO_47 , bidir , X , 236 , 0 , Z ),"&
" 234 (BC_2 , * , control , 0 ) ,"&
" 233 (BC_7 , GPIO_46 , bidir , X , 234 , 0 , Z ),"&
" 232 (BC_2 , * , control , 0 ) ,"&
" 231 (BC_7 , GPIO_45 , bidir , X , 232 , 0 , Z ),"&
" 230 (BC_2 , * , control , 0 ) ,"&
" 229 (BC_7 , GPIO_44 , bidir , X , 230 , 0 , Z ),"&
" 228 (BC_2 , * , control , 0 ) ,"&
" 227 (BC_7 , GPIO_43 , bidir , X , 228 , 0 , Z ),"&
" 226 (BC_2 , * , control , 0 ) ,"&
" 225 (BC_7 , GPIO_42 , bidir , X , 226 , 0 , Z ),"&
" 224 (BC_2 , * , control , 0 ) ,"&
" 223 (BC_7 , GPIO_41 , bidir , X , 224 , 0 , Z ),"&
" 222 (BC_2 , * , control , 0 ) ,"&
" 221 (BC_7 , GPIO_40 , bidir , X , 222 , 0 , Z ),"&
" 220 (BC_2 , * , control , 0 ) ,"&
" 219 (BC_7 , GPIO_39 , bidir , X , 220 , 0 , Z ),"&
" 218 (BC_2 , * , control , 0 ) ,"&
" 217 (BC_7 , GPIO_38 , bidir , X , 218 , 0 , Z ),"&
" 216 (BC_2 , * , control , 0 ) ,"&
" 215 (BC_7 , GPIO_9 , bidir , X , 216 , 0 , Z ),"&
" 214 (BC_2 , * , control , 0 ) ,"&
" 213 (BC_7 , GPIO_8 , bidir , X , 214 , 0 , Z ),"&
" 212 (BC_2 , * , control , 0 ) ,"&
" 211 (BC_7 , SI_CLK , bidir , X , 212 , 0 , Z ),"&
" 210 (BC_2 , * , control , 0 ) ,"&
" 209 (BC_7 , SI_D0 , bidir , X , 210 , 0 , Z ),"&
" 208 (BC_2 , * , control , 0 ) ,"&
" 207 (BC_7 , SI_D1 , bidir , X , 208 , 0 , Z ),"&
" 206 (BC_2 , * , control , 0 ) ,"&
" 205 (BC_7 , SI_nCS0 , bidir , X , 206 , 0 , Z ),"&
" 204 (BC_2 , * , control , 0 ) ,"&
" 203 (BC_7 , MDC0 , bidir , X , 204 , 0 , Z ),"&
" 202 (BC_2 , * , control , 0 ) ,"&
" 201 (BC_7 , MDIO0 , bidir , X , 202 , 0 , Z ),"&
" 200 (BC_2 , * , control , 0 ) ,"&
" 199 (BC_7 , GPIO_0 , bidir , X , 200 , 0 , Z ),"&
" 198 (BC_2 , * , control , 0 ) ,"&
" 197 (BC_7 , GPIO_1 , bidir , X , 198 , 0 , Z ),"&
" 196 (BC_2 , * , control , 0 ) ,"&
" 195 (BC_7 , GPIO_2 , bidir , X , 196 , 0 , Z ),"&
" 194 (BC_2 , * , control , 0 ) ,"&
" 193 (BC_7 , GPIO_3 , bidir , X , 194 , 0 , Z ),"&
" 192 (BC_2 , * , control , 0 ) ,"&
" 191 (BC_7 , GPIO_4 , bidir , X , 192 , 0 , Z ),"&
" 190 (BC_2 , * , control , 0 ) ,"&
" 189 (BC_7 , GPIO_5 , bidir , X , 190 , 0 , Z ),"&
" 188 (BC_2 , * , control , 0 ) ,"&
" 187 (BC_7 , GPIO_6 , bidir , X , 188 , 0 , Z ),"&
" 186 (BC_2 , * , control , 0 ) ,"&
" 185 (BC_7 , GPIO_7 , bidir , X , 186 , 0 , Z ),"&
" 184 (BC_2 , * , control , 0 ) ,"&
" 183 (BC_7 , GPIO_10 , bidir , X , 184 , 0 , Z ),"&
" 182 (BC_2 , * , control , 0 ) ,"&
" 181 (BC_7 , GPIO_11 , bidir , X , 182 , 0 , Z ),"&
" 180 (BC_2 , * , control , 0 ) ,"&
" 179 (BC_7 , GPIO_12 , bidir , X , 180 , 0 , Z ),"&
" 178 (BC_2 , * , control , 0 ) ,"&
" 177 (BC_7 , GPIO_13 , bidir , X , 178 , 0 , Z ),"&
" 176 (BC_2 , * , control , 0 ) ,"&
" 175 (BC_7 , GPIO_14 , bidir , X , 176 , 0 , Z ),"&
" 174 (BC_2 , * , control , 0 ) ,"&
" 173 (BC_7 , GPIO_15 , bidir , X , 174 , 0 , Z ),"&
" 172 (BC_2 , * , control , 0 ) ,"&
" 171 (BC_7 , GPIO_16 , bidir , X , 172 , 0 , Z ),"&
" 170 (BC_2 , * , control , 0 ) ,"&
" 169 (BC_7 , GPIO_17 , bidir , X , 170 , 0 , Z ),"&
" 168 (BC_2 , * , control , 0 ) ,"&
" 167 (BC_7 , GPIO_18 , bidir , X , 168 , 0 , Z ),"&
" 166 (BC_2 , * , control , 0 ) ,"&
" 165 (BC_7 , GPIO_19 , bidir , X , 166 , 0 , Z ),"&
" 164 (BC_2 , * , control , 0 ) ,"&
" 163 (BC_7 , GPIO_20 , bidir , X , 164 , 0 , Z ),"&
" 162 (BC_2 , * , control , 0 ) ,"&
" 161 (BC_7 , GPIO_21 , bidir , X , 162 , 0 , Z ),"&
" 160 (BC_2 , * , control , 0 ) ,"&
" 159 (BC_7 , GPIO_22 , bidir , X , 160 , 0 , Z ),"&
" 158 (BC_2 , * , control , 0 ) ,"&
" 157 (BC_7 , GPIO_23 , bidir , X , 158 , 0 , Z ),"&
" 156 (BC_2 , * , control , 0 ) ,"&
" 155 (BC_7 , GPIO_24 , bidir , X , 156 , 0 , Z ),"&
" 154 (BC_2 , * , control , 0 ) ,"&
" 153 (BC_7 , GPIO_25 , bidir , X , 154 , 0 , Z ),"&
" 152 (BC_2 , * , control , 0 ) ,"&
" 151 (BC_7 , GPIO_26 , bidir , X , 152 , 0 , Z ),"&
" 150 (BC_2 , * , control , 0 ) ,"&
" 149 (BC_7 , GPIO_27 , bidir , X , 150 , 0 , Z ),"&
" 148 (BC_2 , * , control , 0 ) ,"&
" 147 (BC_7 , GPIO_28 , bidir , X , 148 , 0 , Z ),"&
" 146 (BC_2 , * , control , 0 ) ,"&
" 145 (BC_7 , GPIO_29 , bidir , X , 146 , 0 , Z ),"&
" 144 (BC_2 , * , control , 0 ) ,"&
" 143 (BC_7 , GPIO_30 , bidir , X , 144 , 0 , Z ),"&
" 142 (BC_2 , * , control , 0 ) ,"&
" 141 (BC_7 , GPIO_31 , bidir , X , 142 , 0 , Z ),"&
" 140 (BC_2 , * , control , 0 ) ,"&
" 139 (BC_7 , GPIO_32 , bidir , X , 140 , 0 , Z ),"&
" 138 (BC_2 , * , control , 0 ) ,"&
" 137 (BC_7 , GPIO_33 , bidir , X , 138 , 0 , Z ),"&
" 136 (BC_2 , * , control , 0 ) ,"&
" 135 (BC_7 , GPIO_34 , bidir , X , 136 , 0 , Z ),"&
" 134 (BC_2 , * , control , 0 ) ,"&
" 133 (BC_7 , GPIO_35 , bidir , X , 134 , 0 , Z ),"&
" 132 (BC_2 , * , control , 0 ) ,"&
" 131 (BC_7 , GPIO_36 , bidir , X , 132 , 0 , Z ),"&
" 130 (BC_2 , * , control , 0 ) ,"&
" 129 (BC_7 , GPIO_37 , bidir , X , 130 , 0 , Z ),"&
" 128 (BC_2 , * , control , 0 ) ,"&
" 127 (BC_7 , GPIO_48 , bidir , X , 128 , 0 , Z ),"&
" 126 (BC_2 , * , control , 0 ) ,"&
" 125 (BC_7 , GPIO_49 , bidir , X , 126 , 0 , Z ),"&
" 124 (BC_2 , * , control , 0 ) ,"&
" 123 (BC_7 , GPIO_50 , bidir , X , 124 , 0 , Z ),"&
" 122 (BC_2 , * , control , 0 ) ,"&
" 121 (BC_7 , GPIO_51 , bidir , X , 122 , 0 , Z ),"&
" 120 (BC_2 , * , control , 0 ) ,"&
" 119 (BC_7 , GPIO_52 , bidir , X , 120 , 0 , Z ),"&
" 118 (BC_2 , * , control , 0 ) ,"&
" 117 (BC_7 , GPIO_53 , bidir , X , 118 , 0 , Z ),"&
" 116 (BC_2 , * , control , 0 ) ,"&
" 115 (BC_7 , GPIO_54 , bidir , X , 116 , 0 , Z ),"&
" 114 (BC_2 , * , control , 0 ) ,"&
" 113 (BC_7 , GPIO_55 , bidir , X , 114 , 0 , Z ),"&
" 112 (BC_2 , * , control , 0 ) ,"&
" 111 (BC_7 , GPIO_56 , bidir , X , 112 , 0 , Z ),"&
" 110 (BC_2 , * , control , 0 ) ,"&
" 109 (BC_7 , GPIO_57 , bidir , X , 110 , 0 , Z ),"&
" 108 (BC_2 , * , control , 0 ) ,"&
" 107 (BC_7 , GPIO_58 , bidir , X , 108 , 0 , Z ),"&
" 106 (BC_2 , * , control , 0 ) ,"&
" 105 (BC_7 , GPIO_59 , bidir , X , 106 , 0 , Z ),"&
" 104 (BC_2 , * , control , 0 ) ,"&
" 103 (BC_7 , GPIO_60 , bidir , X , 104 , 0 , Z ),"&
" 102 (BC_2 , * , control , 0 ) ,"&
" 101 (BC_7 , GPIO_61 , bidir , X , 102 , 0 , Z ),"&
" 100 (BC_2 , * , control , 0 ) ,"&
" 99 (BC_7 , GPIO_62 , bidir , X , 100 , 0 , Z ),"&
" 98 (BC_2 , * , control , 0 ) ,"&
" 97 (BC_7 , GPIO_63 , bidir , X , 98 , 0 , Z ),"&
" 96 (BC_2 , * , control , 0 ) ,"&
" 95 (BC_7 , DDR_RESETn , bidir , X , 96 , 0 , Z ),"&
" 94 (BC_7 , DDR_CK_t , bidir , X , 96 , 0 , Z ),"&
" 93 (BC_7 , DDR_CK_c , bidir , X , 96 , 0 , Z ),"&
" 92 (BC_7 , DDR_CKE1 , bidir , X , 96 , 0 , Z ),"&
" 91 (BC_7 , DDR_CKE0 , bidir , X , 96 , 0 , Z ),"&
" 90 (BC_7 , DDR_ODT1 , bidir , X , 96 , 0 , Z ),"&
" 89 (BC_7 , DDR_ODT0 , bidir , X , 96 , 0 , Z ),"&
" 88 (BC_7 , DDR_CS_n1 , bidir , X , 96 , 0 , Z ),"&
" 87 (BC_7 , DDR_CS_n0 , bidir , X , 96 , 0 , Z ),"&
" 86 (BC_7 , DDR_ACT_n , bidir , X , 96 , 0 , Z ),"&
" 85 (BC_7 , DDR_BG1 , bidir , X , 96 , 0 , Z ),"&
" 84 (BC_7 , DDR_BG0 , bidir , X , 96 , 0 , Z ),"&
" 83 (BC_7 , DDR_BA1 , bidir , X , 96 , 0 , Z ),"&
" 82 (BC_7 , DDR_BA0 , bidir , X , 96 , 0 , Z ),"&
" 81 (BC_7 , DDR_A17 , bidir , X , 96 , 0 , Z ),"&
" 80 (BC_7 , DDR_A16 , bidir , X , 96 , 0 , Z ),"&
" 79 (BC_2 , * , control , 0 ) ,"&
" 78 (BC_7 , DDR_A15 , bidir , X , 79 , 0 , Z ),"&
" 77 (BC_7 , DDR_A14 , bidir , X , 79 , 0 , Z ),"&
" 76 (BC_7 , DDR_A13 , bidir , X , 79 , 0 , Z ),"&
" 75 (BC_7 , DDR_A12 , bidir , X , 79 , 0 , Z ),"&
" 74 (BC_7 , DDR_A11 , bidir , X , 79 , 0 , Z ),"&
" 73 (BC_7 , DDR_A10 , bidir , X , 79 , 0 , Z ),"&
" 72 (BC_7 , DDR_A9 , bidir , X , 79 , 0 , Z ),"&
" 71 (BC_7 , DDR_A8 , bidir , X , 79 , 0 , Z ),"&
" 70 (BC_7 , DDR_A7 , bidir , X , 79 , 0 , Z ),"&
" 69 (BC_7 , DDR_A6 , bidir , X , 79 , 0 , Z ),"&
" 68 (BC_7 , DDR_A5 , bidir , X , 79 , 0 , Z ),"&
" 67 (BC_7 , DDR_A4 , bidir , X , 79 , 0 , Z ),"&
" 66 (BC_7 , DDR_A3 , bidir , X , 79 , 0 , Z ),"&
" 65 (BC_7 , DDR_A2 , bidir , X , 79 , 0 , Z ),"&
" 64 (BC_7 , DDR_A1 , bidir , X , 79 , 0 , Z ),"&
" 63 (BC_7 , DDR_A0 , bidir , X , 79 , 0 , Z ),"&
" 62 (BC_2 , * , control , 0 ) ,"&
" 61 (BC_7 , DDR_PAR , bidir , X , 62 , 0 , Z ),"&
" 60 (BC_7 , DDR_ALERT_n , bidir , X , 62 , 0 , Z ),"&
" 59 (BC_7 , DDR_DQS_t4 , bidir , X , 62 , 0 , Z ),"&
" 58 (BC_7 , DDR_DQS_t3 , bidir , X , 62 , 0 , Z ),"&
" 57 (BC_7 , DDR_DQS_t2 , bidir , X , 62 , 0 , Z ),"&
" 56 (BC_7 , DDR_DQS_t1 , bidir , X , 62 , 0 , Z ),"&
" 55 (BC_7 , DDR_DQS_t0 , bidir , X , 62 , 0 , Z ),"&
" 54 (BC_7 , DDR_DQS_c4 , bidir , X , 62 , 0 , Z ),"&
" 53 (BC_7 , DDR_DQS_c3 , bidir , X , 62 , 0 , Z ),"&
" 52 (BC_7 , DDR_DQS_c2 , bidir , X , 62 , 0 , Z ),"&
" 51 (BC_7 , DDR_DQS_c1 , bidir , X , 62 , 0 , Z ),"&
" 50 (BC_7 , DDR_DQS_c0 , bidir , X , 62 , 0 , Z ),"&
" 49 (BC_7 , DDR_DM4 , bidir , X , 62 , 0 , Z ),"&
" 48 (BC_7 , DDR_DM3 , bidir , X , 62 , 0 , Z ),"&
" 47 (BC_7 , DDR_DM2 , bidir , X , 62 , 0 , Z ),"&
" 46 (BC_7 , DDR_DM1 , bidir , X , 62 , 0 , Z ),"&
" 45 (BC_2 , * , control , 0 ) ,"&
" 44 (BC_7 , DDR_DM0 , bidir , X , 45 , 0 , Z ),"&
" 43 (BC_7 , DDR_DQ39 , bidir , X , 45 , 0 , Z ),"&
" 42 (BC_7 , DDR_DQ38 , bidir , X , 45 , 0 , Z ),"&
" 41 (BC_7 , DDR_DQ37 , bidir , X , 45 , 0 , Z ),"&
" 40 (BC_7 , DDR_DQ36 , bidir , X , 45 , 0 , Z ),"&
" 39 (BC_7 , DDR_DQ35 , bidir , X , 45 , 0 , Z ),"&
" 38 (BC_7 , DDR_DQ34 , bidir , X , 45 , 0 , Z ),"&
" 37 (BC_7 , DDR_DQ33 , bidir , X , 45 , 0 , Z ),"&
" 36 (BC_7 , DDR_DQ32 , bidir , X , 45 , 0 , Z ),"&
" 35 (BC_7 , DDR_DQ31 , bidir , X , 45 , 0 , Z ),"&
" 34 (BC_7 , DDR_DQ30 , bidir , X , 45 , 0 , Z ),"&
" 33 (BC_7 , DDR_DQ29 , bidir , X , 45 , 0 , Z ),"&
" 32 (BC_7 , DDR_DQ28 , bidir , X , 45 , 0 , Z ),"&
" 31 (BC_7 , DDR_DQ27 , bidir , X , 45 , 0 , Z ),"&
" 30 (BC_7 , DDR_DQ26 , bidir , X , 45 , 0 , Z ),"&
" 29 (BC_7 , DDR_DQ25 , bidir , X , 45 , 0 , Z ),"&
" 28 (BC_2 , * , control , 0 ) ,"&
" 27 (BC_7 , DDR_DQ24 , bidir , X , 28 , 0 , Z ),"&
" 26 (BC_7 , DDR_DQ23 , bidir , X , 28 , 0 , Z ),"&
" 25 (BC_7 , DDR_DQ22 , bidir , X , 28 , 0 , Z ),"&
" 24 (BC_7 , DDR_DQ21 , bidir , X , 28 , 0 , Z ),"&
" 23 (BC_7 , DDR_DQ20 , bidir , X , 28 , 0 , Z ),"&
" 22 (BC_7 , DDR_DQ19 , bidir , X , 28 , 0 , Z ),"&
" 21 (BC_7 , DDR_DQ18 , bidir , X , 28 , 0 , Z ),"&
" 20 (BC_7 , DDR_DQ17 , bidir , X , 28 , 0 , Z ),"&
" 19 (BC_7 , DDR_DQ16 , bidir , X , 28 , 0 , Z ),"&
" 18 (BC_7 , DDR_DQ15 , bidir , X , 28 , 0 , Z ),"&
" 17 (BC_7 , DDR_DQ14 , bidir , X , 28 , 0 , Z ),"&
" 16 (BC_7 , DDR_DQ13 , bidir , X , 28 , 0 , Z ),"&
" 15 (BC_7 , DDR_DQ12 , bidir , X , 28 , 0 , Z ),"&
" 14 (BC_7 , DDR_DQ11 , bidir , X , 28 , 0 , Z ),"&
" 13 (BC_7 , DDR_DQ10 , bidir , X , 28 , 0 , Z ),"&
" 12 (BC_7 , DDR_DQ9 , bidir , X , 28 , 0 , Z ),"&
" 11 (BC_2 , * , control , 0 ) ,"&
" 10 (BC_7 , DDR_DQ8 , bidir , X , 11 , 0 , Z ),"&
" 9 (BC_7 , DDR_DQ7 , bidir , X , 11 , 0 , Z ),"&
" 8 (BC_7 , DDR_DQ6 , bidir , X , 11 , 0 , Z ),"&
" 7 (BC_7 , DDR_DQ5 , bidir , X , 11 , 0 , Z ),"&
" 6 (BC_7 , DDR_DQ4 , bidir , X , 11 , 0 , Z ),"&
" 5 (BC_7 , DDR_DQ3 , bidir , X , 11 , 0 , Z ),"&
" 4 (BC_7 , DDR_DQ2 , bidir , X , 11 , 0 , Z ),"&
" 3 (BC_7 , DDR_DQ1 , bidir , X , 11 , 0 , Z ),"&
" 2 (BC_7 , DDR_DQ0 , bidir , X , 11 , 0 , Z ),"&
" 1 (BC_2 , RESERVED_4 , output3 , X , 11 , 0 , Z ),"&
" 0 (BC_2 , RESERVED_3 , output3 , X , 11 , 0 , Z ) ";
end VSC7558;