-- ***************************************************************************
-- Intel(R) Xeon(R) Processor E7-8800/4800/2800 product families 6-Core processor's Core#4
-- Boundary Scan Descriptor Language (BSDL) Model, Version 1.0
--
-- The syntax was checked using Agilent(c) Scan Port Driver, Revision 3070 07.00p
--
-- ***************************************************************************
-- Information in this document is provided in connection with Intel products.
-- No license, express or implied, by estoppel or otherwise, to any
-- intellectual property rights is granted by this document. Except as
-- provided in Intel's Terms and Conditions of Sale for such products,
-- Intel assumes no liability whatsoever, and Intel disclaims any express or
-- implied warranty, relating to sale and/or use of Intel products including
-- liability or warranties relating to fitness for a particular purpose,
-- merchantability, or infringement of any patent, copyright or other
-- intellectual property right. Intel products are not intended for use in
-- medical, life saving, or life sustaining applications.
--
-- Intel may make changes to specifications and product descriptions at any
-- time, without notice.
--
-- The Intel(R) Xeon(R) Processor E7-8800/4800/2800 product families may contain design
-- defects or errors known as errata which may cause the product to deviate from
-- published specifications. Current characterized errata are available on request.
--
-- Contact your local Intel sales office or your distributor to obtain the
-- latest specifications and before placing your product order.
--
-- Copyright (c) Intel Corporation 2010, 2011. Third-party brands and
-- names are the property of their respective owners.
-- ***************************************************************************
--
-- Modifications:
entity XeonE7_core4 is
generic(PHYSICAL_PIN_MAP : string := "EGL_CORE4_LGA1567");
port (
TCLK : in bit;
TDI : in bit;
TDO : out bit;
TMS : in bit;
TRST_N : in bit
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of XeonE7_core4 : entity is "STD_1149_1_2001" ;
attribute PIN_MAP of XeonE7_core4 : entity is PHYSICAL_PIN_MAP;
constant EGL_CORE4_LGA1567 : PIN_MAP_STRING :=
"TCLK : K10 ," &
"TDI : CORE3TDO ," &
"TDO : CORE4TDO ," &
"TMS : M9 ," &
"TRST_N : M10 "
;
--
-- Scan Port Identification
--
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRST_N : signal is true;
attribute TAP_SCAN_CLOCK of TCLK : signal is (66.0e6, both);
attribute Instruction_Length of XeonE7_core4: entity is 8;
attribute Instruction_Opcode of XeonE7_core4: entity is
" EXTEST ( 00000000 ), " &
" SAMPLE ( 00000001 ), " &
" PRELOAD ( 00000001 ), " &
" IDCODE ( 00000010 ), " &
" CLAMP ( 00000100 ), " &
" HIGHZ ( 00001000 ), " &
" BYPASS ( 11111111 ), " &
" Reserved ( 00000011, 00000101, 00000110, 00001001, 00001010, " &
" 00001011, 00001100, 00001101, 00001110, 00001111, " &
" 00010000, 00010001, 00010010, 00010011, 00010100, " &
" 00010101, 00010110, 00010111, 00011000, 00011001, " &
" 00011010, 00011011, 00011100, 00011101, 00011110, " &
" 00011111, 00100000, 00100001, 00100010, 00100011, " &
" 00100100, 00100101, 00100110, 00100111, 00101000, " &
" 00101001, 00101010, 00101011, 00101100, 00101101, " &
" 00101110, 00101111, 00110000, 00110001, 00110010, " &
" 00110011, 00110100, 00110101, 00110110, 00110111, " &
" 00111000, 00111001, 00111010, 00111011, 00111100, " &
" 00111101, 00111110, 00111111, 01000000, 01000001, " &
" 01000010, 01000011, 01000100, 01000101, 01000110, " &
" 01000111, 01001000, 01001001, 01001010, 01001011, " &
" 01001100, 01001101, 01001110, 01001111, 01010000, " &
" 01010001, 01010010, 01010011, 01010100, 01010101, " &
" 01010110, 01010111, 01011000, 01011001, 01011010, " &
" 01011011, 01011100, 01011101, 01011110, 01011111, " &
" 01100000, 01100001, 01100010, 01100011, 01100100, " &
" 01100101, 01100110, 01100111, 01101000, 01101001, " &
" 01101010, 01101011, 01101100, 01101101, 01101110, " &
" 01101111, 01110000, 01110001, 01110010, 01110011, " &
" 01110100, 01110101, 01110110, 01110111, 01111000, " &
" 01111001, 01111010, 01111011, 01111100, 01111101, " &
" 01111110, 01111111, 10000000, 10000001, 10000010, " &
" 10000011, 10000100, 10000101, 10000110, 10000111, " &
" 10001000, 10001001, 10001010, 10001011, 10001100, " &
" 10001101, 10001110, 10001111, 10010000, 10010001, " &
" 10010010, 10010011, 10010100, 10010101, 10010110, " &
" 10010111, 10011000, 10011001, 10011010, 10011011, " &
" 10011100, 10011101, 10011110, 10011111, 10100000, " &
" 10100001, 10100010, 10100011, 10100100, 10100101, " &
" 10100110, 10100111, 10101000, 10101001, 10101010, " &
" 10101011, 10101100, 10101101, 10101110, 10101111, " &
" 10110000, 10110001, 10110010, 10110011, 10110100, " &
" 10110101, 10110110, 10110111, 10111000, 10111001, " &
" 10111010, 10111011, 10111100, 10111101, 10111110, " &
" 10111111, 11000000, 11000001, 11000010, 11000011, " &
" 11000100, 11000101, 11000110, 11000111, 11001000, " &
" 11001001, 11001010, 11001011, 11001100, 11001101, " &
" 11001110, 11001111, 11010000, 11010001, 11010010, " &
" 11010011, 11010100, 11010101, 11010110, 11010111, " &
" 11011000, 11011001, 11011010, 11011011, 11011100, " &
" 11011101, 11011110, 11011111, 11100000, 11100001, " &
" 11100010, 11100011, 11100100, 11100101, 11100110, " &
" 11100111, 11101000, 11101001, 11101010, 11101011, " &
" 11101100, 11101101, 11101110, 11101111, 11110000, " &
" 11110001, 11110010, 11110011, 11110100, 11110101, " &
" 11110110, 11110111, 11111000, 11111001, 11111010, " &
" 11111011, 11111100, 11111101, 11111110 )" ;
attribute Instruction_Capture of XeonE7_core4: entity is "00000001";
attribute Instruction_Private of XeonE7_core4: entity is "Reserved";
--
-- XeonE7_core4 A2 IDCODE Register
-- Hex value: 0x0A244013
attribute Idcode_Register of XeonE7_core4 : entity is
"0000" & -- XeonE7 core stepping ID
"1010001001000100" & -- Part number
"00000001001" & -- Manufacturer's identity
"1"; -- Required by the standard
--
-- XeonE7_core4 Data Register Access
--
attribute Register_Access of XeonE7_core4: entity is
"BOUNDARY (EXTEST, SAMPLE, PRELOAD), " &
"DEVICE_ID (IDCODE), " &
"BYPASS (HIGHZ, BYPASS) ";
--
-- XeonE7_core4 Boundary Scan cells
--
attribute BOUNDARY_LENGTH of XeonE7_core4: entity is 1;
attribute BOUNDARY_REGISTER of XeonE7_core4: entity is
-- num cell port function safe
"0 (BC_3, * , internal , X )";
attribute DESIGN_WARNING of XeonE7_core4 : entity is
" This is Intel(R) Xeon(R) Processor E7-8800/4800/2800 product families BSDL file. " &
" " &
" 1. Normal power up sequence must be completed prior to using Boundary scan logic. " &
" " &
" 2. PwrGood should be held stable for 34ms before beginning Boundary Scan operations. " &
" " &
" 3. The serial chain for 1 chipset TAP and all 6 Core TAP blocks are connected in the following way: " &
" TDI -> XeonE7_chipset -> XeonE7_core0 -> XeonE7_core1 -> " &
" XeonE7_core2 -> XeonE7_core3 -> XeonE7_core4 -> " &
" XeonE7_core5 -> TDO " &
" " &
" 4. TCLK, TMS, TRST_N are all connected in parallel to each TAP. Each TAP has its own Instruction Register. " &
" " &
" 5. Output and bidirectional pins may experience a 1-Tclk glitch during Sample/Preload. " &
" " &
" 6. During Extest, output pins are updated on the rising edge of TCLK. " &
" " ;
end XeonE7_core4;