-- ======================================================================
-- Copyright 2020, Cypress Semiconductor Corporation.
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-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
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-- This software is protected by and subject to worldwide patent
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-- ======================================================================
--
-- File Name: PSoC_6_256K_TQFP_80.bsdl
--
-- BSDL Version 2001
--
-- Revision: 1.0 -- New BSDL model
--
-- Last Updated:
--
-- Part #: CY8C6244AZI-S4D93
--
-- Package: 80 Pin TQFP
-- ======================================================================
entity CY8C6244AZI_S4D93 is
generic (PHYSICAL_PIN_MAP : string := "TQFP80");
port (
-- Port List
VCCD : linkage bit;
VDDD : linkage bit;
VSS : linkage bit_vector(0 to 6);
VBACKUP : linkage bit;
P0_0 : inout bit;
P0_1 : in bit;
P0_2 : inout bit;
P0_3 : inout bit;
P0_4 : inout bit;
P0_5 : inout bit;
XRES : linkage bit;
P1_0 : inout bit;
P1_1 : inout bit;
P1_2 : inout bit;
P2_0 : inout bit;
P2_1 : inout bit;
P2_2 : inout bit;
P2_3 : inout bit;
P2_4 : inout bit;
P2_5 : inout bit;
P2_6 : inout bit;
P2_7 : inout bit;
VDDIO_2 : linkage bit;
P3_0 : inout bit;
P3_1 : inout bit;
P5_0 : inout bit;
P5_1 : inout bit;
P5_2 : inout bit;
P5_6 : inout bit;
P5_7 : inout bit;
P6_2 : inout bit;
P6_3 : inout bit;
P6_4 : out bit;
P6_5 : in bit;
P6_6 : in bit;
P6_7 : in bit;
VDDIO_1 : linkage bit;
P7_0 : inout bit;
P7_1 : inout bit;
P7_2 : inout bit;
P7_3 : inout bit;
P7_4 : inout bit;
P7_5 : inout bit;
P7_7 : inout bit;
P8_0 : inout bit;
P8_1 : inout bit;
P9_0 : inout bit;
P9_1 : inout bit;
P9_2 : inout bit;
P9_3 : inout bit;
P9_4 : inout bit;
P9_5 : inout bit;
VDDIO_A : linkage bit;
VDDA : linkage bit;
VREF : linkage bit_vector(0 to 1);
P10_0 : inout bit;
P10_1 : inout bit;
P10_2 : inout bit;
P10_3 : inout bit;
P10_4 : inout bit;
P10_5 : inout bit;
P10_6 : inout bit;
P10_7 : inout bit;
P11_1 : inout bit;
P11_2 : inout bit;
P11_3 : inout bit;
P11_4 : inout bit;
P11_5 : inout bit;
P11_6 : inout bit;
P11_7 : inout bit;
VDDIO_0 : linkage bit;
P12_6 : inout bit;
P12_7 : inout bit);
use STD_1149_1_2001.all;
use TS_BSCAN_CELLS.all;
attribute COMPONENT_CONFORMANCE of CY8C6244AZI_S4D93: entity is "STD_1149_1_2001";
--Pin mappings
attribute PIN_MAP of CY8C6244AZI_S4D93: entity is PHYSICAL_PIN_MAP;
constant TQFP80: PIN_MAP_STRING :=
"VDDD : 1 , " &
"VSS : ( 2, 11, 24, 38, 41, 58, 77), " &
"VBACKUP : 3 , " &
"P0_0 : 4 , " &
"P0_1 : 5 , " &
"P0_2 : 6 , " &
"P0_3 : 7 , " &
"P0_4 : 8 , " &
"P0_5 : 9 , " &
"XRES : 10 , " &
"P1_0 : 12 , " &
"P1_1 : 13 , " &
"P1_2 : 14 , " &
"P2_0 : 15 , " &
"P2_1 : 16 , " &
"P2_2 : 17 , " &
"P2_3 : 18 , " &
"P2_4 : 19 , " &
"P2_5 : 20 , " &
"P2_6 : 21 , " &
"P2_7 : 22 , " &
"VDDIO_2 : 23 , " &
"P3_0 : 25 , " &
"P3_1 : 26 , " &
"P5_0 : 27 , " &
"P5_1 : 28 , " &
"P5_2 : 29 , " &
"P5_6 : 30 , " &
"P5_7 : 31 , " &
"P6_2 : 32 , " &
"P6_3 : 33 , " &
"P6_4 : 34 , " &
"P6_5 : 35 , " &
"P6_6 : 36 , " &
"P6_7 : 37 , " &
"VDDIO_1 : 39 , " &
"VDDIO_A : 40 , " &
"P7_0 : 42 , " &
"P7_1 : 43 , " &
"P7_2 : 44 , " &
"P7_3 : 45 , " &
"P7_4 : 46 , " &
"P7_5 : 47 , " &
"P7_7 : 48 , " &
"P8_0 : 49 , " &
"P8_1 : 50 , " &
"P9_0 : 51 , " &
"P9_1 : 52 , " &
"P9_2 : 53 , " &
"P9_3 : 54 , " &
"P9_4 : 55 , " &
"P9_5 : 56 , " &
"VREF : ( 57, 60), " &
"VDDA : 59 , " &
"P10_0 : 61 , " &
"P10_1 : 62 , " &
"P10_2 : 63 , " &
"P10_3 : 64 , " &
"P10_4 : 65 , " &
"P10_5 : 66 , " &
"P10_6 : 67 , " &
"P10_7 : 68 , " &
"P11_1 : 69 , " &
"P11_2 : 70 , " &
"P11_3 : 71 , " &
"P11_4 : 72 , " &
"P11_5 : 73 , " &
"P11_6 : 74 , " &
"P11_7 : 75 , " &
"VDDIO_0 : 76 , " &
"P12_6 : 78 , " &
"P12_7 : 79 , " &
"VCCD : 80";
attribute TAP_SCAN_RESET of P0_1 : signal is true;
attribute TAP_SCAN_IN of P6_5 : signal is true;
attribute TAP_SCAN_MODE of P6_6 : signal is true;
attribute TAP_SCAN_OUT of P6_4 : signal is true;
attribute TAP_SCAN_CLOCK of P6_7 : signal is (1.0000000000000000000e+07, BOTH);
attribute INSTRUCTION_LENGTH of CY8C6244AZI_S4D93: entity is 4;
attribute INSTRUCTION_OPCODE of CY8C6244AZI_S4D93: entity is
"IDCODE (1100)," &
"BYPASS (1111)," &
"EXTEST (0001)," &
"EXTEST_PULSE (0010)," &
"EXTEST_TRAIN (0011)," &
"SAMPLE (0101)," &
"PRELOAD (0101)," &
"HIGHZ (0110)," &
"CLAMP (0000) " ;
attribute INSTRUCTION_CAPTURE of CY8C6244AZI_S4D93: entity is "0001";
attribute IDCODE_REGISTER of CY8C6244AZI_S4D93: entity is
"0001" & -- version
"1110101011000000" & -- part number
"00000110100" & -- manufacturer's identity
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of CY8C6244AZI_S4D93: entity is
"DEVICE_ID ( IDCODE )," &
"BOUNDARY ( SAMPLE, PRELOAD, EXTEST, EXTEST_PULSE, EXTEST_TRAIN )," &
"BYPASS ( HIGHZ, CLAMP, BYPASS ) " ;
--Boundary scan definition
attribute BOUNDARY_LENGTH of CY8C6244AZI_S4D93: entity is 118;
attribute BOUNDARY_REGISTER of CY8C6244AZI_S4D93: entity is
-- num cell port function safe [ccell disval rslt]
" 117 (BC_2 , * , control , 0 ) ,"&
" 116 (TS_BC_7 , P0_0 , bidir , X , 117 , 0 , Z ),"&
" 115 (BC_2 , * , control , 0 ) ,"&
" 114 (TS_BC_7 , P0_2 , bidir , X , 115 , 0 , Z ),"&
" 113 (BC_2 , * , control , 0 ) ,"&
" 112 (TS_BC_7 , P0_3 , bidir , X , 113 , 0 , Z ),"&
" 111 (BC_2 , * , control , 0 ) ,"&
" 110 (TS_BC_7 , P0_4 , bidir , X , 111 , 0 , Z ),"&
" 109 (BC_2 , * , control , 0 ) ,"&
" 108 (TS_BC_7 , P0_5 , bidir , X , 109 , 0 , Z ),"&
" 107 (BC_0 , * , internal , 0 ) ,"&
" 106 (BC_0 , * , internal , X ) ,"&
" 105 (BC_0 , * , internal , 0 ) ,"&
" 104 (BC_0 , * , internal , X ) ,"&
" 103 (BC_2 , * , control , 0 ) ,"&
" 102 (TS_BC_7 , P1_0 , bidir , X , 103 , 0 , Z ),"&
" 101 (BC_2 , * , control , 0 ) ,"&
" 100 (TS_BC_7 , P1_1 , bidir , X , 101 , 0 , Z ),"&
" 99 (BC_2 , * , control , 0 ) ,"&
" 98 (TS_BC_7 , P1_2 , bidir , X , 99 , 0 , Z ),"&
" 97 (BC_2 , * , control , 0 ) ,"&
" 96 (TS_BC_7 , P2_0 , bidir , X , 97 , 0 , Z ),"&
" 95 (BC_2 , * , control , 0 ) ,"&
" 94 (TS_BC_7 , P2_1 , bidir , X , 95 , 0 , Z ),"&
" 93 (BC_2 , * , control , 0 ) ,"&
" 92 (TS_BC_7 , P2_2 , bidir , X , 93 , 0 , Z ),"&
" 91 (BC_2 , * , control , 0 ) ,"&
" 90 (TS_BC_7 , P2_3 , bidir , X , 91 , 0 , Z ),"&
" 89 (BC_2 , * , control , 0 ) ,"&
" 88 (TS_BC_7 , P2_4 , bidir , X , 89 , 0 , Z ),"&
" 87 (BC_2 , * , control , 0 ) ,"&
" 86 (TS_BC_7 , P2_5 , bidir , X , 87 , 0 , Z ),"&
" 85 (BC_2 , * , control , 0 ) ,"&
" 84 (TS_BC_7 , P2_6 , bidir , X , 85 , 0 , Z ),"&
" 83 (BC_2 , * , control , 0 ) ,"&
" 82 (TS_BC_7 , P2_7 , bidir , X , 83 , 0 , Z ),"&
" 81 (BC_2 , * , control , 0 ) ,"&
" 80 (TS_BC_7 , P3_0 , bidir , X , 81 , 0 , Z ),"&
" 79 (BC_2 , * , control , 0 ) ,"&
" 78 (TS_BC_7 , P3_1 , bidir , X , 79 , 0 , Z ),"&
" 77 (BC_2 , * , control , 0 ) ,"&
" 76 (TS_BC_7 , P5_0 , bidir , X , 77 , 0 , Z ),"&
" 75 (BC_2 , * , control , 0 ) ,"&
" 74 (TS_BC_7 , P5_1 , bidir , X , 75 , 0 , Z ),"&
" 73 (BC_2 , * , control , 0 ) ,"&
" 72 (TS_BC_7 , P5_2 , bidir , X , 73 , 0 , Z ),"&
" 71 (BC_2 , * , control , 0 ) ,"&
" 70 (TS_BC_7 , P5_6 , bidir , X , 71 , 0 , Z ),"&
" 69 (BC_2 , * , control , 0 ) ,"&
" 68 (TS_BC_7 , P5_7 , bidir , X , 69 , 0 , Z ),"&
" 67 (BC_2 , * , control , 0 ) ,"&
" 66 (TS_BC_7 , P6_2 , bidir , X , 67 , 0 , Z ),"&
" 65 (BC_2 , * , control , 0 ) ,"&
" 64 (TS_BC_7 , P6_3 , bidir , X , 65 , 0 , Z ),"&
" 63 (BC_2 , * , control , 0 ) ,"&
" 62 (TS_BC_7 , P7_0 , bidir , X , 63 , 0 , Z ),"&
" 61 (BC_2 , * , control , 0 ) ,"&
" 60 (TS_BC_7 , P7_1 , bidir , X , 61 , 0 , Z ),"&
" 59 (BC_2 , * , control , 0 ) ,"&
" 58 (TS_BC_7 , P7_2 , bidir , X , 59 , 0 , Z ),"&
" 57 (BC_2 , * , control , 0 ) ,"&
" 56 (TS_BC_7 , P7_3 , bidir , X , 57 , 0 , Z ),"&
" 55 (BC_2 , * , control , 0 ) ,"&
" 54 (TS_BC_7 , P7_4 , bidir , X , 55 , 0 , Z ),"&
" 53 (BC_2 , * , control , 0 ) ,"&
" 52 (TS_BC_7 , P7_5 , bidir , X , 53 , 0 , Z ),"&
" 51 (BC_2 , * , control , 0 ) ,"&
" 50 (TS_BC_7 , P7_7 , bidir , X , 51 , 0 , Z ),"&
" 49 (BC_2 , * , control , 0 ) ,"&
" 48 (TS_BC_7 , P8_0 , bidir , X , 49 , 0 , Z ),"&
" 47 (BC_2 , * , control , 0 ) ,"&
" 46 (TS_BC_7 , P8_1 , bidir , X , 47 , 0 , Z ),"&
" 45 (BC_2 , * , control , 0 ) ,"&
" 44 (TS_BC_7 , P9_0 , bidir , X , 45 , 0 , Z ),"&
" 43 (BC_2 , * , control , 0 ) ,"&
" 42 (TS_BC_7 , P9_1 , bidir , X , 43 , 0 , Z ),"&
" 41 (BC_2 , * , control , 0 ) ,"&
" 40 (TS_BC_7 , P9_2 , bidir , X , 41 , 0 , Z ),"&
" 39 (BC_2 , * , control , 0 ) ,"&
" 38 (TS_BC_7 , P9_3 , bidir , X , 39 , 0 , Z ),"&
" 37 (BC_2 , * , control , 0 ) ,"&
" 36 (TS_BC_7 , P9_4 , bidir , X , 37 , 0 , Z ),"&
" 35 (BC_2 , * , control , 0 ) ,"&
" 34 (TS_BC_7 , P9_5 , bidir , X , 35 , 0 , Z ),"&
" 33 (BC_2 , * , control , 0 ) ,"&
" 32 (TS_BC_7 , P10_0 , bidir , X , 33 , 0 , Z ),"&
" 31 (BC_2 , * , control , 0 ) ,"&
" 30 (TS_BC_7 , P10_1 , bidir , X , 31 , 0 , Z ),"&
" 29 (BC_2 , * , control , 0 ) ,"&
" 28 (TS_BC_7 , P10_2 , bidir , X , 29 , 0 , Z ),"&
" 27 (BC_2 , * , control , 0 ) ,"&
" 26 (TS_BC_7 , P10_3 , bidir , X , 27 , 0 , Z ),"&
" 25 (BC_2 , * , control , 0 ) ,"&
" 24 (TS_BC_7 , P10_4 , bidir , X , 25 , 0 , Z ),"&
" 23 (BC_2 , * , control , 0 ) ,"&
" 22 (TS_BC_7 , P10_5 , bidir , X , 23 , 0 , Z ),"&
" 21 (BC_2 , * , control , 0 ) ,"&
" 20 (TS_BC_7 , P10_6 , bidir , X , 21 , 0 , Z ),"&
" 19 (BC_2 , * , control , 0 ) ,"&
" 18 (TS_BC_7 , P10_7 , bidir , X , 19 , 0 , Z ),"&
" 17 (BC_2 , * , control , 0 ) ,"&
" 16 (TS_BC_7 , P11_1 , bidir , X , 17 , 0 , Z ),"&
" 15 (BC_2 , * , control , 0 ) ,"&
" 14 (TS_BC_7 , P11_2 , bidir , X , 15 , 0 , Z ),"&
" 13 (BC_2 , * , control , 0 ) ,"&
" 12 (TS_BC_7 , P11_3 , bidir , X , 13 , 0 , Z ),"&
" 11 (BC_2 , * , control , 0 ) ,"&
" 10 (TS_BC_7 , P11_4 , bidir , X , 11 , 0 , Z ),"&
" 9 (BC_2 , * , control , 0 ) ,"&
" 8 (TS_BC_7 , P11_5 , bidir , X , 9 , 0 , Z ),"&
" 7 (BC_2 , * , control , 0 ) ,"&
" 6 (TS_BC_7 , P11_6 , bidir , X , 7 , 0 , Z ),"&
" 5 (BC_2 , * , control , 0 ) ,"&
" 4 (TS_BC_7 , P11_7 , bidir , X , 5 , 0 , Z ),"&
" 3 (BC_2 , * , control , 0 ) ,"&
" 2 (TS_BC_7 , P12_6 , bidir , X , 3 , 0 , Z ),"&
" 1 (BC_2 , * , control , 0 ) ,"&
" 0 (TS_BC_7 , P12_7 , bidir , X , 1 , 0 , Z ) ";
end CY8C6244AZI_S4D93;