----------------------------------------------
-- BSDL for ADSP_BF518 LQFP_PACKAGE
-- 176 LQFP Package
-- Revision 0.1 (May 23, 2010)
----------------------------------------------
-- * NOTE:
-- * Due to TWI functionality, drivers for pins SDA and SCL
-- * are open-drain and therefore can only tri-state or drive 0. Loading
-- * the output cells with 1 will result in the driver tri-stating. Please keep
-- * the following in mind:
-- * - When configuring O/D pins as outputs(i.e. for EXTEST), internal cells
-- * 72(SDA) and 75(SCL) must always be
-- * loaded with 1
-- * - When configuring O/D pins as inputs, output2 cells 71(SDA) and
-- * 74(SCL) must be loaded with 1
----------------------------------------------
entity ADSP_BF518 is
generic (PHYSICAL_PIN_MAP : string:="LQFP_PACKAGE");
port (
NMI: in bit;
CLKIN: linkage bit;
TRST: in bit;
TMS: in bit;
CLKBUF: linkage bit;
PG_n: linkage bit;
BMODE0: in bit;
RTXI: linkage bit;
BMODE1: in bit;
TCK: in bit;
BMODE2: in bit;
TDI: in bit;
RESET: in bit;
PH0: inout bit;
PH1: inout bit;
PH2: inout bit;
PH7: inout bit;
PH3: inout bit;
PH4: inout bit;
PH5: inout bit;
PF10: inout bit;
PF11: inout bit;
PF12: inout bit;
PF13: inout bit;
PF14: inout bit;
PF15: inout bit;
PG0: inout bit;
PG1: inout bit;
PG2: inout bit;
PG3: inout bit;
PG4: inout bit;
PH6: inout bit;
PG5: inout bit;
PG6: inout bit;
DATA11: inout bit;
PG7: inout bit;
PG8: inout bit;
PG9: inout bit;
DATA10: inout bit;
SCL: inout bit;
DATA15: inout bit;
DATA12: inout bit;
DATA13: inout bit;
SDA: inout bit;
DATA14: inout bit;
PG10: inout bit;
PG11: inout bit;
DATA0: inout bit;
PG12: inout bit;
DATA1: inout bit;
PG13: inout bit;
DATA2: inout bit;
PG14: inout bit;
PF0: inout bit;
DATA3: inout bit;
PG15: inout bit;
PF1: inout bit;
DATA4: inout bit;
PF2: inout bit;
DATA5: inout bit;
PF3: inout bit;
DATA6: inout bit;
PF4: inout bit;
DATA7: inout bit;
PF5: inout bit;
DATA8: inout bit;
PF6: inout bit;
DATA9: inout bit;
PF7: inout bit;
PF8: inout bit;
PF9: inout bit;
XTAL: linkage bit;
ADDR5: out bit;
CLKOUT: out bit;
ADDR6: out bit;
TDO: out bit;
ADDR7: out bit;
SA10: out bit;
SMS_n: out bit;
AWE_n: out bit;
ADDR8: out bit;
ADDR9: out bit;
ARE_n: out bit;
SCAS_n: out bit;
ABE_n0: out bit;
ABE_n1: out bit;
SRAS_n: out bit;
SCKE: out bit;
ADDR10: out bit;
ADDR11: out bit;
ADDR12: out bit;
ADDR13: out bit;
ADDR14: out bit;
SWE_n: out bit;
ADDR15: out bit;
ADDR16: out bit;
ADDR17: out bit;
ADDR18: out bit;
ADDR19: out bit;
AMS_n0: out bit;
AMS_n1: out bit;
RTXO: linkage bit;
ADDR1: out bit;
ADDR2: out bit;
ADDR3: out bit;
EXT_WAKE: linkage bit;
ADDR4: out bit;
EMU: linkage bit;
VDDINT: linkage bit_vector(0 to 10);
GND: linkage bit_vector(0 to 29);
VDDEXT: linkage bit_vector(0 to 10);
VDDFLASH: linkage bit_vector(0 to 3);
VDDOTP: linkage bit;
VDDRTC: linkage bit;
VDDMEM: linkage bit_vector(0 to 7);
VPPOTP: linkage bit);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of ADSP_BF518: entity is "STD_1149_1_1990";
attribute PIN_MAP of ADSP_BF518: entity is PHYSICAL_PIN_MAP;
constant LQFP_PACKAGE: PIN_MAP_STRING:=
"NMI: 147," &
"CLKIN: 143," &
"TRST: 54," &
"TMS: 55," &
"CLKBUF: 150," &
"PG_n: 135," &
"BMODE0: 42," &
"RTXI: 141," &
"BMODE1: 41," &
"TCK: 53," &
"BMODE2: 40," &
"TDI: 52," &
"PH0: 162," &
"PH1: 161," &
"PH2: 160," &
"PH7: 153," &
"PH3: 159," &
"PH4: 156," &
"PH5: 155," &
"PF10: 174," &
"PF11: 171," &
"PF12: 168," &
"PF13: 167," &
"PF14: 166," &
"PF15: 165," &
"PG0: 48," &
"PG1: 47," &
"PG2: 39," &
"PG3: 38," &
"PG4: 37," &
"PH6: 154," &
"PG5: 36," &
"PG6: 34," &
"DATA11: 61," &
"PG7: 33," &
"PG8: 32," &
"PG9: 31," &
"DATA10: 62," &
"SCL: 173," &
"DATA15: 56," &
"DATA12: 60," &
"DATA13: 58," &
"SDA: 172," &
"DATA14: 57," &
"PG10: 28," &
"PG11: 27," &
"DATA0: 76," &
"PG12: 26," &
"DATA1: 74," &
"PG13: 25," &
"DATA2: 73," &
"PG14: 21," &
"PF0: 19," &
"DATA3: 72," &
"PG15: 20," &
"PF1: 18," &
"DATA4: 71," &
"PF2: 13," &
"DATA5: 70," &
"PF3: 12," &
"DATA6: 69," &
"PF4: 11," &
"DATA7: 66," &
"PF5: 10," &
"DATA8: 65," &
"PF6: 6," &
"DATA9: 64," &
"PF7: 5," &
"PF8: 4," &
"PF9: 3," &
"XTAL: 144," &
"ADDR5: 102," &
"CLKOUT: 125," &
"ADDR6: 101," &
"TDO: 50," &
"ADDR7: 97," &
"SA10: 110," &
"SMS_n: 118," &
"AWE_n: 122," &
"ADDR8: 96," &
"ADDR9: 94," &
"ARE_n: 121," &
"SCAS_n: 114," &
"ABE_n0: 109," &
"ABE_n1: 108," &
"SRAS_n: 115," &
"SCKE: 119," &
"ADDR10: 93," &
"ADDR11: 92," &
"ADDR12: 91," &
"ADDR13: 86," &
"ADDR14: 85," &
"SWE_n: 113," &
"ADDR15: 84," &
"ADDR16: 81," &
"ADDR17: 80," &
"ADDR18: 78," &
"ADDR19: 77," &
"RESET: 146," &
"AMS_n0: 123," &
"AMS_n1: 120," &
"RTXO: 140," &
"ADDR1: 107," &
"ADDR2: 106," &
"ADDR3: 105," &
"EXT_WAKE: 130," &
"ADDR4: 103," &
"EMU: 51," &
"VDDINT: (14,23,30,63,79,98,100,116,138,152,164)," &
"GND: (1,2,15,22,43,44,45,46,67,83,87,88,89,90,99,111,117,131,132,133,134,137,139,149,151,157,163,169,175,176)," &
"VDDEXT: (136,7,24,35,49,128,129,145,148,158,170)," &
"VDDFLASH: (16,17,29,126)," &
"VDDOTP: 9," &
"VDDRTC: 142," &
"VDDMEM: (59,68,75,82,95,104,112,124)," &
"VPPOTP: 8";
attribute TAP_SCAN_IN of TDI: signal is true;
attribute TAP_SCAN_MODE of TMS: signal is true;
attribute TAP_SCAN_OUT of TDO: signal is true;
attribute TAP_SCAN_RESET of TRST: signal is true;
attribute TAP_SCAN_CLOCK of TCK: signal is (20.0e6, BOTH);
attribute INSTRUCTION_LENGTH of ADSP_BF518: entity is 5;
-- Unspecified opcodes assigned to Bypass.
attribute INSTRUCTION_OPCODE of ADSP_BF518: entity is
"BYPASS (11111)," &
"EXTEST (00000)," &
"SAMPLE (10000)," &
"IDCODE (00010)," &
"PRIVATE (01000, " &
" 00100, " &
" 10100, " &
" 01100, " &
" 01010, " &
" 00110, " &
" 10110, " &
" 11110) " ;
attribute INSTRUCTION_CAPTURE of ADSP_BF518: entity is "00001";
attribute INSTRUCTION_PRIVATE of ADSP_BF518: entity is "PRIVATE";
attribute IDCODE_REGISTER of ADSP_BF518 : entity is
--Select your silicon revision
--"0000" & -- Version: Revision 0.0
"0001" & -- Version: Revision 0.1
--"0002" & -- Version: Revision 0.2
"0010011111100100" & -- Part number
"00001100101" & -- ADI manufacturing code
"1"; -- Required bit
attribute BOUNDARY_LENGTH of ADSP_BF518: entity is 200;
attribute BOUNDARY_REGISTER of ADSP_BF518: entity is
--num cell port function safe [ccell disval rslt]
" 0 (BC_1, ADDR12, output3, X, 7, 0, Z)," &
" 1 (BC_1, ADDR11, output3, X, 7, 0, Z), " &
" 2 (BC_1, ADDR10, output3, X, 7, 0, Z), " &
" 3 (BC_1, ADDR9, output3, X, 7, 0, Z), " &
" 4 (BC_1, ADDR8, output3, X, 7, 0, Z), " &
" 5 (BC_1, ADDR7, output3, X, 7, 0, Z), " &
" 6 (BC_1, ADDR6, output3, X, 7, 0, Z), " &
" 7 (BC_1, *, control, 0), " &
" 8 (BC_1, ADDR5, output3, X, 7, 0, Z), " &
" 9 (BC_1, ADDR4, output3, X, 7, 0, Z), " &
" 10 (BC_1, ADDR3, output3, X, 7, 0, Z), " &
" 11 (BC_1, ADDR2, output3, X, 7, 0, Z), " &
" 12 (BC_1, ADDR1, output3, X, 7, 0, Z), " &
" 13 (BC_1, ABE_n1, output3, X, 7, 0, Z), " &
" 14 (BC_1, ABE_n0, output3, X, 7, 0, Z), " &
" 15 (BC_1, SA10, output3, X, 28, 0, Z), " &
" 16 (BC_1, SWE_n, output3, X, 28, 0, Z), " &
" 17 (BC_1, SCAS_n, output3, X, 28, 0, Z), " &
" 18 (BC_1, SRAS_n, output3, X, 28, 0, Z), " &
" 19 (BC_2, *, internal, 0), " &
" 20 (BC_1, SMS_n, output3, X, 28, 0, Z), " &
" 21 (BC_1, SCKE, output3, X, 28, 0, Z), " &
" 22 (BC_1, AMS_n1, output3, X, 24, 0, Z), " &
" 23 (BC_1, ARE_n, output3, X, 24, 0, Z), " &
" 24 (BC_1, *, control, 0), " &
" 25 (BC_1, AWE_n, output3, X, 24, 0, Z), " &
" 26 (BC_1, AMS_n0, output3, X, 24, 0, Z), " &
" 27 (BC_1, CLKOUT, output3, X, 28, 0, Z), " &
" 28 (BC_1, *, control, 0), " &
" 29 (BC_2, RESET, input, X), " &
" 30 (BC_2, NMI, input, X), " &
" 31 (BC_2, PH7, input, X), " &
" 32 (BC_1, PH7, output3, X, 33, 0, Z), " &
" 33 (BC_1, *, control, 0), " &
" 34 (BC_2, PH6, input, X), " &
" 35 (BC_1, PH6, output3, X, 36, 0, Z), " &
" 36 (BC_1, *, control, 0), " &
" 37 (BC_2, PH5, input, X), " &
" 38 (BC_1, PH5, output3, X, 39, 0, Z), " &
" 39 (BC_1, *, control, 0), " &
" 40 (BC_2, PH4, input, X), " &
" 41 (BC_1, PH4, output3, X, 42, 0, Z), " &
" 42 (BC_1, *, control, 0), " &
" 43 (BC_2, PH3, input, X), " &
" 44 (BC_1, PH3, output3, X, 45, 0, Z), " &
" 45 (BC_1, *, control, 0), " &
" 46 (BC_2, PH2, input, X), " &
" 47 (BC_1, PH2, output3, X, 48, 0, Z), " &
" 48 (BC_1, *, control, 0), " &
" 49 (BC_2, PH1, input, X), " &
" 50 (BC_1, PH1, output3, X, 51, 0, Z), " &
" 51 (BC_1, *, control, 0), " &
" 52 (BC_2, PH0, input, X), " &
" 53 (BC_1, PH0, output3, X, 54, 0, Z), " &
" 54 (BC_1, *, control, 0), " &
" 55 (BC_2, PF15, input, X), " &
" 56 (BC_1, PF15, output3, X, 57, 0, Z), " &
" 57 (BC_1, *, control, 0), " &
" 58 (BC_2, PF14, input, X), " &
" 59 (BC_1, PF14, output3, X, 60, 0, Z), " &
" 60 (BC_1, *, control, 0), " &
" 61 (BC_2, PF13, input, X), " &
" 62 (BC_1, PF13, output3, X, 63, 0, Z), " &
" 63 (BC_1, *, control, 0), " &
" 64 (BC_2, PF12, input, X), " &
" 65 (BC_1, PF12, output3, X, 66, 0, Z), " &
" 66 (BC_1, *, control, 0), " &
" 67 (BC_2, PF11, input, X), " &
" 68 (BC_1, PF11, output3, X, 69, 0, Z), " &
" 69 (BC_1, *, control, 0), " &
" 70 (BC_2, SDA, input, X), " &
" 71 (BC_1, SDA, output2, 1, 71, 1, WEAK1), " &
" 72 (BC_1, *, internal, 1), " &
" 73 (BC_2, SCL, input, X), " &
" 74 (BC_1, SCL, output2, 1, 74, 1, WEAK1), " &
" 75 (BC_1, *, internal, 1), " &
" 76 (BC_2, PF10, input, X), " &
" 77 (BC_1, PF10, output3, X, 78, 0, Z), " &
" 78 (BC_1, *, control, 0), " &
" 79 (BC_2, PF9, input, X), " &
" 80 (BC_1, PF9, output3, X, 81, 0, Z), " &
" 81 (BC_1, *, control, 0), " &
" 82 (BC_2, PF8, input, X), " &
" 83 (BC_1, PF8, output3, X, 84, 0, Z), " &
" 84 (BC_1, *, control, 0), " &
" 85 (BC_2, PF7, input, X), " &
" 86 (BC_1, PF7, output3, X, 87, 0, Z), " &
" 87 (BC_1, *, control, 0), " &
" 88 (BC_2, PF6, input, X), " &
" 89 (BC_1, PF6, output3, X, 90, 0, Z), " &
" 90 (BC_1, *, control, 0), " &
" 91 (BC_2, PF5, input, X), " &
" 92 (BC_1, PF5, output3, X, 93, 0, Z), " &
" 93 (BC_1, *, control, 0), " &
" 94 (BC_2, PF4, input, X), " &
" 95 (BC_1, PF4, output3, X, 96, 0, Z), " &
" 96 (BC_1, *, control, 0), " &
" 97 (BC_2, PF3, input, X), " &
" 98 (BC_1, PF3, output3, X, 99, 0, Z), " &
" 99 (BC_1, *, control, 0), " &
" 100 (BC_2, PF2, input, X), " &
" 101 (BC_1, PF2, output3, X, 102, 0, Z), " &
" 102 (BC_1, *, control, 0), " &
" 103 (BC_2, PF1, input, X), " &
" 104 (BC_1, PF1, output3, X, 105, 0, Z), " &
" 105 (BC_1, *, control, 0), " &
" 106 (BC_2, PF0, input, X), " &
" 107 (BC_1, PF0, output3, X, 108, 0, Z), " &
" 108 (BC_1, *, control, 0), " &
" 109 (BC_2, PG15, input, X), " &
" 110 (BC_1, PG15, output3, X, 111, 0, Z), " &
" 111 (BC_1, *, control, 0), " &
" 112 (BC_2, PG14, input, X), " &
" 113 (BC_1, PG14, output3, X, 114, 0, Z), " &
" 114 (BC_1, *, control, 0), " &
" 115 (BC_2, PG13, input, X), " &
" 116 (BC_1, PG13, output3, X, 117, 0, Z), " &
" 117 (BC_1, *, control, 0), " &
" 118 (BC_2, PG12, input, X), " &
" 119 (BC_1, PG12, output3, X, 120, 0, Z), " &
" 120 (BC_1, *, control, 0), " &
" 121 (BC_2, PG11, input, X), " &
" 122 (BC_1, PG11, output3, X, 123, 0, Z), " &
" 123 (BC_1, *, control, 0), " &
" 124 (BC_2, PG10, input, X), " &
" 125 (BC_1, PG10, output3, X, 126, 0, Z), " &
" 126 (BC_1, *, control, 0), " &
" 127 (BC_2, PG9, input, X), " &
" 128 (BC_1, PG9, output3, X, 129, 0, Z), " &
" 129 (BC_1, *, control, 0), " &
" 130 (BC_2, PG8, input, X), " &
" 131 (BC_1, PG8, output3, X, 132, 0, Z), " &
" 132 (BC_1, *, control, 0), " &
" 133 (BC_2, PG7, input, X), " &
" 134 (BC_1, PG7, output3, X, 135, 0, Z), " &
" 135 (BC_1, *, control, 0), " &
" 136 (BC_2, PG6, input, X), " &
" 137 (BC_1, PG6, output3, X, 138, 0, Z), " &
" 138 (BC_1, *, control, 0), " &
" 139 (BC_2, PG5, input, X), " &
" 140 (BC_1, PG5, output3, X, 141, 0, Z), " &
" 141 (BC_1, *, control, 0), " &
" 142 (BC_2, PG4, input, X), " &
" 143 (BC_1, PG4, output3, X, 144, 0, Z), " &
" 144 (BC_1, *, control, 0), " &
" 145 (BC_2, PG3, input, X), " &
" 146 (BC_1, PG3, output3, X, 147, 0, Z), " &
" 147 (BC_1, *, control, 0), " &
" 148 (BC_2, PG2, input, X), " &
" 149 (BC_1, PG2, output3, X, 150, 0, Z), " &
" 150 (BC_1, *, control, 0), " &
" 151 (BC_2, BMODE2, input, X), " &
" 152 (BC_2, BMODE1, input, X), " &
" 153 (BC_2, BMODE0, input, X), " &
" 154 (BC_2, PG1, input, X), " &
" 155 (BC_1, PG1, output3, X, 156, 0, Z), " &
" 156 (BC_1, *, control, 0), " &
" 157 (BC_2, PG0, input, X), " &
" 158 (BC_1, PG0, output3, X, 159, 0, Z), " &
" 159 (BC_1, *, control, 0), " &
" 160 (BC_2, DATA15, input, X), " &
" 161 (BC_1, DATA15, output3, X, 199, 0, Z), " &
" 162 (BC_2, DATA14, input, X), " &
" 163 (BC_1, DATA14, output3, X, 199, 0, Z), " &
" 164 (BC_2, DATA13, input, X), " &
" 165 (BC_1, DATA13, output3, X, 199, 0, Z), " &
" 166 (BC_2, DATA12, input, X), " &
" 167 (BC_1, DATA12, output3, X, 199, 0, Z), " &
" 168 (BC_2, DATA11, input, X), " &
" 169 (BC_1, DATA11, output3, X, 199, 0, Z), " &
" 170 (BC_2, DATA10, input, X), " &
" 171 (BC_1, DATA10, output3, X, 199, 0, Z), " &
" 172 (BC_2, DATA9, input, X), " &
" 173 (BC_1, DATA9, output3, X, 199, 0, Z), " &
" 174 (BC_2, DATA8, input, X), " &
" 175 (BC_1, DATA8, output3, X, 199, 0, Z), " &
" 176 (BC_2, DATA7, input, X), " &
" 177 (BC_1, DATA7, output3, X, 199, 0, Z), " &
" 178 (BC_2, DATA6, input, X), " &
" 179 (BC_1, DATA6, output3, X, 199, 0, Z), " &
" 180 (BC_2, DATA5, input, X), " &
" 181 (BC_1, DATA5, output3, X, 199, 0, Z), " &
" 182 (BC_2, DATA4, input, X), " &
" 183 (BC_1, DATA4, output3, X, 199, 0, Z), " &
" 184 (BC_2, DATA3, input, X), " &
" 185 (BC_1, DATA3, output3, X, 199, 0, Z), " &
" 186 (BC_2, DATA2, input, X), " &
" 187 (BC_1, DATA2, output3, X, 199, 0, Z), " &
" 188 (BC_2, DATA1, input, X), " &
" 189 (BC_1, DATA1, output3, X, 199, 0, Z), " &
" 190 (BC_2, DATA0, input, X), " &
" 191 (BC_1, DATA0, output3, X, 199, 0, Z), " &
" 192 (BC_1, ADDR19, output3, X, 7, 0, Z), " &
" 193 (BC_1, ADDR18, output3, X, 7, 0, Z), " &
" 194 (BC_1, ADDR17, output3, X, 7, 0, Z), " &
" 195 (BC_1, ADDR16, output3, X, 7, 0, Z), " &
" 196 (BC_1, ADDR15, output3, X, 7, 0, Z), " &
" 197 (BC_1, ADDR14, output3, X, 7, 0, Z), " &
" 198 (BC_1, ADDR13, output3, X, 7, 0, Z), " &
" 199 (BC_1, *, control, 0)";
end ADSP_BF518;
