--------------------------------------------------------------------------------
-- Freescale Boundary Scan Description Language --
--------------------------------------------------------------------------------
-- Boundary Scan Description Language (IEEE 1149.1b) --
-- --
-- Device : P1010 Revision R2.01 --
-- File Version : A --
-- File created : Modified R1 file manually which was generated by --
-- Viper version: 2010.03.15 --
-- File Time : at: Tue Mar 31 11:32:07 2015 --
-- Package type : PBGA --
-- BSDL_status : preliminary --
-- --
--------------------------------------------------------------------------------
-- Revision History: --
-- A - Original version created by manually modifying the rev-1 model --
-- by Rajkumar Agrawal --
-- --
-- NOTE: The IEEE 1149.1 standard optional instructions HIGHZ, CLAMP, and --
-- IDCODE are supported. --
-- --
-- WARNING : INCORRECT VOLTAGE SELECT SETTINGS CAN LEAD TO IRREVERSIBLE --
-- DEVICE DAMAGE. BVDD_VSEL0, BVDD_VSEL1, voltage selects must be --
-- correctly set to match BVDD power levels. --
-- --
-- The VSELs are to be set as follows. --
-- --
-- Voltage Select Setting Supply Voltage --
-- BVDD_VSEL0,BVDD_VSEL1 00 BVDD = 3.3V --
-- 01 BVDD = 2.5V --
-- 10 BVDD = 1.8V --
-- 11 BVDD = 3.3V --
-- --
-- WARNING: UDP/UDM pins are non-complaint with IEEE 1149.1 Standard. --
-- Description --
-- ------------ --
-- UDP/UDM are functionally a differential bi-directional pair but --
-- have been implemented as separate input only pins in boundary scan --
-- operations for EXTEST, CLAMP,and SAMPLE. The drivers are disabled --
-- during these instructions. If the pins can be driven during the --
-- 1149.1 test, then the interconnect can be tested. --
-- --
-- NOTE: For assistance with this file, contact your sales office. --
-- --
-- --
--------------------------------------------------------------------------------
-- --
-- --
--============================================================================--
-- IMPORTANT NOTICE --
-- This information is provided on an AS IS basis and without warranty. --
-- IN NO EVENT SHALL Freescale BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL --
-- DAMAGES ARISING FROM USE OF THIS INFORMATION. THIS DISCLAIMER OF --
-- WARRANTY EXTENDS TO THE USER OF THE INFORMATION, AND TO THEIR CUSTOMERS --
-- OR USERS OF PRODUCTS AND IS IN LIEU OF ALL WARRANTIES WHETHER EXPRESS, --
-- IMPLIED, OR STATUTORY, INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY --
-- OR FITNESS FOR PARTICULAR PURPOSE. --
-- --
-- Freescale does not represent or warrant that the information furnished --
-- hereunder is free of infringement of any third party patents, --
-- copyrights, trade secrets, or other intellectual property rights. --
-- Freescale does not represent or warrant that the information is free of --
-- defect, or that it meets any particular standard, requirements or need --
-- of the user of the infomation or their customers. --
-- --
-- Freescale reserves the right to change the information in this file --
-- without notice. --
-- --
-- --
--============================================================================--
entity P1010 is
generic (PHYSICAL_PIN_MAP : string := "PBGA");
-- PORT DESCRIPTION TERMS
-- in = input only
-- out = three-state output (0, Z, 1)
-- buffer = two-state output (0, 1)
-- inout = bidirectional
-- linkage = OTHER (vdd, vss, analog)
--
-- bit = single pin
-- bit_vector = group of pins with suffix 0 to n
port (
BVDD_VSEL0: in bit;
BVDD_VSEL1: in bit;
CAN1_RX: inout bit;
CAN1_TX: inout bit;
CAN2_RX: inout bit;
CAN2_TX: inout bit;
EC_MDC: inout bit;
EC_MDIO: inout bit;
GPIO: inout bit_vector(0 to 5);
HRESET_B: in bit;
HRESET_REQ_B: inout bit;
IBIAS_REXT: in bit;
IFC_AD: inout bit_vector(0 to 15);
IFC_ADDR: inout bit_vector(16 to 24);
IFC_AVD: inout bit;
IFC_BCTL: inout bit;
IFC_CLE: inout bit;
IFC_CLK: inout bit_vector(0 to 1);
IFC_CS_B: inout bit_vector(0 to 1);
IFC_OE_B: inout bit;
IFC_PAR: inout bit_vector(0 to 1);
IFC_PERR_B: inout bit;
IFC_RB_B: inout bit;
IFC_WE_B: inout bit;
IFC_WP_B: inout bit;
IIC1_SCL: inout bit;
IIC1_SDA: inout bit;
IIC2_SCL: inout bit;
IIC2_SDA: inout bit;
IRQ: in bit_vector(0 to 0);
IRQ01: inout bit;
IRQ02: inout bit;
IRQ03: inout bit;
IRQ_OUT_B: inout bit;
MA: inout bit_vector(0 to 15);
MBA: inout bit_vector(0 to 2);
MCAS_B: inout bit;
MCK: out bit;
MCKE: out bit_vector(0 to 1);
MCK_B: out bit;
MCS_B00: out bit;
MCS_B01: out bit;
MCS_B02: out bit;
MCS_B03: out bit;
MDIC: inout bit_vector(0 to 1);
MDM: inout bit_vector(0 to 3);
MDQ: inout bit_vector(0 to 31);
MDQS: inout bit_vector(0 to 3);
MDQS_B00: inout bit;
MDQS_B01: inout bit;
MDQS_B02: inout bit;
MDQS_B03: inout bit;
MODT: out bit_vector(0 to 1);
MRAS_B: inout bit;
MWE_B: inout bit;
READY: inout bit;
RTC: in bit;
SCAN_MODE_B: in bit;
SD1_PLL_TPD: out bit;
SD1_REF_CLK: in bit;
SD1_REF_CLK_B: in bit;
SD1_RXA_N: in bit;
SD1_RXA_P: in bit;
SD1_RXB_N: in bit;
SD1_RXB_P: in bit;
SD1_RXE_N: in bit;
SD1_RXE_P: in bit;
SD1_RXF_N: in bit;
SD1_RXF_P: in bit;
SD1_TXA_N: out bit;
SD1_TXA_P: out bit;
SD1_TXB_N: out bit;
SD1_TXB_P: out bit;
SD1_TXE_N: out bit;
SD1_TXE_P: out bit;
SD1_TXF_N: out bit;
SD1_TXF_P: out bit;
SD2_PLL_TPD: out bit;
SD2_REF_CLK: in bit;
SD2_REF_CLK_B: in bit;
SD2_RXA_N: in bit;
SD2_RXA_P: in bit;
SD2_RXE_N: in bit;
SD2_RXE_P: in bit;
SD2_TXA_N: out bit;
SD2_TXA_P: out bit;
SD2_TXE_N: out bit;
SD2_TXE_P: out bit;
SPI_CLK: inout bit;
SPI_CS0_B: inout bit;
SPI_MISO: inout bit;
SPI_MOSI: inout bit;
SYSCLK: in bit;
TCK: in bit;
TDI: in bit;
TDO: out bit;
TMS: in bit;
TRST_B: in bit;
TSEC1_GTX_CLK: inout bit;
TSEC1_GTX_CLK125: inout bit;
TSEC1_RXD: inout bit_vector(0 to 3);
TSEC1_RX_CLK: inout bit;
TSEC1_RX_DV: inout bit;
TSEC1_TXD: inout bit_vector(0 to 3);
TSEC1_TX_EN: out bit;
UART_CTS_B: inout bit_vector(0 to 1);
UART_RTS_B: inout bit_vector(0 to 1);
UART_SIN: inout bit_vector(0 to 1);
UART_SOUT: inout bit_vector(0 to 1);
UDM: in bit;
UDP: in bit;
UID: in bit;
USBPHY_CLK: in bit;
VBUSCLMP: in bit;
AVDD_CORE: linkage bit;
AVDD_DDR: linkage bit;
AVDD_PLAT: linkage bit;
BVDD: linkage bit_vector(0 to 4);
FA_VDD: linkage bit;
GVDD: linkage bit_vector(0 to 10);
LVDD: linkage bit_vector(0 to 2);
MVREF: linkage bit;
NC: linkage bit;
OVDD: linkage bit_vector(0 to 4);
POVDD1: linkage bit;
POVDD2: linkage bit;
S1VDD: linkage bit_vector(0 to 8);
S1VSS: linkage bit_vector(0 to 7);
S2VDD: linkage bit_vector(0 to 4);
S2VSS: linkage bit_vector(0 to 3);
SD1_AVDD: linkage bit;
SD1_AVSS: linkage bit;
SD1_IMP_CAL_RX: linkage bit;
SD1_IMP_CAL_TX: linkage bit;
SD1_PLL_TPA: linkage bit;
SD2_AVDD: linkage bit;
SD2_AVSS: linkage bit;
SD2_IMP_CAL_RX: linkage bit;
SD2_IMP_CAL_TX: linkage bit;
SD2_PLL_TPA: linkage bit;
SENSEVDD: linkage bit;
SENSEVSS: linkage bit;
TEMP_ANODE: linkage bit;
TEMP_CATHODE: linkage bit;
USB1_0VDD: linkage bit_vector(0 to 1);
USB1_8VDD: linkage bit_vector(0 to 1);
USB3_3VDD: linkage bit_vector(0 to 1);
USBVSS: linkage bit_vector(0 to 4);
VDD: linkage bit_vector(0 to 32);
VSS: linkage bit_vector(0 to 78);
X1VDD: linkage bit_vector(0 to 4);
X1VSS: linkage bit_vector(0 to 3);
X2VDD: linkage bit_vector(0 to 3);
X2VSS: linkage bit_vector(0 to 3));
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of P1010: entity is "STD_1149_1_2001";
attribute PIN_MAP of P1010: entity is PHYSICAL_PIN_MAP;
constant PBGA :PIN_MAP_STRING :=
"CAN1_RX: D17," &
"CAN1_TX: A17," &
"CAN2_RX: B18," &
"CAN2_TX: A18," &
"EC_MDC: AA6," &
"EC_MDIO: AC2," &
"GPIO: (D23, D22, A23, B23, B21, E22)," &
"HRESET_B: E23," &
"HRESET_REQ_B: H23," &
"IBIAS_REXT: M22," &
"IFC_AD: (P21, R22, T23, T22, U23, U22," &
"V23, V22, R21, R20, T21, T20," &
"U21, V21, V20, W20)," &
"IFC_ADDR: (W23, W21, Y23, Y22, AA23, Y21," &
"AB23, AA22, AC23)," &
"IFC_AVD: AC22," &
"IFC_BCTL: AA19," &
"IFC_CLE: AA20," &
"IFC_CLK: (Y18, AC18)," &
"IFC_CS_B: (AA21, AB21)," &
"IFC_OE_B: AB20," &
"IFC_PAR: (AC19, AB18)," &
"IFC_PERR_B: AA18," &
"IFC_RB_B: Y19," &
"IFC_WE_B: AC21," &
"IFC_WP_B: AC20," &
"IIC1_SCL: B20," &
"IIC1_SDA: A21," &
"IIC2_SCL: C21," &
"IIC2_SDA: A22," &
"IRQ: (F23)," &
"IRQ01: E21," &
"IRQ02: F22," &
"IRQ03: C23," &
"IRQ_OUT_B: D21," &
"MA: (D3, D7, B6, B3, A2, C7," &
"A5, A3, C6, B5, D1, A4," &
"D5, A6, C3, A7)," &
"MBA: (C4, C5, D4)," &
"MCAS_B: F2," &
"MCK: G4," &
"MCKE: (E3, C1)," &
"MCK_B: F3," &
"MCS_B00: B1," &
"MCS_B01: C2," &
"MCS_B02: A8," &
"MCS_B03: B8," &
"MDIC: (D8, C8)," &
"MDM: (M4, L2, W3, V1)," &
"MDQ: (K4, M3, J4, N4, K3, N3," &
"G3, L3, H2, L1, G1, M2," &
"H1, N1, J2, M1, R4, V4," &
"R3, W4, T4, Y2, P3, V3," &
"R2, V2, P1, W1, R1, Y1," &
"P2, U2)," &
"MDQS: (H3, J1, T3, T1)," &
"MDQS_B00: J3," &
"MDQS_B01: K1," &
"MDQS_B02: U3," &
"MDQS_B03: U1," &
"MODT: (E2, E1)," &
"MRAS_B: F1," &
"MWE_B: F4," &
"READY: F21," &
"RTC: F20," &
"SCAN_MODE_B: H21," &
"SD1_PLL_TPD: U11," &
"SD1_REF_CLK: AA12," &
"SD1_REF_CLK_B: Y12," &
"SD1_RXA_N: AA8," &
"SD1_RXA_P: Y8," &
"SD1_RXB_N: AC11," &
"SD1_RXB_P: AB11," &
"SD1_RXE_N: AC13," &
"SD1_RXE_P: AB13," &
"SD1_RXF_N: AA16," &
"SD1_RXF_P: Y16," &
"SD1_TXA_N: AC9," &
"SD1_TXA_P: AB9," &
"SD1_TXB_N: AA10," &
"SD1_TXB_P: Y10," &
"SD1_TXE_N: AA14," &
"SD1_TXE_P: Y14," &
"SD1_TXF_N: AC15," &
"SD1_TXF_P: AB15," &
"SD2_PLL_TPD: G13," &
"SD2_REF_CLK: C12," &
"SD2_REF_CLK_B: D12," &
"SD2_RXA_N: B13," &
"SD2_RXA_P: A13," &
"SD2_RXE_N: B11," &
"SD2_RXE_P: A11," &
"SD2_TXA_N: D14," &
"SD2_TXA_P: C14," &
"SD2_TXE_N: D10," &
"SD2_TXE_P: C10," &
"SPI_CLK: C16," &
"SPI_CS0_B: D16," &
"SPI_MISO: B16," &
"SPI_MOSI: A16," &
"SYSCLK: P23," &
"TCK: G21," &
"TDI: H22," &
"TDO: G23," &
"TMS: J22," &
"TRST_B: H20," &
"TSEC1_GTX_CLK: AA3," &
"TSEC1_GTX_CLK125: Y5," &
"TSEC1_RXD: (AC4, AB4, AB3, AC3)," &
"TSEC1_RX_CLK: Y6," &
"TSEC1_RX_DV: AB6," &
"TSEC1_TXD: (AC5, AC1, AA5, AA4)," &
"TSEC1_TX_EN: AC6," &
"UART_CTS_B: (A19, A20)," &
"UART_RTS_B: (C19, D19)," &
"UART_SIN: (D18, E20)," &
"UART_SOUT: (C18, C20)," &
"UDM: L23," &
"UDP: K23," &
"UID: N23," &
"USBPHY_CLK: M20," &
"VBUSCLMP: L21," &
"AVDD_CORE: H9," &
"AVDD_DDR: N17," &
"AVDD_PLAT: P17," &
"BVDD: (T17, U16, U17, U20, AB19)," &
"BVDD_VSEL0: G17," &
"BVDD_VSEL1: H17," &
"FA_VDD: N21," &
"GVDD: (G7, G8, G9, H7, K7, L7," &
"M7, N7, P7, R7, T7)," &
"LVDD: (U7, U8, AB5)," &
"MVREF: J7," &
"NC: N22," &
"OVDD: (C17, C22, D20, G20, J20)," &
"POVDD1: P22," &
"POVDD2: N20," &
"S1VDD: (T13, Y7, Y13, AA11, AA17, AB7," &
"AB10, AB12, AB14)," &
"S1VSS: (Y11, Y17, AA7, AA13, AB17, AC10," &
"AC12, AC14)," &
"S2VDD: (A10, A12, C11, C15, H13)," &
"S2VSS: (B10, B12, D11, D15)," &
"SD1_AVDD: U12," &
"SD1_AVSS: T12," &
"SD1_IMP_CAL_RX: U10," &
"SD1_IMP_CAL_TX: U14," &
"SD1_PLL_TPA: U13," &
"SD2_AVDD: G12," &
"SD2_AVSS: H12," &
"SD2_IMP_CAL_RX: G14," &
"SD2_IMP_CAL_TX: G10," &
"SD2_PLL_TPA: G11," &
"SENSEVDD: AA2," &
"SENSEVSS: Y3," &
"TEMP_ANODE: AA1," &
"TEMP_CATHODE: AB1," &
"USB1_0VDD: (L17, M17)," &
"USB1_8VDD: (J21, K21)," &
"USB3_3VDD: (K20, L20)," &
"USBVSS: (J23, K22, L22, M21, M23)," &
"VDD: (G15, G16, H8, H10, H11, H14," &
"H15, H16, J8, J16, J17, K8," &
"K16, K17, L8, L16, M8, M16," &
"N8, N16, P8, P16, R8, R16," &
"R17, T8, T9, T10, T14, T15," &
"T16, U9, U15)," &
"VSS: (A1, A9, A15, B4, B7, B17," &
"B19, B22, D2, D6, E4, G2," &
"G22, H4, J9, J10, J11, J12," &
"J13, J14, J15, K2, K9, K10," &
"K11, K12, K13, K14, K15, L4," &
"L9, L10, L11, L12, L13, L14," &
"L15, M9, M10, M11, M12, M13," &
"M14, M15, N2, N9, N10, N11," &
"N12, N13, N14, N15, P4, P9," &
"P10, P11, P12, P13, P14, P15," &
"P20, R9, R10, R11, R12, R13," &
"R14, R15, R23, T2, U4, W2," &
"W22, Y4, Y20, AB2, AB22, AC7," &
"AC17)," &
"X1VDD: (T11, Y9, Y15, AB8, AB16)," &
"X1VSS: (AA9, AA15, AC8, AC16)," &
"X2VDD: (A14, B9, C9, C13)," &
"X2VSS: (B14, B15, D9, D13)" ;
attribute PORT_GROUPING of P1010: entity is
"DIFFERENTIAL_VOLTAGE (" &
"(MCK, MCK_B)," &
"(MDQS(0), MDQS_B00)," &
"(MDQS(1), MDQS_B01)," &
"(MDQS(2), MDQS_B02)," &
"(MDQS(3), MDQS_B03)," &
"(SD2_RXA_P, SD2_RXA_N)," &
"(SD2_RXE_P, SD2_RXE_N)," &
"(SD2_TXA_P, SD2_TXA_N)," &
"(SD2_TXE_P, SD2_TXE_N)," &
"(SD2_REF_CLK, SD2_REF_CLK_B)," &
"(SD1_RXA_P, SD1_RXA_N)," &
"(SD1_RXB_P, SD1_RXB_N)," &
"(SD1_RXE_P, SD1_RXE_N)," &
"(SD1_RXF_P, SD1_RXF_N)," &
"(SD1_TXA_P, SD1_TXA_N)," &
"(SD1_TXB_P, SD1_TXB_N)," &
"(SD1_TXE_P, SD1_TXE_N)," &
"(SD1_TXF_P, SD1_TXF_N)," &
"(SD1_REF_CLK, SD1_REF_CLK_B))" ;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (3.00e+07,BOTH);
attribute TAP_SCAN_RESET of TRST_B : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute COMPLIANCE_PATTERNS of P1010: entity is
"(SCAN_MODE_B, BVDD_VSEL0, BVDD_VSEL1) (1XX)";
attribute INSTRUCTION_LENGTH of P1010: entity is 8;
attribute INSTRUCTION_OPCODE of P1010: entity is
"BYPASS (11111111)," &
"CLAMP (11110001)," &
"EXTEST (00000000)," &
"HIGHZ (11110010)," &
"IDCODE (11110011)," &
"PRELOAD (11110000)," &
"SAMPLE (11110000)," &
"PRIVATE001 (11111110)," &
"PRIVATE002 (00000101)," &
"PRIVATE003 (00000110)," &
"PRIVATE004 (00000111)," &
"PRIVATE005 (00111000)," &
"PRIVATE006 (00000011)," &
"PRIVATE007 (00000100)," &
"PRIVATE008 (00001001)," &
"PRIVATE009 (11110100)," &
"PRIVATE010 (00010000)," &
"PRIVATE011 (00010001)," &
"PRIVATE012 (00010010)," &
"PRIVATE013 (00010011)," &
"PRIVATE014 (00010100)," &
"PRIVATE015 (00001010)," &
"PRIVATE016 (00111001)," &
"PRIVATE017 (01000000)," &
"PRIVATE018 (01000111)," &
"PRIVATE019 (01001000)," &
"PRIVATE020 (00110011)," &
"PRIVATE021 (01010100)," &
"PRIVATE022 (01010101)," &
"PRIVATE023 (01010110)," &
"PRIVATE024 (01010111)," &
"PRIVATE025 (01011000)," &
"PRIVATE026 (01010011)," &
"PRIVATE027 (01100000)," &
"PRIVATE028 (01100001)," &
"PRIVATE029 (01100010)," &
"PRIVATE030 (00110000)";
attribute INSTRUCTION_CAPTURE of P1010: entity is "xxxxxx01";
attribute INSTRUCTION_PRIVATE of P1010: entity is
"PRIVATE001," &
"PRIVATE002," &
"PRIVATE003," &
"PRIVATE004," &
"PRIVATE005," &
"PRIVATE006," &
"PRIVATE007," &
"PRIVATE008," &
"PRIVATE009," &
"PRIVATE010," &
"PRIVATE011," &
"PRIVATE012," &
"PRIVATE013," &
"PRIVATE014," &
"PRIVATE015," &
"PRIVATE016," &
"PRIVATE017," &
"PRIVATE018," &
"PRIVATE019," &
"PRIVATE020," &
"PRIVATE021," &
"PRIVATE022," &
"PRIVATE023," &
"PRIVATE024," &
"PRIVATE025," &
"PRIVATE026," &
"PRIVATE027," &
"PRIVATE028," &
"PRIVATE029," &
"PRIVATE030";
attribute IDCODE_REGISTER of P1010: entity is
"0001" & -- Version
"0110100100100011" & -- Part Number
"00000001110" & -- Manufacturer Identity
"1"; -- IEEE 1149.1 Requirement
attribute REGISTER_ACCESS of P1010: entity is
"BOUNDARY (SAMPLE)," &
"BYPASS (BYPASS)";
attribute BOUNDARY_LENGTH of P1010: entity is 367;
attribute BOUNDARY_REGISTER of P1010: entity is
-- BSR DESCRIPTION TERMS
-- cell type = BC_0 - BC_99
-- port = port name
-- function
-- input = input only
-- bidir = bidirectional
-- output2 = two state ouput
-- output3 = three state ouput
-- control = control cell
-- controlr = control cell
-- internal = placeholder cell
-- safe = value that turns off drivers in control cells
-- ccell = controlling cell number for I/O direction
-- dsval = disabling (input) value
-- rslt = result if disabled (input = Z)
--
-- num cell port/* func safe [ccell dis rslt]
"0 (BC_2, *, control, 0)," &
"1 (BC_7, IFC_PAR(1), bidir, X, 0, 0, Z)," &
"2 (BC_2, *, control, 0)," &
"3 (BC_7, IFC_PERR_B, bidir, X, 2, 0, Z)," &
"4 (BC_2, *, control, 0)," &
"5 (BC_7, IFC_CLK(0), bidir, X, 4, 0, Z)," &
"6 (BC_2, *, control, 0)," &
"7 (BC_7, IFC_PAR(0), bidir, X, 6, 0, Z)," &
"8 (BC_2, *, control, 0)," &
"9 (BC_7, IFC_BCTL, bidir, X, 8, 0, Z)," &
"10 (BC_2, *, control, 0)," &
"11 (BC_7, IFC_RB_B, bidir, X, 10, 0, Z)," &
"12 (BC_2, *, control, 0)," &
"13 (BC_7, IFC_WP_B, bidir, X, 12, 0, Z)," &
"14 (BC_2, *, control, 0)," &
"15 (BC_7, IFC_OE_B, bidir, X, 14, 0, Z)," &
"16 (BC_2, *, control, 0)," &
"17 (BC_7, IFC_CLE, bidir, X, 16, 0, Z)," &
"18 (BC_2, *, control, 0)," &
"19 (BC_7, IFC_WE_B, bidir, X, 18, 0, Z)," &
"20 (BC_2, *, control, 0)," &
"21 (BC_7, IFC_CS_B(1), bidir, X, 20, 0, Z)," &
"22 (BC_2, *, control, 0)," &
"23 (BC_7, IFC_CS_B(0), bidir, X, 22, 0, Z)," &
"24 (BC_2, *, control, 0)," &
"25 (BC_7, IFC_AVD, bidir, X, 24, 0, Z)," &
"26 (BC_2, *, control, 0)," &
"27 (BC_7, IFC_ADDR(24), bidir, X, 26, 0, Z)," &
"28 (BC_2, *, control, 0)," &
"29 (BC_7, IFC_ADDR(21), bidir, X, 28, 0, Z)," &
"30 (BC_2, *, control, 0)," &
"31 (BC_7, IFC_ADDR(20), bidir, X, 30, 0, Z)," &
"32 (BC_2, *, control, 0)," &
"33 (BC_7, IFC_ADDR(23), bidir, X, 32, 0, Z)," &
"34 (BC_2, *, control, 0)," &
"35 (BC_7, IFC_ADDR(22), bidir, X, 34, 0, Z)," &
"36 (BC_2, *, control, 0)," &
"37 (BC_7, IFC_ADDR(18), bidir, X, 36, 0, Z)," &
"38 (BC_2, *, control, 0)," &
"39 (BC_7, IFC_ADDR(19), bidir, X, 38, 0, Z)," &
"40 (BC_2, *, control, 0)," &
"41 (BC_7, IFC_ADDR(16), bidir, X, 40, 0, Z)," &
"42 (BC_2, *, control, 0)," &
"43 (BC_7, IFC_AD(12), bidir, X, 42, 0, Z)," &
"44 (BC_2, *, control, 0)," &
"45 (BC_7, IFC_ADDR(17), bidir, X, 44, 0, Z)," &
"46 (BC_2, *, control, 0)," &
"47 (BC_7, IFC_AD(11), bidir, X, 46, 0, Z)," &
"48 (BC_2, *, control, 0)," &
"49 (BC_7, IFC_AD(13), bidir, X, 48, 0, Z)," &
"50 (BC_2, *, control, 0)," &
"51 (BC_7, IFC_AD(10), bidir, X, 50, 0, Z)," &
"52 (BC_2, *, control, 0)," &
"53 (BC_7, IFC_AD(7), bidir, X, 52, 0, Z)," &
"54 (BC_2, *, control, 0)," &
"55 (BC_7, IFC_AD(8), bidir, X, 54, 0, Z)," &
"56 (BC_2, *, control, 0)," &
"57 (BC_7, IFC_AD(4), bidir, X, 56, 0, Z)," &
"58 (BC_2, *, control, 0)," &
"59 (BC_7, IFC_AD(6), bidir, X, 58, 0, Z)," &
"60 (BC_2, *, control, 0)," &
"61 (BC_7, IFC_AD(5), bidir, X, 60, 0, Z)," &
"62 (BC_2, *, control, 0)," &
"63 (BC_7, IFC_AD(3), bidir, X, 62, 0, Z)," &
"64 (BC_2, *, control, 0)," &
"65 (BC_7, IFC_AD(1), bidir, X, 64, 0, Z)," &
"66 (BC_2, *, control, 0)," &
"67 (BC_7, IFC_AD(14), bidir, X, 66, 0, Z)," &
"68 (BC_2, *, control, 0)," &
"69 (BC_7, IFC_AD(2), bidir, X, 68, 0, Z)," &
"70 (BC_2, *, control, 0)," &
"71 (BC_7, IFC_AD(0), bidir, X, 70, 0, Z)," &
"72 (BC_2, *, control, 0)," &
"73 (BC_7, IFC_AD(15), bidir, X, 72, 0, Z)," &
"74 (BC_2, *, control, 0)," &
"75 (BC_7, IFC_AD(9), bidir, X, 74, 0, Z)," &
"76 (BC_2, *, internal, X)," &
"77 (BC_2, SYSCLK, input, X)," &
"78 (BC_2, *, internal, X)," &
"79 (BC_2, USBPHY_CLK, input, X)," &
"80 (BC_4, UDP, observe_only, X)," &
"81 (BC_4, UDM, observe_only, X)," &
"82 (BC_4, VBUSCLMP, observe_only, X)," &
"83 (BC_4, UID, observe_only, X)," &
"84 (BC_4, IBIAS_REXT, observe_only, X)," &
"85 (BC_2, *, control, 0)," &
"86 (BC_7, HRESET_REQ_B, bidir, X, 85, 0, Z)," &
"87 (BC_2, *, internal, X)," &
"88 (BC_2, RTC, input, X)," &
"89 (BC_2, *, control, 0)," &
"90 (BC_7, IRQ02, bidir, X, 89, 0, Z)," &
"91 (BC_2, *, internal, X)," &
"92 (BC_2, HRESET_B, input, X)," &
"93 (BC_2, *, control, 0)," &
"94 (BC_7, READY, bidir, X, 93, 0, Z)," &
"95 (BC_2, *, control, 0)," &
"96 (BC_7, GPIO(5), bidir, X, 95, 0, Z)," &
"97 (BC_2, *, control, 0)," &
"98 (BC_7, GPIO(0), bidir, X, 97, 0, Z)," &
"99 (BC_2, *, internal, X)," &
"100 (BC_2, IRQ(0), input, X)," &
"101 (BC_2, *, control, 0)," &
"102 (BC_7, IRQ01, bidir, X, 101, 0, Z)," &
"103 (BC_2, *, control, 0)," &
"104 (BC_7, GPIO(1), bidir, X, 103, 0, Z)," &
"105 (BC_2, *, control, 0)," &
"106 (BC_7, IRQ03, bidir, X, 105, 0, Z)," &
"107 (BC_2, *, control, 0)," &
"108 (BC_7, IRQ_OUT_B, bidir, X, 107, 0, Z)," &
"109 (BC_2, *, control, 0)," &
"110 (BC_7, GPIO(3), bidir, X, 109, 0, Z)," &
"111 (BC_2, *, control, 0)," &
"112 (BC_7, GPIO(2), bidir, X, 111, 0, Z)," &
"113 (BC_2, *, control, 0)," &
"114 (BC_7, IIC2_SCL, bidir, X, 113, 0, Z)," &
"115 (BC_2, *, control, 0)," &
"116 (BC_7, GPIO(4), bidir, X, 115, 0, Z)," &
"117 (BC_2, *, control, 0)," &
"118 (BC_7, IIC2_SDA, bidir, X, 117, 0, Z)," &
"119 (BC_2, *, control, 0)," &
"120 (BC_7, IIC1_SCL, bidir, X, 119, 0, Z)," &
"121 (BC_2, *, control, 0)," &
"122 (BC_7, IIC1_SDA, bidir, X, 121, 0, Z)," &
"123 (BC_2, *, control, 0)," &
"124 (BC_7, UART_RTS_B(1), bidir, X, 123, 0, Z)," &
"125 (BC_2, *, control, 0)," &
"126 (BC_7, UART_SOUT(1), bidir, X, 125, 0, Z)," &
"127 (BC_2, *, control, 0)," &
"128 (BC_7, UART_SIN(1), bidir, X, 127, 0, Z)," &
"129 (BC_2, *, control, 0)," &
"130 (BC_7, UART_CTS_B(1), bidir, X, 129, 0, Z)," &
"131 (BC_2, *, control, 0)," &
"132 (BC_7, UART_RTS_B(0), bidir, X, 131, 0, Z)," &
"133 (BC_2, *, control, 0)," &
"134 (BC_7, UART_CTS_B(0), bidir, X, 133, 0, Z)," &
"135 (BC_2, *, control, 0)," &
"136 (BC_7, UART_SIN(0), bidir, X, 135, 0, Z)," &
"137 (BC_2, *, control, 0)," &
"138 (BC_7, UART_SOUT(0), bidir, X, 137, 0, Z)," &
"139 (BC_2, *, control, 0)," &
"140 (BC_7, CAN2_RX, bidir, X, 139, 0, Z)," &
"141 (BC_2, *, control, 0)," &
"142 (BC_7, CAN2_TX, bidir, X, 141, 0, Z)," &
"143 (BC_2, *, control, 0)," &
"144 (BC_7, CAN1_RX, bidir, X, 143, 0, Z)," &
"145 (BC_2, *, control, 0)," &
"146 (BC_7, CAN1_TX, bidir, X, 145, 0, Z)," &
"147 (BC_2, *, control, 0)," &
"148 (BC_7, SPI_CS0_B, bidir, X, 147, 0, Z)," &
"149 (BC_2, *, control, 0)," &
"150 (BC_7, SPI_CLK, bidir, X, 149, 0, Z)," &
"151 (BC_2, *, control, 0)," &
"152 (BC_7, SPI_MISO, bidir, X, 151, 0, Z)," &
"153 (BC_2, *, control, 0)," &
"154 (BC_7, SPI_MOSI, bidir, X, 153, 0, Z)," &
"155 (BC_4, SD2_RXA_P, observe_only, X)," &
"156 (BC_2, *, control, 1)," &
"157 (BC_2, SD2_TXA_P, output3, 0, 156, 1, Z)," &
"158 (BC_4, SD2_REF_CLK, clock, X)," &
"159 (BC_2, *, control, 1)," &
"160 (BC_2, SD2_PLL_TPD, output3, 0, 159, 1, Z)," &
"161 (BC_4, SD2_RXE_P, observe_only, X)," &
"162 (BC_2, *, control, 1)," &
"163 (BC_2, SD2_TXE_P, output3, 0, 162, 1, Z)," &
"164 (BC_2, *, control, 0)," &
"165 (BC_1, MCS_B02, output3, X, 164, 0, Z)," &
"166 (BC_2, *, control, 0)," &
"167 (BC_1, MCS_B03, output3, X, 166, 0, Z)," &
"168 (BC_2, *, control, 0)," &
"169 (BC_7, MDIC(1), bidir, X, 168, 0, Z)," &
"170 (BC_2, *, control, 0)," &
"171 (BC_7, MA(15), bidir, X, 170, 0, Z)," &
"172 (BC_2, *, control, 0)," &
"173 (BC_7, MDIC(0), bidir, X, 172, 0, Z)," &
"174 (BC_2, *, control, 0)," &
"175 (BC_7, MA(13), bidir, X, 174, 0, Z)," &
"176 (BC_2, *, control, 0)," &
"177 (BC_7, MA(5), bidir, X, 176, 0, Z)," &
"178 (BC_2, *, control, 0)," &
"179 (BC_7, MA(2), bidir, X, 178, 0, Z)," &
"180 (BC_2, *, control, 0)," &
"181 (BC_7, MA(6), bidir, X, 180, 0, Z)," &
"182 (BC_2, *, control, 0)," &
"183 (BC_7, MA(1), bidir, X, 182, 0, Z)," &
"184 (BC_2, *, control, 0)," &
"185 (BC_7, MA(8), bidir, X, 184, 0, Z)," &
"186 (BC_2, *, control, 0)," &
"187 (BC_7, MA(9), bidir, X, 186, 0, Z)," &
"188 (BC_2, *, control, 0)," &
"189 (BC_7, MA(11), bidir, X, 188, 0, Z)," &
"190 (BC_2, *, control, 0)," &
"191 (BC_7, MBA(1), bidir, X, 190, 0, Z)," &
"192 (BC_2, *, control, 0)," &
"193 (BC_7, MA(7), bidir, X, 192, 0, Z)," &
"194 (BC_2, *, control, 0)," &
"195 (BC_7, MA(14), bidir, X, 194, 0, Z)," &
"196 (BC_2, *, control, 0)," &
"197 (BC_7, MBA(0), bidir, X, 196, 0, Z)," &
"198 (BC_2, *, control, 0)," &
"199 (BC_7, MA(3), bidir, X, 198, 0, Z)," &
"200 (BC_2, *, control, 0)," &
"201 (BC_7, MA(4), bidir, X, 200, 0, Z)," &
"202 (BC_2, *, control, 0)," &
"203 (BC_7, MA(12), bidir, X, 202, 0, Z)," &
"204 (BC_2, *, control, 0)," &
"205 (BC_1, MCKE(1), output3, X, 204, 0, Z)," &
"206 (BC_2, *, control, 0)," &
"207 (BC_7, MBA(2), bidir, X, 206, 0, Z)," &
"208 (BC_2, *, control, 0)," &
"209 (BC_1, MCS_B01, output3, X, 208, 0, Z)," &
"210 (BC_2, *, control, 0)," &
"211 (BC_7, MA(0), bidir, X, 210, 0, Z)," &
"212 (BC_2, *, control, 0)," &
"213 (BC_1, MCS_B00, output3, X, 212, 0, Z)," &
"214 (BC_2, *, control, 0)," &
"215 (BC_7, MA(10), bidir, X, 214, 0, Z)," &
"216 (BC_2, *, control, 0)," &
"217 (BC_1, MODT(1), output3, X, 216, 0, Z)," &
"218 (BC_2, *, control, 0)," &
"219 (BC_1, MCKE(0), output3, X, 218, 0, Z)," &
"220 (BC_2, *, control, 0)," &
"221 (BC_1, MODT(0), output3, X, 220, 0, Z)," &
"222 (BC_2, *, control, 0)," &
"223 (BC_7, MCAS_B, bidir, X, 222, 0, Z)," &
"224 (BC_2, *, control, 0)," &
"225 (BC_1, MCK, output3, X, 224, 0, Z)," &
"226 (BC_2, *, internal, X)," &
"227 (BC_2, *, internal, X)," &
"228 (BC_2, *, control, 0)," &
"229 (BC_7, MWE_B, bidir, X, 228, 0, Z)," &
"230 (BC_2, *, control, 0)," &
"231 (BC_7, MRAS_B, bidir, X, 230, 0, Z)," &
"232 (BC_2, *, control, 0)," &
"233 (BC_7, MDQS(0), bidir, X, 232, 0, Z)," &
"234 (BC_2, *, internal, X)," &
"235 (BC_2, *, internal, X)," &
"236 (BC_2, *, control, 0)," &
"237 (BC_7, MDQ(10), bidir, X, 236, 0, Z)," &
"238 (BC_2, *, control, 0)," &
"239 (BC_7, MDQ(12), bidir, X, 238, 0, Z)," &
"240 (BC_2, *, control, 0)," &
"241 (BC_7, MDQ(6), bidir, X, 240, 0, Z)," &
"242 (BC_2, *, control, 0)," &
"243 (BC_7, MDQ(8), bidir, X, 242, 0, Z)," &
"244 (BC_2, *, control, 0)," &
"245 (BC_7, MDQ(14), bidir, X, 244, 0, Z)," &
"246 (BC_2, *, control, 0)," &
"247 (BC_7, MDQS(1), bidir, X, 246, 0, Z)," &
"248 (BC_2, *, internal, X)," &
"249 (BC_2, *, internal, X)," &
"250 (BC_2, *, control, 0)," &
"251 (BC_7, MDQ(0), bidir, X, 250, 0, Z)," &
"252 (BC_2, *, control, 0)," &
"253 (BC_7, MDQ(2), bidir, X, 252, 0, Z)," &
"254 (BC_2, *, control, 0)," &
"255 (BC_7, MDQ(4), bidir, X, 254, 0, Z)," &
"256 (BC_2, *, control, 0)," &
"257 (BC_7, MDQ(15), bidir, X, 256, 0, Z)," &
"258 (BC_2, *, control, 0)," &
"259 (BC_7, MDM(1), bidir, X, 258, 0, Z)," &
"260 (BC_2, *, control, 0)," &
"261 (BC_7, MDQ(9), bidir, X, 260, 0, Z)," &
"262 (BC_2, *, control, 0)," &
"263 (BC_7, MDQ(11), bidir, X, 262, 0, Z)," &
"264 (BC_2, *, control, 0)," &
"265 (BC_7, MDQ(7), bidir, X, 264, 0, Z)," &
"266 (BC_2, *, control, 0)," &
"267 (BC_7, MDQ(1), bidir, X, 266, 0, Z)," &
"268 (BC_2, *, control, 0)," &
"269 (BC_7, MDQ(13), bidir, X, 268, 0, Z)," &
"270 (BC_2, *, control, 0)," &
"271 (BC_7, MDM(0), bidir, X, 270, 0, Z)," &
"272 (BC_2, *, control, 0)," &
"273 (BC_7, MDQ(3), bidir, X, 272, 0, Z)," &
"274 (BC_2, *, control, 0)," &
"275 (BC_7, MDQ(5), bidir, X, 274, 0, Z)," &
"276 (BC_2, *, control, 0)," &
"277 (BC_7, MDQ(30), bidir, X, 276, 0, Z)," &
"278 (BC_2, *, control, 0)," &
"279 (BC_7, MDQ(26), bidir, X, 278, 0, Z)," &
"280 (BC_2, *, control, 0)," &
"281 (BC_7, MDQ(22), bidir, X, 280, 0, Z)," &
"282 (BC_2, *, control, 0)," &
"283 (BC_7, MDQ(24), bidir, X, 282, 0, Z)," &
"284 (BC_2, *, control, 0)," &
"285 (BC_7, MDQ(18), bidir, X, 284, 0, Z)," &
"286 (BC_2, *, control, 0)," &
"287 (BC_7, MDQ(16), bidir, X, 286, 0, Z)," &
"288 (BC_2, *, control, 0)," &
"289 (BC_7, MDQ(28), bidir, X, 288, 0, Z)," &
"290 (BC_2, *, control, 0)," &
"291 (BC_7, MDQ(20), bidir, X, 290, 0, Z)," &
"292 (BC_2, *, control, 0)," &
"293 (BC_7, MDQS(3), bidir, X, 292, 0, Z)," &
"294 (BC_2, *, internal, X)," &
"295 (BC_2, *, internal, X)," &
"296 (BC_2, *, control, 0)," &
"297 (BC_7, MDM(3), bidir, X, 296, 0, Z)," &
"298 (BC_2, *, control, 0)," &
"299 (BC_7, MDQ(31), bidir, X, 298, 0, Z)," &
"300 (BC_2, *, control, 0)," &
"301 (BC_7, MDQS(2), bidir, X, 300, 0, Z)," &
"302 (BC_2, *, internal, X)," &
"303 (BC_2, *, internal, X)," &
"304 (BC_2, *, control, 0)," &
"305 (BC_7, MDQ(23), bidir, X, 304, 0, Z)," &
"306 (BC_2, *, control, 0)," &
"307 (BC_7, MDQ(25), bidir, X, 306, 0, Z)," &
"308 (BC_2, *, control, 0)," &
"309 (BC_7, MDQ(17), bidir, X, 308, 0, Z)," &
"310 (BC_2, *, control, 0)," &
"311 (BC_7, MDM(2), bidir, X, 310, 0, Z)," &
"312 (BC_2, *, control, 0)," &
"313 (BC_7, MDQ(19), bidir, X, 312, 0, Z)," &
"314 (BC_2, *, control, 0)," &
"315 (BC_7, MDQ(21), bidir, X, 314, 0, Z)," &
"316 (BC_2, *, control, 0)," &
"317 (BC_7, MDQ(27), bidir, X, 316, 0, Z)," &
"318 (BC_2, *, control, 0)," &
"319 (BC_7, MDQ(29), bidir, X, 318, 0, Z)," &
"320 (BC_2, *, control, 0)," &
"321 (BC_7, TSEC1_GTX_CLK, bidir, X, 320, 0, Z)," &
"322 (BC_2, *, control, 0)," &
"323 (BC_7, TSEC1_TXD(1), bidir, X, 322, 0, Z)," &
"324 (BC_2, *, control, 0)," &
"325 (BC_7, EC_MDIO, bidir, X, 324, 0, Z)," &
"326 (BC_2, *, control, 0)," &
"327 (BC_7, TSEC1_RXD(2), bidir, X, 326, 0, Z)," &
"328 (BC_2, *, control, 0)," &
"329 (BC_7, TSEC1_TXD(3), bidir, X, 328, 0, Z)," &
"330 (BC_2, *, control, 0)," &
"331 (BC_7, TSEC1_GTX_CLK125, bidir, X, 330, 0, Z)," &
"332 (BC_2, *, control, 0)," &
"333 (BC_7, TSEC1_RXD(3), bidir, X, 332, 0, Z)," &
"334 (BC_2, *, control, 0)," &
"335 (BC_7, TSEC1_RXD(1), bidir, X, 334, 0, Z)," &
"336 (BC_2, *, control, 0)," &
"337 (BC_7, TSEC1_TXD(2), bidir, X, 336, 0, Z)," &
"338 (BC_2, *, control, 0)," &
"339 (BC_7, TSEC1_RX_CLK, bidir, X, 338, 0, Z)," &
"340 (BC_2, *, control, 0)," &
"341 (BC_7, TSEC1_RXD(0), bidir, X, 340, 0, Z)," &
"342 (BC_2, *, control, 0)," &
"343 (BC_7, EC_MDC, bidir, X, 342, 0, Z)," &
"344 (BC_2, *, control, 0)," &
"345 (BC_7, TSEC1_TXD(0), bidir, X, 344, 0, Z)," &
"346 (BC_2, *, control, 0)," &
"347 (BC_7, TSEC1_RX_DV, bidir, X, 346, 0, Z)," &
"348 (BC_2, *, control, 0)," &
"349 (BC_1, TSEC1_TX_EN, output3, X, 348, 0, Z)," &
"350 (BC_4, SD1_RXA_P, observe_only, X)," &
"351 (BC_2, *, control, 1)," &
"352 (BC_2, SD1_TXA_P, output3, 0, 351, 1, Z)," &
"353 (BC_2, *, control, 1)," &
"354 (BC_2, SD1_TXB_P, output3, 0, 353, 1, Z)," &
"355 (BC_4, SD1_RXB_P, observe_only, X)," &
"356 (BC_4, SD1_REF_CLK, clock, X)," &
"357 (BC_2, *, control, 1)," &
"358 (BC_2, SD1_PLL_TPD, output3, 0, 357, 1, Z)," &
"359 (BC_4, SD1_RXE_P, observe_only, X)," &
"360 (BC_2, *, control, 1)," &
"361 (BC_2, SD1_TXE_P, output3, 0, 360, 1, Z)," &
"362 (BC_2, *, control, 1)," &
"363 (BC_2, SD1_TXF_P, output3, 0, 362, 1, Z)," &
"364 (BC_4, SD1_RXF_P, observe_only, X)," &
"365 (BC_2, *, control, 0)," &
"366 (BC_7, IFC_CLK(1), bidir, X, 365, 0, Z)";
attribute DESIGN_WARNING of P1010 : entity is
"WARNING: Some of the I/O on this device support multiple supply voltages "&
"and must be configured appropriately. INCORRECT VOLTAGE SELECT SETTINGS CAN "&
"LEAD TO IRREVERSIBLE DEVICE DAMAGE. Read the comments in the header of the "&
"BSDL and refer to the Hardware Spec. "&
" "&
"WARNING: UDP/UDM pins are non-complaint with IEEE 1149.1 Standard. UDP/UDM "&
"are functionally a differential bi-directional pair but have been "&
"implemented as separate input only pins in boundary scan operations for "&
"EXTEST, CLAMP,and SAMPLE. The drivers are disabled during these "&
"instructions. If the pins can be driven during the 1149.1 test, then the "&
"interconnect can be tested. ";
end P1010;