-- Freescale Semiconductor
-- BSDL File Generated:
--
-- MCF5223x_112_LQFP.bsdl
-- ----------------
--
-- Package type: 112 pin LQFP
entity kirin2 is
generic (PHYSICAL_PIN_MAP : string := "LQFP_112");
-- KEY:
-- in = input only
-- out = three-state output or open-drain
-- buffer = two-state output
-- inout = bidirectional
-- linkage = pins not included in jtag chain
-- i.e. power, ground, clocks etc.
port ( TCLK:in bit;
TMS:in bit;
RCON_B:in bit;
TDI:in bit;
TDO:out bit;
TRST_B:in bit;
ALLPST:out bit;
TIN0:inout bit;
TIN1:inout bit;
IRQ_B8:inout bit;
IRQ_B9:inout bit;
DDATA3:inout bit;
DDATA2:inout bit;
VDDX1:linkage bit;
VSSX1:linkage bit;
DDATA1:inout bit;
DDATA0:inout bit;
JTAG_EN:in bit;
IRQ_B6:inout bit;
IRQ_B5:inout bit;
TIN2:inout bit;
TIN3:inout bit;
RTS_B1:inout bit;
CTS_B1:inout bit;
RTS_B0:inout bit;
CTS_B0:inout bit;
CANRX:inout bit;
CANTX:inout bit;
IRQ_B10:inout bit;
RXD0:inout bit;
TXD0:inout bit;
RXD1:inout bit;
TXD1:inout bit;
QSDI:inout bit;
QSDO:inout bit;
SCK:inout bit;
PCS0:inout bit;
PCS1:inout bit;
PCS2:inout bit;
PCS3:inout bit;
IRQ_B4:inout bit;
VSSX3:linkage bit;
VDDX3:linkage bit;
RSTIN_B:in bit;
VDDPLL:linkage bit;
RSTOUT_B:inout bit;
VSSPLL:linkage bit;
EXTAL:linkage bit;
XTAL:linkage bit;
TEST:in bit;
TXLED:inout bit;
RXLED:inout bit;
IRQ_B3:inout bit;
IRQ_B2:inout bit;
IRQ_B1:inout bit;
IRQ_B7:inout bit;
IRQ_B11:inout bit;
COLLED:inout bit;
DUPLED:inout bit;
RTS_B2:inout bit;
CTS_B2:inout bit;
RXD2:inout bit;
TXD2:inout bit;
VSS2:linkage bit;
VDD2:linkage bit;
EPHY_RBIAS:linkage bit;
EPHY_VSSA:linkage bit;
EPHY_VDDA:linkage bit;
EPHY_VDDTX:linkage bit;
EPHY_TXP:linkage bit;
EPHY_TXN:linkage bit;
EPHY_VSSTX:linkage bit;
EPHY_RXP:linkage bit;
EPHY_RXN:linkage bit;
EPHY_VDDRX:linkage bit;
EPHY_VSSRX:linkage bit;
PST0:inout bit;
PST1:inout bit;
PST2:inout bit;
PST3:inout bit;
SPDLED:inout bit;
EPHY_VDDX:linkage bit;
LNKLED:inout bit;
ACTLED:inout bit;
AN4:inout bit;
AN5:inout bit;
AN6:inout bit;
AN7:inout bit;
AN3:inout bit;
AN2:inout bit;
AN1:inout bit;
AN0:inout bit;
VDDAX:linkage bit;
VRH:linkage bit;
VRL:linkage bit;
VSSAX:linkage bit;
IRQ_B12:inout bit;
IRQ_B13:inout bit;
PWM1:inout bit;
PWM3:inout bit;
VSS3:linkage bit;
VDD4:linkage bit;
PWM5:inout bit;
PWM7:inout bit;
IRQ_B14:inout bit;
IRQ_B15:inout bit;
ICOC3:inout bit;
ICOC2:inout bit;
ICOC1:inout bit;
ICOC0:inout bit;
SCL:inout bit;
SDA:inout bit);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of kirin2 : entity is "STD_1149_1_2001";
attribute PIN_MAP of kirin2 : entity is PHYSICAL_PIN_MAP;
constant LQFP_112 : PIN_MAP_STRING :=
"TCLK: 1, " &
"TMS: 2, " &
"RCON_B: 3, " &
"TDI: 4, " &
"TDO: 5, " &
"TRST_B: 6, " &
"ALLPST: 7, " &
"TIN0: 8, " &
"TIN1: 9, " &
"IRQ_B8: 10, " &
"IRQ_B9: 11, " &
"DDATA3: 12, " &
"DDATA2: 13, " &
"VDDX1: 14, " &
"VSSX1: 15, " &
"DDATA1: 16, " &
"DDATA0: 17, " &
"JTAG_EN: 18, " &
"IRQ_B6: 19, " &
"IRQ_B5: 20, " &
"TIN2: 21, " &
"TIN3: 22, " &
"RTS_B1: 23, " &
"CTS_B1: 24, " &
"RTS_B0: 25, " &
"CTS_B0: 26, " &
"CANRX: 27, " &
"CANTX: 28, " &
"IRQ_B10: 29, " &
"RXD0: 30, " &
"TXD0: 31, " &
"RXD1: 32, " &
"TXD1: 33, " &
"QSDI: 34, " &
"QSDO: 35, " &
"SCK: 36, " &
"PCS0: 37, " &
"PCS1: 38, " &
"PCS2: 39, " &
"PCS3: 40, " &
"IRQ_B4: 41, " &
"VSSX3: 42, " &
"VDDX3: 43, " &
"RSTIN_B: 44, " &
"VDDPLL: 45, " &
"RSTOUT_B: 46, " &
"VSSPLL: 47, " &
"EXTAL: 48, " &
"XTAL: 49, " &
"TEST: 50, " &
"TXLED: 51, " &
"RXLED: 52, " &
"IRQ_B3: 53, " &
"IRQ_B2: 54, " &
"IRQ_B1: 55, " &
"IRQ_B7: 56, " &
"IRQ_B11: 57, " &
"COLLED: 58, " &
"DUPLED: 59, " &
"RTS_B2: 60, " &
"CTS_B2: 61, " &
"RXD2: 62, " &
"TXD2: 63, " &
"VSS2: 64, " &
"VDD2: 65, " &
"EPHY_RBIAS: 66, " &
"EPHY_VSSA: 67, " &
"EPHY_VDDA: 68, " &
"EPHY_VDDTX: 69, " &
"EPHY_TXP: 70, " &
"EPHY_TXN: 71, " &
"EPHY_VSSTX: 72, " &
"EPHY_RXP: 73, " &
"EPHY_RXN: 74, " &
"EPHY_VDDRX: 75, " &
"EPHY_VSSRX: 76, " &
"PST0: 77, " &
"PST1: 78, " &
"PST2: 79, " &
"PST3: 80, " &
"SPDLED: 81, " &
"EPHY_VDDX: 82, " &
"LNKLED: 83, " &
"ACTLED: 84, " &
"AN4: 85, " &
"AN5: 86, " &
"AN6: 87, " &
"AN7: 88, " &
"AN3: 89, " &
"AN2: 90, " &
"AN1: 91, " &
"AN0: 92, " &
"VDDAX: 93, " &
"VRH: 94, " &
"VRL: 95, " &
"VSSAX: 96, " &
"IRQ_B12: 97, " &
"IRQ_B13: 98, " &
"PWM1: 99, " &
"PWM3: 100, " &
"VSS3: 101, " &
"VDD4: 102, " &
"PWM5: 103, " &
"PWM7: 104, " &
"IRQ_B14: 105, " &
"IRQ_B15: 106, " &
"ICOC3: 107, " &
"ICOC2: 108, " &
"ICOC1: 109, " &
"ICOC0: 110, " &
"SCL: 111, " &
"SDA: 112 ";
attribute TAP_SCAN_RESET of TRST_B: signal is true;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_CLOCK of TCLK : signal is (25.0e6, BOTH);
attribute COMPLIANCE_PATTERNS of kirin2 : entity is
"(TEST, JTAG_EN) (01)";
attribute INSTRUCTION_LENGTH of kirin2 : entity is 4;
attribute INSTRUCTION_OPCODE of kirin2 : entity is
"EXTEST (0000)," &
"IDCODE (0001)," &
"SAMPLE (0010)," &
"PRELOAD (0010)," &
"TEST_LEAKAGE (0101)," &
"ENABLE_TEST_CTRL (0110)," &
"HIGHZ (1001)," &
"LOCKOUT_RECOVERY (1011)," &
"CLAMP (1100)," &
"BYPASS (1111) " ;
attribute INSTRUCTION_CAPTURE of kirin2 : entity is "0001";
attribute INSTRUCTION_PRIVATE of kirin2 : entity is "TEST_LEAKAGE, " &
"ENABLE_TEST_CTRL";
attribute REGISTER_ACCESS of kirin2 : entity is
"BYPASS (TEST_LEAKAGE)," &
"TEST_CTRL[3] (ENABLE_TEST_CTRL)," &
"JTAG_CFM_CLKDIV[7] (LOCKOUT_RECOVERY)";
attribute IDCODE_REGISTER of kirin2 : entity is
"0001" & -- version
"100000" & -- design centre
"0001001010" & -- part number
"00000001110" & -- manufacturer identity
"1"; -- 1149.1 requirement
attribute BOUNDARY_LENGTH of kirin2 : entity is 152;
-- KEY:
-- cell:
-- BC_1 = output cells and control cells
-- BC_4 = input cells
-- BC_6 = bidirectional cells
-- func:
-- output2 = two-state output
-- bidir = bidirectional
-- input = input only
-- control = control cell with no reset or .pu, .pd or .de cell
-- internal = unused cells or rtc_osc_ENB, rtc_osc_CLK, main_osc_ENB
-- or main_osc_DI cells
-- safe:
-- value which makes a control cell into an input.
-- 0/1 for control, X for all else
-- ccell:
-- number of controlling cell
-- dis:
-- value of controlling cell to make it an input (disable cell,
-- same as safe value of control cell controlling it.
-- rslt:
-- result when disabled - Weak1 for open drains, DTACKB and RXD1,
-- Z for all else. (All other pull-ups or pull-downs are
-- programmable, controlled by .pu or .pd cells.)
attribute BOUNDARY_REGISTER of kirin2 : entity is
-- num cell port func safe [ccell dis rslt]
"0 (BC_4, RCON_B, input, X)," &
"1 (BC_2, *, control, 0)," & -- ALLPST.ctl
"2 (BC_2, ALLPST, output3, X, 1, 0, Z)," &
"3 (BC_2, *, control, 0)," & -- TIN0.ctl
"4 (BC_7, TIN0, bidir, X, 3, 0, Z)," &
"5 (BC_2, *, control, 0)," & -- TIN1.ctl
"6 (BC_7, TIN1, bidir, X, 5, 0, Z)," &
"7 (BC_2, *, control, 0)," & -- IRQ_B8.ctl
"8 (BC_7, IRQ_B8, bidir, X, 7, 0, Z)," &
"9 (BC_2, *, control, 0)," & -- IRQ_B9.ctl
"10 (BC_7, IRQ_B9, bidir, X, 9, 0, Z)," &
"11 (BC_2, *, control, 0)," & -- DDATA3.ctl
"12 (BC_7, DDATA3, bidir, X, 11, 0, Z)," &
"13 (BC_2, *, control, 0)," & -- DDATA2.ctl
"14 (BC_7, DDATA2, bidir, X, 13, 0, Z)," &
"15 (BC_2, *, control, 0)," & -- DDATA1.ctl
"16 (BC_7, DDATA1, bidir, X, 15, 0, Z)," &
"17 (BC_2, *, control, 0)," & -- DDATA0.ctl
"18 (BC_7, DDATA0, bidir, X, 17, 0, Z)," &
"19 (BC_2, *, control, 0)," & -- IRQ_B6.ctl
"20 (BC_7, IRQ_B6, bidir, X, 19, 0, Z)," &
"21 (BC_2, *, control, 0)," & -- IRQ_B5.ctl
"22 (BC_7, IRQ_B5, bidir, X, 21, 0, Z)," &
"23 (BC_2, *, control, 0)," & -- TIN2.ctl
"24 (BC_7, TIN2, bidir, X, 23, 0, Z)," &
"25 (BC_2, *, control, 0)," & -- TIN3.ctl
"26 (BC_7, TIN3, bidir, X, 25, 0, Z)," &
"27 (BC_2, *, control, 0)," & -- RTS_B1.ctl
"28 (BC_7, RTS_B1, bidir, X, 27, 0, Z)," &
"29 (BC_2, *, control, 0)," & -- CTS_B1.ctl
"30 (BC_7, CTS_B1, bidir, X, 29, 0, Z)," &
"31 (BC_2, *, control, 0)," & -- RTS_B0.ctl
"32 (BC_7, RTS_B0, bidir, X, 31, 0, Z)," &
"33 (BC_2, *, control, 0)," & -- CTS_B0.ctl
"34 (BC_7, CTS_B0, bidir, X, 33, 0, Z)," &
"35 (BC_2, *, control, 0)," & -- CANRX.ctl
"36 (BC_7, CANRX, bidir, X, 35, 0, Z)," &
"37 (BC_2, *, control, 0)," & -- CANTX.ctl
"38 (BC_7, CANTX, bidir, X, 37, 0, Z)," &
"39 (BC_2, *, control, 0)," & -- IRQ_B10.ctl
"40 (BC_7, IRQ_B10, bidir, X, 39, 0, Z)," &
"41 (BC_2, *, control, 0)," & -- RXD0.ctl
"42 (BC_7, RXD0, bidir, X, 41, 0, Z)," &
"43 (BC_2, *, control, 0)," & -- TXD0.ctl
"44 (BC_7, TXD0, bidir, X, 43, 0, Z)," &
"45 (BC_2, *, control, 0)," & -- RXD1.ctl
"46 (BC_7, RXD1, bidir, X, 45, 0, Z)," &
"47 (BC_2, *, control, 0)," & -- TXD1.ctl
"48 (BC_7, TXD1, bidir, X, 47, 0, Z)," &
"49 (BC_2, *, control, 0)," & -- QSDI.ctl
"50 (BC_7, QSDI, bidir, X, 49, 0, Z)," &
"51 (BC_2, *, control, 0)," & -- QSDO.ctl
"52 (BC_7, QSDO, bidir, X, 51, 0, Z)," &
"53 (BC_2, *, control, 0)," & -- SCK.ctl
"54 (BC_7, SCK, bidir, X, 53, 0, Z)," &
"55 (BC_2, *, control, 0)," & -- PCS0.ctl
"56 (BC_7, PCS0, bidir, X, 55, 0, Z)," &
"57 (BC_2, *, control, 0)," & -- PCS1.ctl
"58 (BC_7, PCS1, bidir, X, 57, 0, Z)," &
"59 (BC_2, *, control, 0)," & -- PCS2.ctl
"60 (BC_7, PCS2, bidir, X, 59, 0, Z)," &
"61 (BC_2, *, control, 0)," & -- PCS3.ctl
"62 (BC_7, PCS3, bidir, X, 61, 0, Z)," &
"63 (BC_2, *, control, 0)," & -- IRQ_B4.ctl
"64 (BC_7, IRQ_B4, bidir, X, 63, 0, Z)," &
"65 (BC_4, RSTIN_B, input, X)," &
"66 (BC_2, *, control, 0)," & -- RSTOUT_B.ctl
"67 (BC_7, RSTOUT_B, bidir, X, 66, 0, Z)," &
"68 (BC_2, *, control, 0)," & -- TXLED.ctl
"69 (BC_7, TXLED, bidir, X, 68, 0, Z)," &
"70 (BC_2, *, control, 0)," & -- RXLED.ctl
"71 (BC_7, RXLED, bidir, X, 70, 0, Z)," &
"72 (BC_2, *, control, 0)," & -- IRQ_B3.ctl
"73 (BC_7, IRQ_B3, bidir, X, 72, 0, Z)," &
"74 (BC_2, *, control, 0)," & -- IRQ_B2.ctl
"75 (BC_7, IRQ_B2, bidir, X, 74, 0, Z)," &
"76 (BC_2, *, control, 0)," & -- IRQ_B1.ctl
"77 (BC_7, IRQ_B1, bidir, X, 76, 0, Z)," &
"78 (BC_2, *, control, 0)," & -- IRQ_B7.ctl
"79 (BC_7, IRQ_B7, bidir, X, 78, 0, Z)," &
"80 (BC_2, *, control, 0)," & -- IRQ_B11.ctl
"81 (BC_7, IRQ_B11, bidir, X, 80, 0, Z)," &
"82 (BC_2, *, control, 0)," & -- COLLED.ctl
"83 (BC_7, COLLED, bidir, X, 82, 0, Z)," &
"84 (BC_2, *, control, 0)," & -- DUPLED.ctl
"85 (BC_7, DUPLED, bidir, X, 84, 0, Z)," &
"86 (BC_2, *, control, 0)," & -- RTS_B2.ctl
"87 (BC_7, RTS_B2, bidir, X, 86, 0, Z)," &
"88 (BC_2, *, control, 0)," & -- CTS_B2.ctl
"89 (BC_7, CTS_B2, bidir, X, 88, 0, Z)," &
"90 (BC_2, *, control, 0)," & -- RXD2.ctl
"91 (BC_7, RXD2, bidir, X, 90, 0, Z)," &
"92 (BC_2, *, control, 0)," & -- TXD2.ctl
"93 (BC_7, TXD2, bidir, X, 92, 0, Z)," &
"94 (BC_2, *, control, 0)," & -- PST0.ctl
"95 (BC_7, PST0, bidir, X, 94, 0, Z)," &
"96 (BC_2, *, control, 0)," & -- PST1.ctl
"97 (BC_7, PST1, bidir, X, 96, 0, Z)," &
"98 (BC_2, *, control, 0)," & -- PST2.ctl
"99 (BC_7, PST2, bidir, X, 98, 0, Z)," &
"100 (BC_2, *, control, 0)," & -- PST3.ctl
"101 (BC_7, PST3, bidir, X, 100, 0, Z)," &
"102 (BC_2, *, control, 0)," & -- SPDLED.ctl
"103 (BC_7, SPDLED, bidir, X, 102, 0, Z)," &
"104 (BC_2, *, control, 0)," & -- LNKLED.ctl
"105 (BC_7, LNKLED, bidir, X, 104, 0, Z)," &
"106 (BC_2, *, control, 0)," & -- ACTLED.ctl
"107 (BC_7, ACTLED, bidir, X, 106, 0, Z)," &
"108 (BC_2, *, control, 0)," & -- AN4.ctl
"109 (BC_7, AN4, bidir, X, 108, 0, Z)," &
"110 (BC_2, *, control, 0)," & -- AN5.ctl
"111 (BC_7, AN5, bidir, X, 110, 0, Z)," &
"112 (BC_2, *, control, 0)," & -- AN6.ctl
"113 (BC_7, AN6, bidir, X, 112, 0, Z)," &
"114 (BC_2, *, control, 0)," & -- AN7.ctl
"115 (BC_7, AN7, bidir, X, 114, 0, Z)," &
"116 (BC_2, *, control, 0)," & -- AN3.ctl
"117 (BC_7, AN3, bidir, X, 116, 0, Z)," &
"118 (BC_2, *, control, 0)," & -- AN2.ctl
"119 (BC_7, AN2, bidir, X, 118, 0, Z)," &
"120 (BC_2, *, control, 0)," & -- AN1.ctl
"121 (BC_7, AN1, bidir, X, 120, 0, Z)," &
"122 (BC_2, *, control, 0)," & -- AN0.ctl
"123 (BC_7, AN0, bidir, X, 122, 0, Z)," &
"124 (BC_2, *, control, 0)," & -- IRQ_B12.ctl
"125 (BC_7, IRQ_B12, bidir, X, 124, 0, Z)," &
"126 (BC_2, *, control, 0)," & -- IRQ_B13.ctl
"127 (BC_7, IRQ_B13, bidir, X, 126, 0, Z)," &
"128 (BC_2, *, control, 0)," & -- PWM1.ctl
"129 (BC_7, PWM1, bidir, X, 128, 0, Z)," &
"130 (BC_2, *, control, 0)," & -- PWM3.ctl
"131 (BC_7, PWM3, bidir, X, 130, 0, Z)," &
"132 (BC_2, *, control, 0)," & -- PWM5.ctl
"133 (BC_7, PWM5, bidir, X, 132, 0, Z)," &
"134 (BC_2, *, control, 0)," & -- PWM7.ctl
"135 (BC_7, PWM7, bidir, X, 134, 0, Z)," &
"136 (BC_2, *, control, 0)," & -- IRQ_B14.ctl
"137 (BC_7, IRQ_B14, bidir, X, 136, 0, Z)," &
"138 (BC_2, *, control, 0)," & -- IRQ_B15.ctl
"139 (BC_7, IRQ_B15, bidir, X, 138, 0, Z)," &
"140 (BC_2, *, control, 0)," & -- ICOC3.ctl
"141 (BC_7, ICOC3, bidir, X, 140, 0, Z)," &
"142 (BC_2, *, control, 0)," & -- ICOC2.ctl
"143 (BC_7, ICOC2, bidir, X, 142, 0, Z)," &
"144 (BC_2, *, control, 0)," & -- ICOC1.ctl
"145 (BC_7, ICOC1, bidir, X, 144, 0, Z)," &
"146 (BC_2, *, control, 0)," & -- ICOC0.ctl
"147 (BC_7, ICOC0, bidir, X, 146, 0, Z)," &
"148 (BC_2, *, control, 0)," & -- SCL.ctl
"149 (BC_7, SCL, bidir, X, 148, 0, Z)," &
"150 (BC_2, *, control, 0)," & -- SDA.ctl
"151 (BC_7, SDA, bidir, X, 150, 0, Z)";
end kirin2;