-- ======================================================================
-- Copyright 2019, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or implied,
-- with regard to this material, including, but not limited to, the
-- implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- ======================================================================
--
-- File Name: PSoC_6_512K_WLCSP_49.bsdl
--
-- BSDL Version 2001
--
-- Revision: 1.0 -- New BSDL model
--
-- Last Updated: May 24, 2019
--
-- Part #: CY8C6245FNI-Dxx
--
-- Package: 49 Pin WLCSP
-- ======================================================================
entity CY8C6245FNI_Dxx is
generic (PHYSICAL_PIN_MAP : string := "WLCSP49");
port (
-- Port List
VCCD : linkage bit;
VDDD : linkage bit;
P0_0 : inout bit;
P0_1 : in bit;
XRES : linkage bit;
VDD_NS : linkage bit;
VIND : linkage bit;
P2_0 : inout bit;
P2_1 : inout bit;
P2_2 : inout bit;
P2_3 : inout bit;
P2_4 : inout bit;
P2_5 : inout bit;
VDDIO_2 : linkage bit;
P5_0 : inout bit;
P5_1 : inout bit;
P6_2 : inout bit;
P6_3 : inout bit;
P6_4 : out bit;
P6_5 : in bit;
P6_6 : in bit;
P6_7 : in bit;
VDDIO_1 : linkage bit;
VDDA : linkage bit;
P7_0 : inout bit;
P7_1 : inout bit;
P7_2 : inout bit;
P7_3 : inout bit;
P7_4 : inout bit;
P9_0 : inout bit;
P9_1 : inout bit;
P9_2 : inout bit;
P9_3 : inout bit;
VREF : linkage bit;
P10_0 : inout bit;
P10_1 : inout bit;
P10_2 : inout bit;
P10_3 : inout bit;
P10_4 : inout bit;
P10_5 : inout bit;
P11_2 : inout bit;
P11_3 : inout bit;
P11_4 : inout bit;
P11_5 : inout bit;
P11_6 : inout bit;
P11_7 : inout bit;
VDDIO_0 : linkage bit;
VSS : linkage bit_vector(0 to 1));
use STD_1149_1_2001.all;
use TS_BSCAN_CELLS.all;
attribute COMPONENT_CONFORMANCE of CY8C6245FNI_Dxx: entity is "STD_1149_1_2001";
--Pin mappings
attribute PIN_MAP of CY8C6245FNI_Dxx: entity is PHYSICAL_PIN_MAP;
constant WLCSP49: PIN_MAP_STRING :=
"VCCD : A11 , " &
"VDDD : C11 , " &
"P0_0 : E9 , " &
"P0_1 : D10 , " &
"XRES : E11 , " &
"VDD_NS : F10 , " &
"VIND : G11 , " &
"P2_0 : H10 , " &
"P2_1 : F8 , " &
"P2_2 : H8 , " &
"P2_3 : G9 , " &
"P2_4 : J11 , " &
"P2_5 : J9 , " &
"VDDIO_2 : J7 , " &
"P5_0 : J5 , " &
"P5_1 : G7 , " &
"P6_2 : J3 , " &
"P6_3 : H4 , " &
"P6_4 : G5 , " &
"P6_5 : J1 , " &
"P6_6 : H2 , " &
"P6_7 : G3 , " &
"VDDIO_1 : G1 , " &
"VDDA : B2 , " &
"P7_0 : F6 , " &
"P7_1 : F4 , " &
"P7_2 : F2 , " &
"P7_3 : E3 , " &
"P7_4 : E1 , " &
"P9_0 : D2 , " &
"P9_1 : E5 , " &
"P9_2 : E7 , " &
"P9_3 : C1 , " &
"VREF : C3 , " &
"P10_0 : D4 , " &
"P10_1 : A5 , " &
"P10_2 : B4 , " &
"P10_3 : A3 , " &
"P10_4 : C5 , " &
"P10_5 : D6 , " &
"P11_2 : C7 , " &
"P11_3 : A7 , " &
"P11_4 : D8 , " &
"P11_5 : B8 , " &
"P11_6 : C9 , " &
"P11_7 : B10 , " &
"VDDIO_0 : A9 , " &
"VSS : (B6, H6) ";
attribute TAP_SCAN_RESET of P0_1 : signal is true;
attribute TAP_SCAN_IN of P6_5 : signal is true;
attribute TAP_SCAN_MODE of P6_6 : signal is true;
attribute TAP_SCAN_OUT of P6_4 : signal is true;
attribute TAP_SCAN_CLOCK of P6_7 : signal is (1.0000000000000000000e+07, BOTH);
attribute INSTRUCTION_LENGTH of CY8C6245FNI_Dxx: entity is 4;
attribute INSTRUCTION_OPCODE of CY8C6245FNI_Dxx: entity is
"IDCODE (1100)," &
"BYPASS (1111)," &
"EXTEST (0001)," &
"EXTEST_PULSE (0010)," &
"EXTEST_TRAIN (0011)," &
"SAMPLE (0101)," &
"PRELOAD (0101)," &
"HIGHZ (0110)," &
"CLAMP (0000) " ;
attribute INSTRUCTION_CAPTURE of CY8C6245FNI_Dxx: entity is "0001";
attribute IDCODE_REGISTER of CY8C6245FNI_Dxx: entity is
"0001" & -- version
"1110011100000000" & -- part number
"00000110100" & -- manufacturer's identity
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of CY8C6245FNI_Dxx: entity is
"DEVICE_ID ( IDCODE )," &
"BOUNDARY ( SAMPLE, PRELOAD, EXTEST, EXTEST_PULSE, EXTEST_TRAIN )," &
"BYPASS ( HIGHZ, CLAMP, BYPASS ) " ;
--Boundary scan definition
attribute BOUNDARY_LENGTH of CY8C6245FNI_Dxx: entity is 122;
attribute BOUNDARY_REGISTER of CY8C6245FNI_Dxx: entity is
-- num cell port function safe [ccell disval rslt]
" 121 (BC_2 , * , control , 0 ) ,"&
" 120 (TS_BC_7 , P0_0 , bidir , X , 121 , 0 , Z ),"&
" 119 (BC_0 , * , internal , 0 ) ,"&
" 118 (BC_0 , * , internal , X ) ,"&
" 117 (BC_0 , * , internal , 0 ) ,"&
" 116 (BC_0 , * , internal , X ) ,"&
" 115 (BC_0 , * , internal , 0 ) ,"&
" 114 (BC_0 , * , internal , X ) ,"&
" 113 (BC_0 , * , internal , 0 ) ,"&
" 112 (BC_0 , * , internal , X ) ,"&
" 111 (BC_0 , * , internal , 0 ) ,"&
" 110 (BC_0 , * , internal , X ) ,"&
" 109 (BC_0 , * , internal , 0 ) ,"&
" 108 (BC_0 , * , internal , X ) ,"&
" 107 (BC_2 , * , control , 0 ) ,"&
" 106 (TS_BC_7 , P2_0 , bidir , X , 107 , 0 , Z ),"&
" 105 (BC_2 , * , control , 0 ) ,"&
" 104 (TS_BC_7 , P2_1 , bidir , X , 105 , 0 , Z ),"&
" 103 (BC_2 , * , control , 0 ) ,"&
" 102 (TS_BC_7 , P2_2 , bidir , X , 103 , 0 , Z ),"&
" 101 (BC_2 , * , control , 0 ) ,"&
" 100 (TS_BC_7 , P2_3 , bidir , X , 101 , 0 , Z ),"&
" 99 (BC_2 , * , control , 0 ) ,"&
" 98 (TS_BC_7 , P2_4 , bidir , X , 99 , 0 , Z ),"&
" 97 (BC_2 , * , control , 0 ) ,"&
" 96 (TS_BC_7 , P2_5 , bidir , X , 97 , 0 , Z ),"&
" 95 (BC_0 , * , internal , 0 ) ,"&
" 94 (BC_0 , * , internal , X ) ,"&
" 93 (BC_0 , * , internal , 0 ) ,"&
" 92 (BC_0 , * , internal , X ) ,"&
" 91 (BC_0 , * , internal , 0 ) ,"&
" 90 (BC_0 , * , internal , X ) ,"&
" 89 (BC_0 , * , internal , 0 ) ,"&
" 88 (BC_0 , * , internal , X ) ,"&
" 87 (BC_2 , * , control , 0 ) ,"&
" 86 (TS_BC_7 , P5_0 , bidir , X , 87 , 0 , Z ),"&
" 85 (BC_2 , * , control , 0 ) ,"&
" 84 (TS_BC_7 , P5_1 , bidir , X , 85 , 0 , Z ),"&
" 83 (BC_0 , * , internal , 0 ) ,"&
" 82 (BC_0 , * , internal , X ) ,"&
" 81 (BC_0 , * , internal , 0 ) ,"&
" 80 (BC_0 , * , internal , X ) ,"&
" 79 (BC_0 , * , internal , 0 ) ,"&
" 78 (BC_0 , * , internal , X ) ,"&
" 77 (BC_0 , * , internal , 0 ) ,"&
" 76 (BC_0 , * , internal , X ) ,"&
" 75 (BC_2 , * , control , 0 ) ,"&
" 74 (TS_BC_7 , P6_2 , bidir , X , 75 , 0 , Z ),"&
" 73 (BC_2 , * , control , 0 ) ,"&
" 72 (TS_BC_7 , P6_3 , bidir , X , 73 , 0 , Z ),"&
" 71 (BC_2 , * , control , 0 ) ,"&
" 70 (TS_BC_7 , P7_0 , bidir , X , 71 , 0 , Z ),"&
" 69 (BC_2 , * , control , 0 ) ,"&
" 68 (TS_BC_7 , P7_1 , bidir , X , 69 , 0 , Z ),"&
" 67 (BC_2 , * , control , 0 ) ,"&
" 66 (TS_BC_7 , P7_2 , bidir , X , 67 , 0 , Z ),"&
" 65 (BC_2 , * , control , 0 ) ,"&
" 64 (TS_BC_7 , P7_3 , bidir , X , 65 , 0 , Z ),"&
" 63 (BC_2 , * , control , 0 ) ,"&
" 62 (TS_BC_7 , P7_4 , bidir , X , 63 , 0 , Z ),"&
" 61 (BC_0 , * , internal , 0 ) ,"&
" 60 (BC_0 , * , internal , X ) ,"&
" 59 (BC_0 , * , internal , 0 ) ,"&
" 58 (BC_0 , * , internal , X ) ,"&
" 57 (BC_0 , * , internal , 0 ) ,"&
" 56 (BC_0 , * , internal , X ) ,"&
" 55 (BC_0 , * , internal , 0 ) ,"&
" 54 (BC_0 , * , internal , X ) ,"&
" 53 (BC_0 , * , internal , 0 ) ,"&
" 52 (BC_0 , * , internal , X ) ,"&
" 51 (BC_0 , * , internal , 0 ) ,"&
" 50 (BC_0 , * , internal , X ) ,"&
" 49 (BC_0 , * , internal , 0 ) ,"&
" 48 (BC_0 , * , internal , X ) ,"&
" 47 (BC_2 , * , control , 0 ) ,"&
" 46 (TS_BC_7 , P9_0 , bidir , X , 47 , 0 , Z ),"&
" 45 (BC_2 , * , control , 0 ) ,"&
" 44 (TS_BC_7 , P9_1 , bidir , X , 45 , 0 , Z ),"&
" 43 (BC_2 , * , control , 0 ) ,"&
" 42 (TS_BC_7 , P9_2 , bidir , X , 43 , 0 , Z ),"&
" 41 (BC_2 , * , control , 0 ) ,"&
" 40 (TS_BC_7 , P9_3 , bidir , X , 41 , 0 , Z ),"&
" 39 (BC_2 , * , control , 0 ) ,"&
" 38 (TS_BC_7 , P10_0 , bidir , X , 39 , 0 , Z ),"&
" 37 (BC_2 , * , control , 0 ) ,"&
" 36 (TS_BC_7 , P10_1 , bidir , X , 37 , 0 , Z ),"&
" 35 (BC_2 , * , control , 0 ) ,"&
" 34 (TS_BC_7 , P10_2 , bidir , X , 35 , 0 , Z ),"&
" 33 (BC_2 , * , control , 0 ) ,"&
" 32 (TS_BC_7 , P10_3 , bidir , X , 33 , 0 , Z ),"&
" 31 (BC_2 , * , control , 0 ) ,"&
" 30 (TS_BC_7 , P10_4 , bidir , X , 31 , 0 , Z ),"&
" 29 (BC_2 , * , control , 0 ) ,"&
" 28 (TS_BC_7 , P10_5 , bidir , X , 29 , 0 , Z ),"&
" 27 (BC_0 , * , internal , 0 ) ,"&
" 26 (BC_0 , * , internal , X ) ,"&
" 25 (BC_0 , * , internal , 0 ) ,"&
" 24 (BC_0 , * , internal , X ) ,"&
" 23 (BC_0 , * , internal , 0 ) ,"&
" 22 (BC_0 , * , internal , X ) ,"&
" 21 (BC_0 , * , internal , 0 ) ,"&
" 20 (BC_0 , * , internal , X ) ,"&
" 19 (BC_2 , * , control , 0 ) ,"&
" 18 (TS_BC_7 , P11_2 , bidir , X , 19 , 0 , Z ),"&
" 17 (BC_2 , * , control , 0 ) ,"&
" 16 (TS_BC_7 , P11_3 , bidir , X , 17 , 0 , Z ),"&
" 15 (BC_2 , * , control , 0 ) ,"&
" 14 (TS_BC_7 , P11_4 , bidir , X , 15 , 0 , Z ),"&
" 13 (BC_2 , * , control , 0 ) ,"&
" 12 (TS_BC_7 , P11_5 , bidir , X , 13 , 0 , Z ),"&
" 11 (BC_2 , * , control , 0 ) ,"&
" 10 (TS_BC_7 , P11_6 , bidir , X , 11 , 0 , Z ),"&
" 9 (BC_2 , * , control , 0 ) ,"&
" 8 (TS_BC_7 , P11_7 , bidir , X , 9 , 0 , Z ),"&
" 7 (BC_0 , * , internal , 0 ) ,"&
" 6 (BC_0 , * , internal , X ) ,"&
" 5 (BC_0 , * , internal , 0 ) ,"&
" 4 (BC_0 , * , internal , X ) ,"&
" 3 (BC_0 , * , internal , 0 ) ,"&
" 2 (BC_0 , * , internal , X ) ,"&
" 1 (BC_0 , * , internal , 0 ) ,"&
" 0 (BC_0 , * , internal , X ) ";
end CY8C6245FNI_Dxx;