-- ***************************************************************
-- Company: Integrated Device Technology, Inc.
--
-- Part : CM8A34003P
--
-- Title: BSDL file of CM8A34003P
-- Generated by : AS
--
-- Release status: formal issue
-- Security level: client use
-- BSDL Version 2001
-- Revision History:
-- Jan 15, 2019: initial release - QFN48
-- Jun 13, 2018: ID[4:0] == [nc,nc,nc,nc,nc] == variant31 == 0x64F
--
-- Generated by boundaryScanGenerate 2015.2-p1 Mon Jun 29 23:40:43 GMT 2015 on 09/10/16 18:53:05
-- BSDL Version 2001
entity CM8A34003P is
generic (PHYSICAL_PIN_MAP : string := "QFN_48");
port (
-- Port List
OSCI : linkage bit;
OSCO : linkage bit;
XO_DPLL : linkage bit;
nMR0 : in bit;
SCL_M : inout bit;
SDA_M : inout bit;
SCLK_AUX : inout bit;
SDIO_AUX : inout bit;
SDI_A1_AUX : inout bit;
CS_A0_AUX : inout bit;
nTEST : in bit;
CLK0 : linkage bit;
CLK1 : linkage bit;
nCLK0 : linkage bit;
nCLK1 : linkage bit;
Q9 : linkage bit;
Q8 : linkage bit;
Q10 : linkage bit;
Q11 : linkage bit;
nQ8 : linkage bit;
nQ9 : linkage bit;
nQ10 : linkage bit;
nQ11 : linkage bit;
GPIO_DC0 : in bit;
GPIO_DC1 : in bit;
GPIO_DC2 : in bit;
GPIO_DC3 : out bit;
GPIO_DC4 : in bit;
GPIO_DC5 : inout bit;
GPIO_DC8 : inout bit;
GPIO_DC9 : inout bit;
FILTER_PAD : linkage bit;
VDD_CLK0 : linkage bit;
VDDA_BANDGAP : linkage bit;
VDDA_FBDIV : linkage bit;
VDDA_LC : linkage bit;
VDD_GPIO_DC : linkage bit;
VDDD : linkage bit;
VDD_FOD_Q10 : linkage bit;
VDDO_Q8 : linkage bit;
VDDO_Q9 : linkage bit;
VDDO_Q10 : linkage bit;
VDDO_Q11 : linkage bit;
VREG_XTAL : linkage bit);
use STD_1149_1_2001.all;
use LVS_BSCAN_CELLS.all;
attribute COMPONENT_CONFORMANCE of CM8A34003P: entity is "STD_1149_1_2001";
--Pin mappings
attribute PIN_MAP of CM8A34003P: entity is PHYSICAL_PIN_MAP;
constant QFN_48: PIN_MAP_STRING :=
"OSCI : 45 , " &
"OSCO : 44 , " &
"XO_DPLL : 1 , " &
"nMR0 : 17 , " &
"SCL_M : 8 , " &
"SDA_M : 7 , " &
"SCLK_AUX : 12 , " &
"SDIO_AUX : 11 , " &
"SDI_A1_AUX : 10 , " &
"CS_A0_AUX : 9 , " &
"nTEST : 18 , " &
"CLK0 : 2 , " &
"CLK1 : 4 , " &
"nCLK0 : 3 , " &
"nCLK1 : 5 , " &
"Q8 : 40 , " &
"Q9 : 34 , " &
"Q10 : 27 , " &
"Q11 : 21 , " &
"nQ8 : 41 , " &
"nQ9 : 33 , " &
"nQ10 : 28 , " &
"nQ11 : 20 , " &
"GPIO_DC0 : 42 , " &
"GPIO_DC1 : 32 , " &
"GPIO_DC2 : 29 , " &
"GPIO_DC3 : 19 , " &
"GPIO_DC4 : 37 , " &
"GPIO_DC5 : 36 , " &
"GPIO_DC8 : 25 , " &
"GPIO_DC9 : 24 , " &
"FILTER_PAD : 14 , " &
"VDD_CLK0 : 48 , " &
"VDDA_BANDGAP : 16 , " &
"VDDA_FBDIV : 47 , " &
"VDDA_LC : 15 , " &
"VDD_GPIO_DC : 13 , " &
"VDDD : 6 , " &
"VDD_FOD_Q10 : 30 , " &
"VDDO_Q8 : 39 , " &
"VDDO_Q9 : 35 , " &
"VDDO_Q10 : 26 , " &
"VDDO_Q11 : 22 , " &
"VREG_XTAL : 43 " ;
attribute TAP_SCAN_RESET of GPIO_DC4 : signal is true;
attribute TAP_SCAN_IN of GPIO_DC2 : signal is true;
attribute TAP_SCAN_MODE of GPIO_DC1 : signal is true;
attribute TAP_SCAN_OUT of GPIO_DC3 : signal is true;
attribute TAP_SCAN_CLOCK of GPIO_DC0 : signal is (1.0000000000000000000e+07, BOTH);
attribute COMPLIANCE_PATTERNS of CM8A34003P : entity is
"(nTEST) (0)";
attribute INSTRUCTION_LENGTH of CM8A34003P: entity is 18;
attribute INSTRUCTION_OPCODE of CM8A34003P: entity is
"IDCODE (111111111111111110)," &
"BYPASS (111111111111111111)," &
"EXTEST (111111111111101000)," &
"SAMPLE (111111111111111000)," &
"PRELOAD (111111111111111000)," &
"HIGHZ (111111111111001111)," &
"CLAMP (111111111111101111) " ;
attribute INSTRUCTION_CAPTURE of CM8A34003P: entity is "xxxxxxxxxxxxxxxx01";
attribute IDCODE_REGISTER of CM8A34003P: entity is
"0001" & -- version
"0000011001001100" & -- part number
"00000110011" & -- manufacturer's identity
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of CM8A34003P: entity is
"DEVICE_ID ( IDCODE ), " &
"BOUNDARY ( SAMPLE, PRELOAD, EXTEST )," &
"BYPASS ( HIGHZ, CLAMP, BYPASS ) " ;
--Boundary scan definition
attribute BOUNDARY_LENGTH of CM8A34003P: entity is 43;
attribute BOUNDARY_REGISTER of CM8A34003P: entity is
-- num cell port function safe [ccell disval rslt]
" 42 (BC_4 , nMR0 , observe_only , X ) ,"&
" 41 (BC_2 , * , control , 1 ) ,"&
" 40 (LV_BC_7 , SCL_M , bidir , X , 41 , 1 , Z ),"&
" 39 (BC_2 , * , control , 1 ) ,"&
" 38 (LV_BC_7 , SDA_M , bidir , X , 39 , 1 , Z ),"&
" 37 (BC_2 , * , control , 1 ) ,"&
" 36 (LV_BC_7 , SCLK_AUX , bidir , X , 37 , 1 , Z ),"&
" 35 (BC_2 , * , control , 1 ) ,"&
" 34 (LV_BC_7 , SDIO_AUX , bidir , X , 35 , 1 , Z ),"&
" 33 (BC_2 , * , control , 1 ) ,"&
" 32 (LV_BC_7 , SDI_A1_AUX , bidir , X , 33 , 1 , Z ),"&
" 31 (BC_2 , * , control , 1 ) ,"&
" 30 (LV_BC_7 , CS_A0_AUX , bidir , X , 31 , 1 , Z ),"&
" 29 (BC_0 , * , internal , 0 ) ,"&
" 28 (BC_0 , * , internal , 0 ),"&
" 27 (BC_0 , * , internal , 0 ) ,"&
" 26 (BC_0 , * , internal , 0 ),"&
" 25 (BC_0 , * , internal , 0 ) ,"&
" 24 (BC_0 , * , internal , 0 ),"&
" 23 (BC_0 , * , internal , 0 ) ,"&
" 22 (BC_0 , * , internal , 0 ),"&
" 21 (BC_2 , * , control , 1 ) ,"&
" 20 (LV_BC_7 , GPIO_DC5 , bidir , X , 21 , 1 , Z ),"&
" 19 (BC_0 , * , internal , 0 ) ,"&
" 18 (BC_0 , * , internal , 0 ),"&
" 17 (BC_0 , * , internal , 0 ) ,"&
" 16 (BC_0 , * , internal , 0 ),"&
" 15 (BC_2 , * , control , 1 ) ,"&
" 14 (LV_BC_7 , GPIO_DC8 , bidir , X , 15 , 1 , Z ),"&
" 13 (BC_2 , * , control , 1 ) ,"&
" 12 (LV_BC_7 , GPIO_DC9 , bidir , X , 13 , 1 , Z ),"&
" 11 (BC_0 , * , internal , 0 ) ,"&
" 10 (BC_0 , * , internal , 0 ),"&
" 9 (BC_0 , * , internal , 0 ) ,"&
" 8 (BC_0 , * , internal , 0 ),"&
" 7 (BC_0 , * , internal , 0 ) ,"&
" 6 (BC_0 , * , internal , 0 ),"&
" 5 (BC_0 , * , internal , 0 ) ,"&
" 4 (BC_0 , * , internal , 0 ),"&
" 3 (BC_0 , * , internal , 0 ) ,"&
" 2 (BC_0 , * , internal , 0 ),"&
" 1 (BC_0 , * , internal , 0 ) ,"&
" 0 (BC_0 , * , internal , 0 ) ";
end CM8A34003P;
-- VHDL package to be uploaded
--package LVS_BSCAN_CELLS is
-- use STD_1149_1_2001.all;
-- constant LV_BC_7: CELL_INFO;
--
--end LVS_BSCAN_CELLS;
--package body LVS_BSCAN_CELLS is
-- use STD_1149_1_2001.all;
-- constant LV_BC_7: CELL_INFO :=
-- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PO),
-- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
-- (BIDIR_IN, INTEST, X), (BIDIR_OUT, INTEST, PI));
--
--end LVS_BSCAN_CELLS;
--