-------------------------------------------------------------------------------
-- File Type: BSDL description for top level entity TMS320C6711 for pg2.1
-- $Id: TMS320C6711.bsm,v 1.2 2001/09/11 15:07:02 $
-- External Release version $Revision: 1.2 $
-------------------------------------------------------------------------------
entity TMS320C6711 is
generic(PHYSICAL_PIN_MAP : string := "GFN");
PORT (
ARDY : in BIT ;
BE_Z : out BIT_VECTOR( 0 to 3 );
BUSREQ : out BIT ;
CE_Z : out BIT_VECTOR( 0 to 3 );
CLKIN : in BIT ;
CLKOUT2 : out BIT ;
CLKR0 : inout BIT ;
CLKR1 : inout BIT ;
CLKS0 : in BIT ;
CLKS1 : in BIT ;
CLKX0 : inout BIT ;
CLKX1 : inout BIT ;
CLKMODE0 : in BIT ;
DR0 : in BIT ;
DR1 : in BIT ;
DX0 : out BIT ;
DX1 : out BIT ;
EA : out BIT_VECTOR( 0 to 19 ); -- note datasheet lists as EA(2:21) shift by 2
ECLKIN : in BIT ;
ECLKOUT : out BIT ;
ED : inout BIT_VECTOR( 0 to 31 );
EINT4_Z : in BIT ;
EINT5_Z : in BIT ;
EINT6_Z : in BIT ;
EINT7_Z : in BIT ;
EMU0 : in BIT ; -- COMPLIANCE BIT 0 for BSDL must be 'in'
EMU1 : in BIT ; -- COMPLIANCE BIT 0 for BSDL must be 'in'
EMU2 : in BIT ;
EMU3 : in BIT ;
EMU4 : in BIT ;
EMU5 : in BIT ;
RSV0 : in BIT ; -- datasheet says "leave NC"
RSV1 : in BIT ; -- datasheet says "leave NC"
FSR0 : inout BIT ;
FSR1 : inout BIT ;
FSX0 : inout BIT ;
FSX1 : inout BIT ;
HAS_Z : in BIT ;
HCNTRL : in BIT_VECTOR( 0 to 1 );
HCS_Z : in BIT ;
HD : inout BIT_VECTOR( 0 to 15 );
HDS1_Z : in BIT ;
HDS2_Z : in BIT ;
HHWIL : in BIT ;
HINT_Z : out BIT ;
HOLD_Z : in BIT ;
HOLDA_Z : out BIT ;
HRDY_Z : out BIT ;
HRW : in BIT ;
NMI : in BIT ;
RESET_Z : in BIT ;
SDCAS_Z : out BIT ;
SDRAS_Z : out BIT ;
SDWE_Z : out BIT ;
TCK : in BIT ;
TDI : in BIT ;
TDO : out BIT ;
TINP0 : in BIT ;
TINP1 : in BIT ;
TMS : in BIT ;
TOUT0 : out BIT ;
TOUT1 : out BIT ;
TRST_Z : in BIT ;
TSTSTRB : in BIT ; -- COMPLIANCE BIT 0 for BSDL, datasheet = GND
CLKOUT1 : out BIT ;
PLLF : LINKAGE BIT ;
RSV2 : LINKAGE BIT ; -- datasheet says "leave NC"
RSV3 : LINKAGE BIT ; -- datasheet says "leave NC"
RSV4 : LINKAGE BIT ; -- datasheet says "leave NC"
RSV5 : LINKAGE BIT ; -- datasheet says "leave NC"
VDD1_8V : LINKAGE BIT_VECTOR (0 to 19);
VDD3_3V : LINKAGE BIT_VECTOR (0 to 28);
PLLV : LINKAGE BIT;
VSS : LINKAGE BIT_VECTOR (0 to 37);
PLLG : LINKAGE BIT
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of TMS320C6711 : entity is "STD_1149_1_1993";
attribute PIN_MAP of TMS320C6711 : entity is PHYSICAL_PIN_MAP;
constant GFN : PIN_MAP_STRING :=
"ARDY : Y05,"&
"BE_Z : (V20,U19,Y04,V05),"&
"BUSREQ : J19,"&
"CE_Z : (V17,W18,W06,V06),"&
"CLKIN : A03,"&
"CLKOUT2 : Y12,"&
"CLKR0 : H03,"&
"CLKR1 : M01,"&
"CLKS0 : K03,"&
"CLKS1 : E01,"&
"CLKX0 : G03,"&
"CLKX1 : L03,"&
"CLKMODE0 : C04,"&
"DR0 : J01,"&
"DR1 : M02,"&
"DX0 : H02,"&
"DX1 : L02,"&
"EA : (Y06,V07,W07,V08,W08,Y08,V09,Y09,"&
"V10,W13,V14,W14,Y14,W15,Y15,V16,"&
"Y16,W17,Y18,U18),"&
"ECLKIN : Y11,"&
"ECLKOUT : Y10,"&
"ED : (K18,K19,L18,L19,M19,M20,N18,N19,"&
"N20,P18,P20,R19,R20,T18,T20,T19,"&
"V04,W04,Y03,V02,V01,U02,U01,U03,"&
"T01,T02,R03,R02,P01,P02,P03,N03),"&
"EINT4_Z : C02,"&
"EINT5_Z : C01,"&
"EINT6_Z : D02,"&
"EINT7_Z : E03,"&
"EMU0 : D09,"&
"EMU1 : B09,"&
"EMU2 : D10,"&
"EMU3 : B10,"&
"EMU4 : C11,"&
"EMU5 : B12,"&
"RSV0 : C12,"&
"RSV1 : D12,"&
"FSR0 : J03,"&
"FSR1 : M03,"&
"FSX0 : H01,"&
"FSX1 : L01,"&
"HAS_Z : E18,"&
"HCNTRL : (G18,G19),"&
"HCS_Z : F20,"&
"HD : (E20,D20,D18,C20,C19,B18,C17,A18,"&
"B17,C16,B16,A16,C15,A15,C14,B14),"&
"HDS1_Z : E19,"&
"HDS2_Z : F18,"&
"HHWIL : H20,"&
"HINT_Z : J20,"&
"HOLD_Z : J17,"&
"HOLDA_Z : J18,"&
"HRDY_Z : H19,"&
"HRW : G20,"&
"RSV3 : D03,"&
"RSV5 : Y20,"&
"RSV2 : A05,"&
"RSV4 : N02,"&
"NMI : C13,"&
"PLLF : B05,"&
"RESET_Z : A13,"&
"SDCAS_Z : V11,"&
"SDRAS_Z : W10,"&
"SDWE_Z : V12,"&
"TCK : A06,"&
"TDI : A07,"&
"TDO : A08,"&
"TINP0 : G02,"&
"TINP1 : F02,"&
"TMS : B07,"&
"TOUT0 : G01,"&
"TOUT1 : F01,"&
"TRST_Z : B06,"&
"TSTSTRB : B04,"& -- GND in datasheet
"CLKOUT1 : D07,"&
"VDD1_8V : (A09,A10,A12,B02,B19,C03,C07,C18,"&
"D05,D14,K01,K17,L04,L20,U11,U14,"&
"V03,V18,W02,W19),"&
"VDD3_3V : (A17,B03,B08,B13,C05,C10,D01,D16,"&
"D19,F03,H18,J02,M18,N01,R01,R18,"&
"T03,U05,U07,U12,U16,V13,V15,V19,"&
"W03,W09,W12,Y07,Y17),"&
"PLLV : A04,"&
"VSS : (A02,A11,A14,A19,A20,B01,B11,B15,"&
"B20,C08,C09,E02,E04,E17,F19,G04,"&
"G17,J04,K02,K20,M04,M17,P04,P17,"&
"P19,T04,T17,U09,U20,W01,W05,W11,"&
"W16,W20,Y01,Y02,Y13,Y19),"&
"PLLG : C06";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6,BOTH);
attribute TAP_SCAN_RESET of TRST_Z : signal is true;
attribute COMPLIANCE_PATTERNS of TMS320C6711 : entity is "(EMU0,EMU1,TSTSTRB)(000)";
attribute INSTRUCTION_LENGTH of TMS320C6711 : entity is 8;
-- There are no "unused instructions", all possible instruction codes are either Public or Private.
attribute INSTRUCTION_OPCODE of TMS320C6711 : entity is
"PRIVATE2 (00100101),"& -- SMMID instruction not for customer use
"PRIVATE00 (1XXXXX0X),"&
"PRIVATE01 (0XXX1X0X),"&
"PRIVATE02 (XXXXXX10),"&
"PRIVATE03 (XXXXX011),"&
"PRIVATE04 (XXXX0111),"&
"PRIVATE05 (01XX0X0X),"& -- includes 01010101 Private instruction
"PRIVATE06 (XXX01111),"&
"PRIVATE07 (001X0X00),"&
"PRIVATE08 (00010X0X),"&
"PRIVATE09 (XX011111),"&
"PRIVATE10 (0X111111),"&
"PRIVATE11 (001X0001),"&
"PRIVATE12 (00110101),"&
"PRIVATE13 (00000101),"&
"PRIVATE14 (10111111),"&
"IDCODE_X (00000100),"& -- change IDCODE to IDCODE_X because TLR does not capture IDCODE.
"EXTEST (00000000),"& -- redundant, but harmless to list here
"BYPASS (11111111),"& -- redundant, but harmless to list here
"SAMPLE (00000001)"; -- redundant, but harmless to list here
attribute INSTRUCTION_CAPTURE of TMS320C6711 : entity is "XXXXXX01"; -- C6711 PG2.1
--attribute INSTRUCTION_CAPTURE of TMS320C6711 : entity is "XXXXXXXX"; -- pg1
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE2";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE00";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE01";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE02";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE03";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE04";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE05";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE06";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE07";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE08";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE09";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE10";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE11";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE12";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE13";
attribute INSTRUCTION_PRIVATE of TMS320C6711 : entity is "PRIVATE14";
-- change name of IDCODE to IDCODE_X because TLR
-- (Test-Logic-Reset tap state) does not capture IDCODE into IR
--
-- attribute IDCODE_REGISTER of TMS320C6711 : entity is
-- "1000" & -- variant pg 2.1
-- "0000000001100011" & -- C6711 part number
-- "00000010111" & -- mfg = Texas Instruments
-- "1"; -- must end with 1
attribute REGISTER_ACCESS of TMS320C6711 : entity is
-- PRIVATE instruction does not need to be listed per B.8.13.3 a
-- IDCODE instruction does not need to be listed per B.8.13.3 a
-- change name of IDCODE to IDCODE_X because TLR does not capture IDCODE into IR
"IDCODE_R[32] (IDCODE_X CAPTURES 10000000000001100011000000101111), "&
"BOUNDARY (EXTEST), "& -- redundant, but harmless to list here per B.8.13.3 a
"BOUNDARY (SAMPLE), "& -- redundant, but harmless to list here per B.8.13.3 a
"BYPASS (BYPASS) "; -- redundant, but harmless to list here per B.8.13.3 a
attribute BOUNDARY_LENGTH of TMS320C6711 : entity is 292;
-- IEEE1149.1 suppliment, section B.8.14: "Cell 0 is closest to tdo."
attribute BOUNDARY_REGISTER of TMS320C6711 : entity is
-- num cell port function safe [ccell disval rslt]
" 291 (BC_1, *, control, 1 ),"& -- oe emif
" 290 (BC_1, *, internal, X ),"& -- in ea(0) datasheet pin EA(2)
" 289 (BC_1, ea(0), output3, X, 291, 1, Z ),"&
" 288 (BC_1, *, internal, X ),"& -- in ea(1)
" 287 (BC_1, ea(1), output3, X, 291, 1, Z ),"&
" 286 (BC_1, *, internal, X ),"& -- in ea(2)
" 285 (BC_1, ea(2), output3, X, 291, 1, Z ),"&
" 284 (BC_1, *, internal, X ),"& -- in ea(3)
" 283 (BC_1, ea(3), output3, X, 291, 1, Z ),"&
" 282 (BC_1, *, internal, X ),"& -- in ea(4)
" 281 (BC_1, ea(4), output3, X, 291, 1, Z ),"&
" 280 (BC_1, *, internal, X ),"& -- in ea(5)
" 279 (BC_1, ea(5), output3, X, 291, 1, Z ),"&
" 278 (BC_1, *, internal, X ),"& -- in ea(6)
" 277 (BC_1, ea(6), output3, X, 291, 1, Z ),"&
" 276 (BC_1, *, internal, X ),"& -- in ea(7)
" 275 (BC_1, ea(7), output3, X, 291, 1, Z ),"&
" 274 (BC_1, *, internal, X ),"& -- in ea(8)
" 273 (BC_1, ea(8), output3, X, 291, 1, Z ),"&
" 272 (BC_1, *, internal, X ),"& -- in ea(9)
" 271 (BC_1, ea(9), output3, X, 291, 1, Z ),"&
" 270 (BC_1, *, internal, X ),"& -- in ea(10)
" 269 (BC_1, ea(10), output3, X, 291, 1, Z ),"&
" 268 (BC_1, *, internal, X ),"& -- in ea(11)
" 267 (BC_1, ea(11), output3, X, 291, 1, Z ),"&
" 266 (BC_1, *, internal, X ),"& -- in ea(12)
" 265 (BC_1, ea(12), output3, X, 291, 1, Z ),"&
" 264 (BC_1, *, internal, X ),"& -- in ea(13)
" 263 (BC_1, ea(13), output3, X, 291, 1, Z ),"&
" 262 (BC_1, *, internal, X ),"& -- in ea(14)
" 261 (BC_1, ea(14), output3, X, 291, 1, Z ),"&
" 260 (BC_1, *, internal, X ),"& -- in ea(15)
" 259 (BC_1, ea(15), output3, X, 291, 1, Z ),"&
" 258 (BC_1, *, internal, X ),"& -- in ea(16)
" 257 (BC_1, ea(16), output3, X, 291, 1, Z ),"&
" 256 (BC_1, *, internal, X ),"& -- in ea(17)
" 255 (BC_1, ea(17), output3, X, 291, 1, Z ),"&
" 254 (BC_1, *, internal, X ),"& -- in ea(18)
" 253 (BC_1, ea(18), output3, X, 291, 1, Z ),"&
" 252 (BC_1, *, internal, X ),"& -- in ea(19) datasheet pin EA(21)
" 251 (BC_1, ea(19), output3, X, 291, 1, Z ),"&
" 250 (BC_1, *, internal, X ),"& -- in sdras_z
" 249 (BC_1, sdras_z, output3, X, 291, 1, Z ),"&
" 248 (BC_1, eclkin, input, X ),"&
" 247 (BC_1, *, control, 1 ),"& -- oe eclkout
" 246 (BC_1, *, internal, X ),"& -- in eclkout
" 245 (BC_1, eclkout, output3, X, 247, 1, Z ),"&
" 244 (BC_1, *, control, 1 ),"& -- oe clkout2
" 243 (BC_1, *, internal, X ),"& -- in clkout2
" 242 (BC_1, clkout2, output3, X, 244, 1, Z ),"&
" 241 (BC_1, *, internal, X ),"& -- in sdcas_z
" 240 (BC_1, sdcas_z, output3, X, 291, 1, Z ),"&
" 239 (BC_1, *, internal, X ),"& -- in sdwe_z
" 238 (BC_1, sdwe_z, output3, X, 291, 1, Z ),"&
" 237 (BC_1, *, internal, X ),"& -- in ce_z(0)
" 236 (BC_1, ce_z(0), output3, X, 291, 1, Z ),"&
" 235 (BC_1, *, internal, X ),"& -- in ce_z(1)
" 234 (BC_1, ce_z(1), output3, X, 291, 1, Z ),"&
" 233 (BC_1, *, internal, X ),"& -- in ce_z(2)
" 232 (BC_1, ce_z(2), output3, X, 291, 1, Z ),"&
" 231 (BC_1, *, internal, X ),"& -- in ce_z(3)
" 230 (BC_1, ce_z(3), output3, X, 291, 1, Z ),"&
" 229 (BC_1, *, internal, X ),"& -- in be_z(0)
" 228 (BC_1, be_z(0), output3, X, 291, 1, Z ),"&
" 227 (BC_1, *, internal, X ),"& -- in be_z(1)
" 226 (BC_1, be_z(1), output3, X, 291, 1, Z ),"&
" 225 (BC_1, *, internal, X ),"& -- in be_z(2)
" 224 (BC_1, be_z(2), output3, X, 291, 1, Z ),"&
" 223 (BC_1, *, internal, X ),"& -- in be_z(3)
" 222 (BC_1, be_z(3), output3, X, 291, 1, Z ),"&
" 221 (BC_1, *, internal, 1 ),"& -- oe ardy
" 220 (BC_1, ardy, input, X ),"&
" 219 (BC_1, *, internal, X ),"& -- out3 ardy
" 218 (BC_1, *, control, 1 ),"& -- oe ed(0 to 31)
" 217 (BC_1, ed(0), input, X ),"&
" 216 (BC_1, ed(0), output3, X, 218, 1, Z ),"&
" 215 (BC_1, ed(1), input, X ),"&
" 214 (BC_1, ed(1), output3, X, 218, 1, Z ),"&
" 213 (BC_1, ed(2), input, X ),"&
" 212 (BC_1, ed(2), output3, X, 218, 1, Z ),"&
" 211 (BC_1, ed(3), input, X ),"&
" 210 (BC_1, ed(3), output3, X, 218, 1, Z ),"&
" 209 (BC_1, ed(4), input, X ),"&
" 208 (BC_1, ed(4), output3, X, 218, 1, Z ),"&
" 207 (BC_1, ed(5), input, X ),"&
" 206 (BC_1, ed(5), output3, X, 218, 1, Z ),"&
" 205 (BC_1, ed(6), input, X ),"&
" 204 (BC_1, ed(6), output3, X, 218, 1, Z ),"&
" 203 (BC_1, ed(7), input, X ),"&
" 202 (BC_1, ed(7), output3, X, 218, 1, Z ),"&
" 201 (BC_1, ed(8), input, X ),"&
" 200 (BC_1, ed(8), output3, X, 218, 1, Z ),"&
" 199 (BC_1, ed(9), input, X ),"&
" 198 (BC_1, ed(9), output3, X, 218, 1, Z ),"&
" 197 (BC_1, ed(10), input, X ),"&
" 196 (BC_1, ed(10), output3, X, 218, 1, Z ),"&
" 195 (BC_1, ed(11), input, X ),"&
" 194 (BC_1, ed(11), output3, X, 218, 1, Z ),"&
" 193 (BC_1, ed(12), input, X ),"&
" 192 (BC_1, ed(12), output3, X, 218, 1, Z ),"&
" 191 (BC_1, ed(13), input, X ),"&
" 190 (BC_1, ed(13), output3, X, 218, 1, Z ),"&
" 189 (BC_1, ed(14), input, X ),"&
" 188 (BC_1, ed(14), output3, X, 218, 1, Z ),"&
" 187 (BC_1, ed(15), input, X ),"&
" 186 (BC_1, ed(15), output3, X, 218, 1, Z ),"&
" 185 (BC_1, ed(16), input, X ),"&
" 184 (BC_1, ed(16), output3, X, 218, 1, Z ),"&
" 183 (BC_1, ed(17), input, X ),"&
" 182 (BC_1, ed(17), output3, X, 218, 1, Z ),"&
" 181 (BC_1, ed(18), input, X ),"&
" 180 (BC_1, ed(18), output3, X, 218, 1, Z ),"&
" 179 (BC_1, ed(19), input, X ),"&
" 178 (BC_1, ed(19), output3, X, 218, 1, Z ),"&
" 177 (BC_1, ed(20), input, X ),"&
" 176 (BC_1, ed(20), output3, X, 218, 1, Z ),"&
" 175 (BC_1, ed(21), input, X ),"&
" 174 (BC_1, ed(21), output3, X, 218, 1, Z ),"&
" 173 (BC_1, ed(22), input, X ),"&
" 172 (BC_1, ed(22), output3, X, 218, 1, Z ),"&
" 171 (BC_1, ed(23), input, X ),"&
" 170 (BC_1, ed(23), output3, X, 218, 1, Z ),"&
" 169 (BC_1, ed(24), input, X ),"&
" 168 (BC_1, ed(24), output3, X, 218, 1, Z ),"&
" 167 (BC_1, ed(25), input, X ),"&
" 166 (BC_1, ed(25), output3, X, 218, 1, Z ),"&
" 165 (BC_1, ed(26), input, X ),"&
" 164 (BC_1, ed(26), output3, X, 218, 1, Z ),"&
" 163 (BC_1, ed(27), input, X ),"&
" 162 (BC_1, ed(27), output3, X, 218, 1, Z ),"&
" 161 (BC_1, ed(28), input, X ),"&
" 160 (BC_1, ed(28), output3, X, 218, 1, Z ),"&
" 159 (BC_1, ed(29), input, X ),"&
" 158 (BC_1, ed(29), output3, X, 218, 1, Z ),"&
" 157 (BC_1, ed(30), input, X ),"&
" 156 (BC_1, ed(30), output3, X, 218, 1, Z ),"&
" 155 (BC_1, ed(31), input, X ),"&
" 154 (BC_1, ed(31), output3, X, 218, 1, Z ),"&
" 153 (BC_1, *, control, 1 ),"& -- oe busreq
" 152 (BC_1, *, internal, X ),"& -- in busreq
" 151 (BC_1, busreq, output3, X, 153, 1, Z ),"&
" 150 (BC_1, *, control, 1 ),"& -- oe holda_z
" 149 (BC_1, *, internal, X ),"& -- in holda_z
" 148 (BC_1, holda_z, output3, X, 150, 1, Z ),"&
" 147 (BC_1, *, internal, 1 ),"& -- oe hold_z
" 146 (BC_1, hold_z, input, X ),"&
" 145 (BC_1, *, internal, X ),"& -- out hold_z
" 144 (BC_1, *, control, 1 ),"& -- oe hint_z
" 143 (BC_1, *, internal, X ),"& -- in hint_z
" 142 (BC_1, hint_z, output3, X, 144, 1, Z ),"&
" 141 (BC_1, *, control, 1 ),"& -- oe hrdy_z
" 140 (BC_1, *, internal, X ),"& -- in hrdy_z
" 139 (BC_1, hrdy_z, output3, X, 141, 1, Z ),"&
" 138 (BC_1, hhwil, input, X ),"&
" 137 (BC_1, *, internal, 1 ),"& -- out3 hhwil
" 136 (BC_1, hrw, input, X ),"&
" 135 (BC_1, *, internal, 1 ),"& -- out3 hrw
" 134 (BC_1, hcntrl(0), input, X ),"&
" 133 (BC_1, *, internal, 1 ),"& -- out3 hcntrl(0)
" 132 (BC_1, hcntrl(1), input, X ),"&
" 131 (BC_1, *, internal, 1 ),"& -- out3 hcntrl(1)
" 130 (BC_1, hcs_z, input, X ),"&
" 129 (BC_1, *, internal, 1 ),"& -- out3 hcs_z
" 128 (BC_1, has_z, input, X ),"&
" 127 (BC_1, *, internal, 1 ),"& -- out3 has_z
" 126 (BC_1, hds1_z, input, X ),"&
" 125 (BC_1, *, internal, 1 ),"& -- out3 hds1_z
" 124 (BC_1, hds2_z, input, X ),"&
" 123 (BC_1, *, internal, 1 ),"& -- out3 hds2_z
" 122 (BC_1, *, control, 1 ),"& -- oe hdbus
" 121 (BC_1, hd(0), input, X ),"&
" 120 (BC_1, hd(0), output3, X, 122, 1, Z ),"&
" 119 (BC_1, hd(1), input, X ),"&
" 118 (BC_1, hd(1), output3, X, 122, 1, Z ),"&
" 117 (BC_1, hd(2), input, X ),"&
" 116 (BC_1, hd(2), output3, X, 122, 1, Z ),"&
" 115 (BC_1, hd(3), input, X ),"&
" 114 (BC_1, hd(3), output3, X, 122, 1, Z ),"&
" 113 (BC_1, hd(4), input, X ),"&
" 112 (BC_1, hd(4), output3, X, 122, 1, Z ),"&
" 111 (BC_1, hd(5), input, X ),"&
" 110 (BC_1, hd(5), output3, X, 122, 1, Z ),"&
" 109 (BC_1, hd(8), input, X ),"&
" 108 (BC_1, hd(8), output3, X, 122, 1, Z ),"&
" 107 (BC_1, hd(6), input, X ),"&
" 106 (BC_1, hd(6), output3, X, 122, 1, Z ),"&
" 105 (BC_1, hd(7), input, X ),"&
" 104 (BC_1, hd(7), output3, X, 122, 1, Z ),"&
" 103 (BC_1, hd(9), input, X ),"&
" 102 (BC_1, hd(9), output3, X, 122, 1, Z ),"&
" 101 (BC_1, hd(10), input, X ),"&
" 100 (BC_1, hd(10), output3, X, 122, 1, Z ),"&
" 99 (BC_1, hd(11), input, X ),"&
" 98 (BC_1, hd(11), output3, X, 122, 1, Z ),"&
" 97 (BC_1, hd(12), input, X ),"&
" 96 (BC_1, hd(12), output3, X, 122, 1, Z ),"&
" 95 (BC_1, hd(13), input, X ),"&
" 94 (BC_1, hd(13), output3, X, 122, 1, Z ),"&
" 93 (BC_1, hd(14), input, X ),"&
" 92 (BC_1, hd(14), output3, X, 122, 1, Z ),"&
" 91 (BC_1, hd(15), input, X ),"&
" 90 (BC_1, hd(15), output3, X, 122, 1, Z ),"&
" 89 (BC_1, *, internal, 1 ),"& -- oe emu0
" 88 (BC_1, *, internal, 0 ),"& -- in emu0 must be 0
" 87 (BC_1, *, internal, 0 ),"& -- out3 emu0
" 86 (BC_1, *, internal, 1 ),"& -- oe emu1
" 85 (BC_1, *, internal, 0 ),"& -- in emu1 must be 0
" 84 (BC_1, *, internal, 0 ),"& -- out3 emu1
" 83 (BC_1, *, internal, X ),"& ------- not an oe, oe for emu2-5 is tied disabled
" 82 (BC_1, emu2, input, X ),"& -- in emu2
" 81 (BC_1, *, internal, X ),"& -- out3 emu2
" 80 (BC_1, *, internal, X ),"&
" 79 (BC_1, emu3, input, X ),"& -- in emu3
" 78 (BC_1, *, internal, X ),"& -- out3 emu3
" 77 (BC_1, *, internal, X ),"&
" 76 (BC_1, emu4, input, X ),"& -- in emu4
" 75 (BC_1, *, internal, X ),"& -- out3 emu4
" 74 (BC_1, *, internal, X ),"&
" 73 (BC_1, emu5, input, X ),"& -- in emu5
" 72 (BC_1, *, internal, X ),"& -- out3 emu5
" 71 (BC_1, *, internal, 1 ),"& -- oe RSV0
" 70 (BC_1, RSV0, input, X ),"& -- in RSV0
" 69 (BC_1, *, internal, X ),"& -- out3 RSV0
" 68 (BC_1, *, internal, 1 ),"& -- oe RSV1
" 67 (BC_1, RSV1, input, X ),"& -- in RSV1
" 66 (BC_1, *, internal, X ),"& -- out3 RSV1
" 65 (BC_1, *, control, 1 ),"& -- oe clkout1
" 64 (BC_1, *, internal, X ),"& -- in
" 63 (BC_1, clkout1, output3, X, 65, 1, Z ),"&
" 62 (BC_1, clkmode0, input, X ),"&
" 61 (BC_1, reset_z, input, X ),"&
" 60 (BC_1, clkin, input, X ),"&
" 59 (BC_1, nmi, input, X ),"&
" 58 (BC_1, *, internal, 1 ),"& -- out3 nmi
" 57 (BC_1, eint4_z, input, X ),"&
" 56 (BC_1, *, internal, 1 ),"& -- out3 eint4_z
" 55 (BC_1, eint5_z, input, X ),"&
" 54 (BC_1, *, internal, 1 ),"& -- out3 eint5_z
" 53 (BC_1, eint6_z, input, X ),"&
" 52 (BC_1, *, internal, 1 ),"& -- out3 eint6_z
" 51 (BC_1, eint7_z, input, X ),"&
" 50 (BC_1, *, internal, 1 ),"& -- out3 eint7_z
" 49 (BC_1, tinp0, input, X ),"&
" 48 (BC_1, *, internal, 1 ),"& -- out3 tinp0
" 47 (BC_1, tinp1, input, X ),"&
" 46 (BC_1, *, internal, 1 ),"& -- out3 tinp1
" 45 (BC_1, *, control, 1 ),"& -- oe tout1
" 44 (BC_1, *, internal, X ),"& -- in tout1
" 43 (BC_1, tout1, output3, X, 45, 1, Z ),"&
" 42 (BC_1, *, control, 1 ),"& -- oe tout0
" 41 (BC_1, *, internal, X ),"& -- in tout0
" 40 (BC_1, tout0, output3, X, 42, 1, Z ),"&
" 39 (BC_1, *, control, 1 ),"& -- oe clkr0
" 38 (BC_1, clkr0, input, X ),"&
" 37 (BC_1, clkr0, output3, X, 39, 1, Z ),"&
" 36 (BC_1, *, control, 1 ),"& -- oe clkx0
" 35 (BC_1, clkx0, input, X ),"&
" 34 (BC_1, clkx0, output3, X, 36, 1, Z ),"&
" 33 (BC_1, dr0, input, X ),"&
" 32 (BC_1, *, internal, 1 ),"&
" 31 (BC_1, *, control, 1 ),"& -- oe dx0
" 30 (BC_1, *, internal, X ),"& -- in dx0
" 29 (BC_1, dx0, output3, X, 31, 1, Z ),"&
" 28 (BC_1, *, control, 1 ),"& -- oe fsr0
" 27 (BC_1, fsr0, input, X ),"&
" 26 (BC_1, fsr0, output3, X, 28, 1, Z ),"&
" 25 (BC_1, *, control, 1 ),"& -- oe fsx0
" 24 (BC_1, fsx0, input, X ),"&
" 23 (BC_1, fsx0, output3, X, 25, 1, Z ),"&
" 22 (BC_1, clks0, input, X ),"&
" 21 (BC_1, *, internal, 1 ),"& -- out3 clks0
" 20 (BC_1, *, control, 1 ),"& -- oe clkr1
" 19 (BC_1, clkr1, input, X ),"&
" 18 (BC_1, clkr1, output3, X, 20, 1, Z ),"&
" 17 (BC_1, *, control, 1 ),"& -- oe clkx1
" 16 (BC_1, clkx1, input, X ),"&
" 15 (BC_1, clkx1, output3, X, 17, 1, Z ),"&
" 14 (BC_1, dr1, input, X ),"&
" 13 (BC_1, *, internal, 1 ),"& -- out3 dr1
" 12 (BC_1, *, control, 1 ),"& -- oe dx1
" 11 (BC_1, *, internal, X ),"& -- in dx1
" 10 (BC_1, dx1, output3, X, 12, 1, Z ),"&
" 9 (BC_1, *, control, 1 ),"& -- oe fsr1
" 8 (BC_1, fsr1, input, X ),"&
" 7 (BC_1, fsr1, output3, X, 9, 1, Z ),"&
" 6 (BC_1, *, control, 1 ),"& -- oe fsx1
" 5 (BC_1, fsx1, input, X ),"&
" 4 (BC_1, fsx1, output3, X, 6, 1, Z ),"&
" 3 (BC_1, clks1, input, X ),"&
" 2 (BC_1, *, internal, 1 ),"& -- out3 clks1
" 1 (BC_1, *, internal, 1 ),"& -- rmv_pullup_reg
" 0 (BC_1, *, internal, 1 ) "; -- rmv_pulldn_reg
attribute DESIGN_WARNING of TMS320C6711 : entity is
"This device has no unused instruction codes. "&
"TLR does not load IDCODE instruction, so IDCODE instruction has been "&
" renamed to IDCODE_X instruction with otherwise same functionality. "&
"IDCODE_X register does not support PAUSE_DR tap state, it will recapture."&
"BYPASS register does not support PAUSE_DR tap state, it will recapture 0."&
"Instruction reg does not support PAUSE_IR tap state, it will recapture."&
" Registers that do not support PAUSE_xR tap states will still work "&
"correctly if the following TAP sequence is used:"&
" Select "&
" Capture "&
" Shift <repeat as needed> "&
" Exit1 "&
" Update "&
" Applies to either IR path or DR path. ";
end TMS320C6711;