This BSDL contains syntax errors!
-- ***********************************************************************
-- BSDL file for design IDT82P2282
-- Created by Synopsys Version 1999.10 (Sep 02, 1999)
-- Designer: H. Pu
-- Company: Integrated Devices Technolgy, Inc.
-- Date: Thu Sep 4 11:10:45 2003
-- ***********************************************************************
entity IDT82P2282 is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "TQFP100");
-- This section declares all the ports in the design.
port (
CSB : in bit;
DSB_RDB : in bit;
MPM : in bit;
OSCI : in bit;
REF_IN_1544 : in bit;
REF_IN_2048 : in bit;
RESETB : in bit;
RWB_WRB : in bit;
SPIEN : in bit;
TCK : in bit;
TDI : in bit;
THZ : in bit;
TMS : in bit;
TRSTB : in bit;
A : in bit_vector (0 to 8);
CLK_SEL : in bit_vector (0 to 2);
TSD : in bit_vector (1 to 2);
TSIG : in bit_vector (1 to 2);
GPIO : inout bit;
D : inout bit_vector (0 to 7);
RSCK : inout bit_vector (1 to 2);
RSFS : inout bit_vector (1 to 2);
TSCK : inout bit_vector (1 to 2);
TSFS : inout bit_vector (1 to 2);
INTB : out bit;
TDO : out bit;
RSD : out bit_vector (1 to 2);
RSIG : out bit_vector (1 to 2);
CLK_GEN : buffer bit;
RefA_OUT : buffer bit;
RefB_OUT : buffer bit;
GNDAB : linkage bit;
GNDAP : linkage bit;
GNDAR[1] : linkage bit;
GNDAR[2] : linkage bit;
GNDAT[1] : linkage bit;
GNDAT[2] : linkage bit;
GNDAX[1] : linkage bit;
GNDAX[2] : linkage bit;
GNDDC[0] : linkage bit;
GNDDC[1] : linkage bit;
GNDDC[2] : linkage bit;
GNDDC[3] : linkage bit;
GNDDIO[0] : linkage bit;
GNDDIO[1] : linkage bit;
GNDDIO[2] : linkage bit;
VDDAB : linkage bit;
VDDAP : linkage bit;
VDDAR[1] : linkage bit;
VDDAR[2] : linkage bit;
VDDAT[1] : linkage bit;
VDDAT[2] : linkage bit;
VDDAX[1] : linkage bit;
VDDAX[2] : linkage bit;
VDDDC[0] : linkage bit;
VDDDC[1] : linkage bit;
VDDDC[2] : linkage bit;
VDDDC[3] : linkage bit;
VDDDIO[0] : linkage bit;
VDDDIO[1] : linkage bit;
VDDDIO[2] : linkage bit;
NC : linkage bit_vector (1 to 14)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of IDT82P2282: entity is "STD_1149_1_1993";
attribute PIN_MAP of IDT82P2282: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant TQFP100: PIN_MAP_STRING :=
"CSB : P48," &
"DSB_RDB : P46," &
"MPM : P32," &
"OSCI : P95," &
"REF_IN_1544 : P83," &
"REF_IN_2048 : P82," &
"RESETB : P84," &
"RWB_WRB : P47," &
"SPIEN : P33," &
"TCK : P98," &
"TDI : P99," &
"THZ : P2," &
"TMS : P100," &
"TRSTB : P97," &
"A : (P52, P53, P54, P55, P56, P57, P60, P62, P63)," &
"CLK_SEL : (P85, P86, P87)," &
"TSD : (P75, P67)," &
"TSIG : (P74, P66)," &
"GPIO : P1," &
"D : (P34, P35, P36, P37, P38, P39, P41, P43)," &
"RSCK : (P80, P72)," &
"RSFS : (P77, P69)," &
"TSCK : (P76, P68)," &
"TSFS : (P73, P65)," &
"INTB : P49," &
"TDO : P96," &
"RSD : (P79, P71)," &
"RSIG : (P78, P70)," &
"CLK_GEN : P81," &
"RefA_OUT : P90," &
"RefB_OUT : P92," &
"GNDAB : P7," &
"GNDAP : P5," &
"GNDAR[1] : P29," &
"GNDAR[2] : P10," &
"GNDAT[1] : P24," &
"GNDAT[2] : P15," &
"GNDAX[1] : P23," &
"GNDAX[2] : P16," &
"GNDDC[0] : P88," &
"GNDDC[1] : P45," &
"GNDDC[2] : P58," &
"GNDDC[3] : P4," &
"GNDDIO[0] : P89," &
"GNDDIO[1] : P44," &
"GNDDIO[2] : P59," &
"VDDAB : P8," &
"VDDAP : P6," &
"VDDAR[1] : P26," &
"VDDAR[2] : P13," &
"VDDAT[1] : P25," &
"VDDAT[2] : P14," &
"VDDAX[1] : P20," &
"VDDAX[2] : P19," &
"VDDDC[0] : P91," &
"VDDDC[1] : P42," &
"VDDDC[2] : P61," &
"VDDDC[3] : P3," &
"VDDDIO[0] : P93," &
"VDDDIO[1] : P40," &
"VDDDIO[2] : P64," &
"NC : (P9, P11, P12, P17, P18, P21, P22, P27, P28, P30, P31" &
", P50, P51, P94)";
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRSTB: signal is true;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of IDT82P2282: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of IDT82P2282: entity is
"BYPASS (111)," &
"EXTEST (000)," &
"SAMPLE (010)," &
"CLAMP (011)," &
"HIGHZ (100)," &
"USER1 (110)," &
"IDCODE (001)," &
"USER2 (101)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of IDT82P2282: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of IDT82P2282: entity is
"0000" & -- 4-bit version number
"0000010010111010" & -- 16-bit part number
"00000110011" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of IDT82P2282: entity is
"BYPASS (BYPASS, CLAMP, HIGHZ, USER1)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"DEVICE_ID (IDCODE)," &
"UTDR1[20] (USER2)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of IDT82P2282: entity is 77;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of IDT82P2282: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"76 (BC_4, OSCI, observe_only, X), " &
"75 (BC_1, RefB_OUT, output2, X), " &
"74 (BC_1, RefA_OUT, output2, X), " &
"73 (BC_4, CLK_SEL(2), observe_only, X), " &
"72 (BC_4, CLK_SEL(1), observe_only, X), " &
"71 (BC_4, CLK_SEL(0), observe_only, X), " &
"70 (BC_4, RESETB, observe_only, X), " &
"69 (BC_4, REF_IN_1544, observe_only, X), " &
"68 (BC_4, REF_IN_2048, observe_only, X), " &
"67 (BC_1, CLK_GEN, output2, X), " &
"66 (BC_1, *, controlr, 1), " &
"65 (BC_4, RSCK(1), observe_only, X), " &
"64 (BC_1, RSCK(1), output3, X, 66, 1, PULL1)," &
"63 (BC_1, *, controlr, 1), " &
"62 (BC_1, RSD(1), output3, X, 63, 1, Z), " &
"61 (BC_1, RSIG(1), output3, X, 63, 1, Z), " &
"60 (BC_4, RSFS(1), observe_only, X), " &
"59 (BC_1, RSFS(1), output3, X, 66, 1, PULL1)," &
"58 (BC_1, *, controlr, 1), " &
"57 (BC_4, TSCK(1), observe_only, X), " &
"56 (BC_1, TSCK(1), output3, X, 58, 1, PULL1)," &
"55 (BC_4, TSD(1), observe_only, X), " &
"54 (BC_4, TSIG(1), observe_only, X), " &
"53 (BC_4, TSFS(1), observe_only, X), " &
"52 (BC_1, TSFS(1), output3, X, 58, 1, PULL1)," &
"51 (BC_1, *, controlr, 1), " &
"50 (BC_4, RSCK(2), observe_only, X), " &
"49 (BC_1, RSCK(2), output3, X, 51, 1, PULL1)," &
"48 (BC_1, *, controlr, 1), " &
"47 (BC_1, RSD(2), output3, X, 48, 1, Z), " &
"46 (BC_1, RSIG(2), output3, X, 48, 1, Z), " &
"45 (BC_4, RSFS(2), observe_only, X), " &
"44 (BC_1, RSFS(2), output3, X, 51, 1, PULL1)," &
"43 (BC_1, *, controlr, 1), " &
"42 (BC_4, TSCK(2), observe_only, X), " &
"41 (BC_1, TSCK(2), output3, X, 43, 1, PULL1)," &
"40 (BC_4, TSD(2), observe_only, X), " &
"39 (BC_4, TSIG(2), observe_only, X), " &
"38 (BC_4, TSFS(2), observe_only, X), " &
"37 (BC_1, TSFS(2), output3, X, 43, 1, PULL1)," &
"36 (BC_4, A(8), observe_only, X), " &
"35 (BC_4, A(7), observe_only, X), " &
"34 (BC_4, A(6), observe_only, X), " &
"33 (BC_4, A(5), observe_only, X), " &
"32 (BC_4, A(4), observe_only, X), " &
"31 (BC_4, A(3), observe_only, X), " &
"30 (BC_4, A(2), observe_only, X), " &
"29 (BC_4, A(1), observe_only, X), " &
"28 (BC_4, A(0), observe_only, X), " &
"27 (BC_1, *, control, 1), " &
"26 (BC_1, INTB, output3, X, 27, 1, Z), " &
"25 (BC_4, CSB, observe_only, X), " &
"24 (BC_4, RWB_WRB, observe_only, X), " &
"23 (BC_4, DSB_RDB, observe_only, X), " &
"22 (BC_1, *, control, 1), " &
"21 (BC_4, D(7), observe_only, X), " &
"20 (BC_1, D(7), output3, X, 22, 1, Z), " &
"19 (BC_4, D(6), observe_only, X), " &
"18 (BC_1, D(6), output3, X, 22, 1, Z), " &
"17 (BC_4, D(5), observe_only, X), " &
"16 (BC_1, D(5), output3, X, 22, 1, Z), " &
"15 (BC_4, D(4), observe_only, X), " &
"14 (BC_1, D(4), output3, X, 22, 1, Z), " &
"13 (BC_4, D(3), observe_only, X), " &
"12 (BC_1, D(3), output3, X, 22, 1, Z), " &
"11 (BC_4, D(2), observe_only, X), " &
"10 (BC_1, D(2), output3, X, 22, 1, Z), " &
"9 (BC_4, D(1), observe_only, X), " &
"8 (BC_1, D(1), output3, X, 22, 1, Z), " &
"7 (BC_4, D(0), observe_only, X), " &
"6 (BC_1, D(0), output3, X, 22, 1, Z), " &
"5 (BC_4, SPIEN, observe_only, X), " &
"4 (BC_4, MPM, observe_only, X), " &
"3 (BC_4, THZ, observe_only, X), " &
"2 (BC_1, *, control, 1), " &
"1 (BC_4, GPIO, observe_only, X), " &
"0 (BC_1, GPIO, output3, X, 2, 1, PULL1)";
end IDT82P2282;