BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: IDT79RC32T332

-- IDT79RC32T332 BSDL File
-- Title:   $Source: /home/slp3/koa3.0/repos/koa3.0/report.dir/bsdl.208.doc,v $
--          Copyright Integrated Device Technology 2003
-- Update:
--          $Log: bsdl.208.doc,v $
--          Revision 1.7  2003/01/29 22:14:51  andyng
--          AN: updated part name.
--
--          Revision 1.6  2003/01/23 16:55:07  andyng
--          AN: Upgraded part name and JTAG IDCODE.
--
--

entity idt79rc32t332 is
    generic (PHYSICAL_PIN_MAP: string:= "UNDEFINED");

    port (
        cpu_coldreset_n		:in         	bit;
        cpu_dt_r_n		:inout      	bit;
        cpu_int_n_0		:in         	bit;
        cpu_int_n_1		:in         	bit;
        cpu_masterclk   	:in         	bit;
        cpu_nmi_n		:in         	bit;
        debug_cpu_ack_n		:inout        	bit;
        debug_cpu_ads_n		:inout        	bit;
        debug_cpu_dma_n		:inout        	bit;
        debug_cpu_i_d_n		:inout        	bit;
        dma_ready_n_0     	:inout        	bit;
        ejtag_dclk		:out          	bit;
        ejtag_debugboot		:in           	bit;
        ejtag_pcst      	:inout        	bit_vector(0     to     2);
        ejtag_tms      		:linkage      	bit;
        jtag_tck      		:in           	bit;
        jtag_tdi             	:in         	bit;
        jtag_tdo             	:out        	bit;
        jtag_tms             	:in         	bit;
        jtag_trst_n          	:in         	bit;
        mem_245_oe_n         	:inout      	bit;
        mem_addr_lsb   	 	:out  		bit_vector(2     to     3);
        mem_addr_mid   	 	:inout		bit_vector(4     to    22);
        mem_cs_n       	 	:out		bit_vector(0     to     5);
        mem_data		:inout		bit_vector(0     to    31);
        mem_oe_n         	:inout      	bit;
        mem_wait_n           	:in         	bit;
        mem_we_n       	 	:out		bit_vector(0     to     3);
        output_clk            	:out        	bit;
        pci_ad               	:inout      	bit_vector(0     to    31);
        pci_cbe_n            	:inout      	bit_vector(0     to     3);
        pci_clk              	:in         	bit;
        pci_devsel_n        	:inout      	bit;
        pci_frame_n          	:inout      	bit;
        pci_gnt_n_0		:inout		bit;
        pci_gnt_n_1		:inout		bit;
        pci_gnt_n_2		:out		bit;
        pci_irdy_n           	:inout     	bit;
        pci_lock_n           	:in         	bit;
        pci_par              	:inout     	bit;
        pci_perr_n           	:inout      	bit;
        pci_req_n_0            	:inout      	bit;
        pci_req_n_2		:in		bit;
        pci_rst_n            	:in         	bit;
        pci_serr_n           	:inout      	bit;
        pci_stop_n           	:inout      	bit;
        pci_trdy_n           	:inout      	bit;
        sdram_245_oe_n		:out        	bit;
        sdram_addr_12           :inout          bit;
        sdram_bemask_n 		:out        	bit_vector(0     to     3);
        sdram_cas_n          	:out        	bit;
        sdram_cke            	:out        	bit;
        sdram_cs_n           	:out        	bit_vector(0     to     3);
        sdram_ras_n          	:out       	bit;
        sdram_s_n          	:out       	bit_vector(0     to     1);
        sdram_we_n           	:out        	bit;
        spi_miso             	:inout      	bit;
        spi_mosi             	:inout      	bit;
        spi_sck             	:inout      	bit;
        spi_ss_n            	:inout      	bit;
        test_cronus_mode_n  	:linkage    	bit;
        test_rhea_mode_n  	:linkage    	bit;
        uart_rx_0            	:inout      	bit;
        uart_tx_0               :inout          bit;
        vcccore                 :linkage        bit_vector(0     to     4);
        vccp                    :linkage        bit;
        vccio                   :linkage        bit_vector(0     to    15);
        vss                     :linkage        bit_vector(0     to    19);
        vssp                    :linkage        bit
    );

    use STD_1149_1_1994.all;

    attribute COMPONENT_CONFORMANCE of idt79rc32t332:
    entity is "STD_1149_1_1993";

    attribute PIN_MAP of idt79rc32t332 : entity is PHYSICAL_PIN_MAP;

--    Pin-port map for package PQFP208

--    note: test_cronus_mode_n must be driven high.
--    note: test_rhea_mode_n must be driven high.
--    note: ejtag_tms must be driven high.
--
--    note: SAMPLE instruction if used, should be initialized after power-up with
--          cpu_coldreset_n driven low
--          pci_rst_n driven low
--          pci_clk toggling
--          cpu_masterclk toggling
--
--    note: pci_req_n_2 and pci_gnt_n_2 cells are swapped relative to their
--          pin/pad position

    constant PQFP208 : PIN_MAP_STRING :=
        "cpu_coldreset_n:52," &
        "cpu_dt_r_n:83," &
        "cpu_int_n_0:160," &
        "cpu_int_n_1:161," &
        "cpu_masterclk:64," &
        "cpu_nmi_n:95," &
        "debug_cpu_ack_n:179," &
        "debug_cpu_ads_n:178," &
        "debug_cpu_dma_n:180," &
        "debug_cpu_i_d_n:177," &
        "dma_ready_n_0:189," &
        "ejtag_dclk:175," &
        "ejtag_debugboot:176," &
        "ejtag_pcst:(170, 171, 174)," &
        "ejtag_tms:167," &
        "jtag_tck:168," &
        "jtag_tdi:164," &
        "jtag_tdo:165," &
        "jtag_tms:166," &
        "jtag_trst_n:169," &
        "mem_245_oe_n:190," &
        "mem_addr_lsb:(13, 14)," &
        "mem_addr_mid:(15, 18, 19, 20, 21, 22, 23, 24," &
                  "28, 35, 38, 39, 40, 41, 42, 43, 44, 45, 48)," &
        "mem_cs_n:(195, 196, 197, 198, 199, 200)," &
        "mem_data:(66, 70, 72, 74, 76, 80, 85, 87," &
                  "91, 93, 49, 50, 53, 55, 57, 63," & 
                  "61, 60, 56, 54, 51, 94, 92, 90," &
                  "86, 84, 79, 75, 73, 71, 67, 65)," &
        "mem_oe_n:194," &
        "mem_wait_n:191," &
        "mem_we_n:(201, 204, 205, 206)," &
        "output_clk:25," &
        "pci_ad:(96, 97, 100, 101, 102, 103, 104, 105," &
                "107, 108, 109, 112, 113, 114, 115, 116," &
                "132, 133, 134, 135, 136, 137, 138, 139," &
                "143, 144, 145, 146, 147, 148, 149, 152)," &
        "pci_cbe_n:(106, 117, 129, 142)," &
        "pci_clk:155," &
        "pci_devsel_n:125," &
        "pci_frame_n:128," &
        "pci_gnt_n_0:154," &
        "pci_gnt_n_1:156," &
        "pci_gnt_n_2:158," &
        "pci_irdy_n:127," &
        "pci_lock_n:123," &
        "pci_par:118," &
        "pci_perr_n:122," &
        "pci_req_n_0:153," &
        "pci_req_n_2:157," &
        "pci_rst_n:159," &
        "pci_serr_n:119," &
        "pci_stop_n:124," &
        "pci_trdy_n:126," &
        "sdram_245_oe_n:1," &
        "sdram_addr_12:29," &
        "sdram_bemask_n:(4, 5, 33, 34)," &
        "sdram_cas_n:3," &
        "sdram_cke:30," &
        "sdram_cs_n:(8, 9, 31, 32)," &
        "sdram_ras_n:10," &
        "sdram_s_n:(11, 12)," &
        "sdram_we_n:2," &
        "spi_miso:187," &
        "spi_mosi:188," &
        "spi_sck:186," &
        "spi_ss_n:185," &
        "test_cronus_mode_n:184," &
        "test_rhea_mode_n:181," &
        "uart_rx_0:208," &
        "uart_tx_0:207," &
        "vcccore:(27, 62, 82, 131, 183)," &
        "vccp:77," &
        "vccio:(7, 17, 37, 47, 59, 69, 89, 99, 111, 121," & 
               "141, 151, 163, 173, 193, 203)," &
        "vss:(6, 16, 26, 36, 46, 58, 68, 81, 88, 98," &
             "110, 120, 130, 140, 150, 162, 172, 182, 192, 202)," &
        "vssp:78";

    attribute TAP_SCAN_CLOCK of jtag_tck : signal is (1.0e7, BOTH);
    attribute TAP_SCAN_IN of jtag_tdi : signal is true;
    attribute TAP_SCAN_MODE of jtag_tms : signal is true;
    attribute TAP_SCAN_OUT of jtag_tdo : signal is true;
    attribute TAP_SCAN_RESET of jtag_trst_n : signal is true;

    attribute INSTRUCTION_LENGTH of idt79rc32t332 : entity is 4;

    attribute INSTRUCTION_OPCODE of idt79rc32t332 : entity is
        "EXTEST          (0000)," &
        "SAMPLE          (0001)," &
        "IDCODE          (0010)," &
        "HIGHZ           (0011)," &
        "CLAMP           (1000)," &
        "BYPASS          (1111)";

    attribute INSTRUCTION_CAPTURE of idt79rc32t332 : entity is "1101";

    attribute IDCODE_REGISTER of idt79rc32t332 : entity is
        "0010" &                -- version
        "0000000000011010" &    -- part number
        "00000110011" &         -- manufacturer's identity
        "1";                    -- required by 1149.1

    attribute REGISTER_ACCESS of idt79rc32t332 : entity is
        "Bypass          (BYPASS, CLAMP, HIGHZ)," &
        "Boundary        (SAMPLE, EXTEST)";

    attribute BOUNDARY_LENGTH of idt79rc32t332 : entity is 303;

    attribute BOUNDARY_REGISTER of idt79rc32t332 : entity is
     --
     -- num   cell   port		   function   safe [ccell disval rslt]
        "302 (BC_0,  sdram_245_oe_n,	   output3,   1, 301, 0, Z)," &
        "301 (BC_0,  *,			   control,   0)," &
        "300 (BC_0,  sdram_we_n,	   output3,   1, 299, 0, Z)," &
        "299 (BC_0,  *,			   control,   0)," &
        "298 (BC_0,  sdram_cas_n,	   output3,   1, 297, 0, Z)," &
        "297 (BC_0,  *,			   control,   0)," &
        "296 (BC_0,  sdram_bemask_n(0),	   output3,   1, 295, 0, Z)," &
        "295 (BC_0,  *,			   control,   0)," &
        "294 (BC_0,  sdram_bemask_n(1),	   output3,   1, 293, 0, Z)," &
        "293 (BC_0,  *,			   control,   0)," &
        "292 (BC_0,  sdram_cs_n(0),	   output3,   1, 291, 0, Z)," &
        "291 (BC_0,  *,			   control,   0)," &
        "290 (BC_0,  sdram_cs_n(1),	   output3,   1, 289, 0, Z)," &
        "289 (BC_0,  *,			   control,   0)," &
        "288 (BC_0,  sdram_ras_n,	   output3,   1, 287, 0, Z)," &
        "287 (BC_0,  *,			   control,   0)," &
        "286 (BC_0,  sdram_s_n(0),	   output3,   1, 285, 0, Z)," &
        "285 (BC_0,  *,			   control,   0)," &
        "284 (BC_0,  sdram_s_n(1),	   output3,   1, 283, 0, Z)," &
        "283 (BC_0,  *,			   control,   0)," &
        "282 (BC_0,  mem_addr_lsb(2),	   output3,   1, 281, 0, Z)," &
        "281 (BC_0,  *,			   control,   0)," &
        "280 (BC_0,  mem_addr_lsb(3),	   output3,   1, 279, 0, Z)," &
        "279 (BC_0,  *,			   control,   0)," &
        "278 (BC_0,  mem_addr_mid(4),	   bidir,     1, 277, 0, Z)," &
        "277 (BC_0,  *,			   control,   0)," &
        "276 (BC_0,  mem_addr_mid(5),	   bidir,     1, 275, 0, Z)," &
        "275 (BC_0,  *,			   control,   0)," &
        "274 (BC_0,  mem_addr_mid(6),	   bidir,     1, 273, 0, Z)," &
        "273 (BC_0,  *,			   control,   0)," &
        "272 (BC_0,  mem_addr_mid(7),	   bidir,     1, 271, 0, Z)," &
        "271 (BC_0,  *,			   control,   0)," &
        "270 (BC_0,  mem_addr_mid(8),	   bidir,     1, 269, 0, Z)," &
        "269 (BC_0,  *,			   control,   0)," &
        "268 (BC_0,  mem_addr_mid(9),	   bidir,     1, 267, 0, Z)," &
        "267 (BC_0,  *,			   control,   0)," &
        "266 (BC_0,  mem_addr_mid(10),	   bidir,     1, 265, 0, Z)," &
        "265 (BC_0,  *,			   control,   0)," &
        "264 (BC_0,  mem_addr_mid(11),	   bidir,     1, 263, 0, Z)," &
        "263 (BC_0,  *,			   control,   0)," &
        "262 (BC_0,  output_clk,           output3,   1, 261, 0, Z)," &
        "261 (BC_0,  *,			   control,   0)," &
        "260 (BC_0,  mem_addr_mid(12),	   bidir,     1, 259, 0, Z)," &
        "259 (BC_0,  *,			   control,   0)," &
        "258 (BC_0,  sdram_addr_12,	   bidir,     1, 257, 0, Z)," &
        "257 (BC_0,  *,			   control,   0)," &
        "256 (BC_0,  sdram_cke,		   output3,   1, 255, 0, Z)," &
        "255 (BC_0,  *,			   control,   0)," &
        "254 (BC_0,  sdram_cs_n(2),	   output3,   1, 253, 0, Z)," &
        "253 (BC_0,  *,			   control,   0)," &
        "252 (BC_0,  sdram_cs_n(3),	   output3,   1, 251, 0, Z)," &
        "251 (BC_0,  *,			   control,   0)," &
        "250 (BC_0,  sdram_bemask_n(2),	   output3,   1, 249, 0, Z)," &
        "249 (BC_0,  *,			   control,   0)," &
        "248 (BC_0,  sdram_bemask_n(3),	   output3,   1, 247, 0, Z)," &
        "247 (BC_0,  *,			   control,   0)," &
        "246 (BC_0,  mem_addr_mid(13),	   bidir,     1, 245, 0, Z)," &
        "245 (BC_0,  *,			   control,   0)," &
        "244 (BC_0,  mem_addr_mid(14),	   bidir,     1, 243, 0, Z)," &
        "243 (BC_0,  *,			   control,   0)," &
        "242 (BC_0,  mem_addr_mid(15),	   bidir,     1, 241, 0, Z)," &
        "241 (BC_0,  *,			   control,   0)," &
        "240 (BC_0,  mem_addr_mid(16),	   bidir,     1, 239, 0, Z)," &
        "239 (BC_0,  *,			   control,   0)," &
        "238 (BC_0,  mem_addr_mid(17),	   bidir,     1, 237, 0, Z)," &
        "237 (BC_0,  *,			   control,   0)," &
        "236 (BC_0,  mem_addr_mid(18),	   bidir,     1, 235, 0, Z)," &
        "235 (BC_0,  *,			   control,   0)," &
        "234 (BC_0,  mem_addr_mid(19),	   bidir,     1, 233, 0, Z)," &
        "233 (BC_0,  *,			   control,   0)," &
        "232 (BC_0,  mem_addr_mid(20),	   bidir,     1, 231, 0, Z)," &
        "231 (BC_0,  *,			   control,   0)," &
        "230 (BC_0,  mem_addr_mid(21),	   bidir,     1, 229, 0, Z)," &
        "229 (BC_0,  *,			   control,   0)," &
        "228 (BC_0,  mem_addr_mid(22),	   bidir,     1, 227, 0, Z)," &
        "227 (BC_0,  *,			   control,   0)," &
        "226 (BC_0,  mem_data(10),	   bidir,     1, 225, 0, Z)," &
        "225 (BC_0,  *,			   control,   0)," &
        "224 (BC_0,  mem_data(11),	   bidir,     1, 223, 0, Z)," &
        "223 (BC_0,  *,			   control,   0)," &
        "222 (BC_0,  mem_data(20),	   bidir,     1, 221, 0, Z)," &
        "221 (BC_0,  *,			   control,   0)," &
        "220 (BC_0,  cpu_coldreset_n,	   input,     1)," &
        "219 (BC_0,  mem_data(12),	   bidir,     1, 218, 0, Z)," &
        "218 (BC_0,  *,			   control,   0)," &
        "217 (BC_0,  mem_data(19),	   bidir,     1, 216, 0, Z)," &
        "216 (BC_0,  *,			   control,   0)," &
        "215 (BC_0,  mem_data(13),	   bidir,     1, 214, 0, Z)," &
        "214 (BC_0,  *,			   control,   0)," &
        "213 (BC_0,  mem_data(18),	   bidir,     1, 212, 0, Z)," &
        "212 (BC_0,  *,			   control,   0)," &
        "211 (BC_0,  mem_data(14),	   bidir,     1, 210, 0, Z)," &
        "210 (BC_0,  *,			   control,   0)," &
        "209 (BC_0,  mem_data(17),	   bidir,     1, 208, 0, Z)," &
        "208 (BC_0,  *,			   control,   0)," &
        "207 (BC_0,  mem_data(16),	   bidir,     1, 206, 0, Z)," &
        "206 (BC_0,  *,			   control,   0)," &
        "205 (BC_0,  mem_data(15),	   bidir,     1, 204, 0, Z)," &
        "204 (BC_0,  *,			   control,   0)," &
        "203 (BC_0,  cpu_masterclk,	   input,     1)," &
        "202 (BC_0,  mem_data(31),	   bidir,     1, 201, 0, Z)," &
        "201 (BC_0,  *,			   control,   0)," &
        "200 (BC_0,  mem_data(0),	   bidir,     1, 199, 0, Z)," &
        "199 (BC_0,  *,			   control,   0)," &
        "198 (BC_0,  mem_data(30),	   bidir,     1, 197, 0, Z)," &
        "197 (BC_0,  *,			   control,   0)," &
        "196 (BC_0,  mem_data(1),	   bidir,     1, 195, 0, Z)," &
        "195 (BC_0,  *,			   control,   0)," &
        "194 (BC_0,  mem_data(29),	   bidir,     1, 193, 0, Z)," &
        "193 (BC_0,  *,			   control,   0)," &
        "192 (BC_0,  mem_data(2),	   bidir,     1, 191, 0, Z)," &
        "191 (BC_0,  *,			   control,   0)," &
        "190 (BC_0,  mem_data(28),	   bidir,     1, 189, 0, Z)," &
        "189 (BC_0,  *,			   control,   0)," &
        "188 (BC_0,  mem_data(3),	   bidir,     1, 187, 0, Z)," &
        "187 (BC_0,  *,			   control,   0)," &
        "186 (BC_0,  mem_data(27),	   bidir,     1, 185, 0, Z)," &
        "185 (BC_0,  *,			   control,   0)," &
        "184 (BC_0,  mem_data(4),	   bidir,     1, 183, 0, Z)," &
        "183 (BC_0,  *,			   control,   0)," &
        "182 (BC_0,  mem_data(26),	   bidir,     1, 181, 0, Z)," &
        "181 (BC_0,  *,			   control,   0)," &
        "180 (BC_0,  mem_data(5),	   bidir,     1, 179, 0, Z)," &
        "179 (BC_0,  *,			   control,   0)," &
        "178 (BC_0,  cpu_dt_r_n,	   bidir,     1, 177, 0, Z)," &
        "177 (BC_0,  *,			   control,   0)," &
        "176 (BC_0,  mem_data(25),	   bidir,     1, 175, 0, Z)," &
        "175 (BC_0,  *,			   control,   0)," &
        "174 (BC_0,  mem_data(6),	   bidir,     1, 173, 0, Z)," &
        "173 (BC_0,  *,			   control,   0)," &
        "172 (BC_0,  mem_data(24),	   bidir,     1, 171, 0, Z)," &
        "171 (BC_0,  *,			   control,   0)," &
        "170 (BC_0,  mem_data(7),	   bidir,     1, 169, 0, Z)," &
        "169 (BC_0,  *,			   control,   0)," &
        "168 (BC_0,  mem_data(23),	   bidir,     1, 167, 0, Z)," &
        "167 (BC_0,  *,			   control,   0)," &
        "166 (BC_0,  mem_data(8),	   bidir,     1, 165, 0, Z)," &
        "165 (BC_0,  *,			   control,   0)," &
        "164 (BC_0,  mem_data(22),	   bidir,     1, 163, 0, Z)," &
        "163 (BC_0,  *,			   control,   0)," &
        "162 (BC_0,  mem_data(9),	   bidir,     1, 161, 0, Z)," &
        "161 (BC_0,  *,			   control,   0)," &
        "160 (BC_0,  mem_data(21),	   bidir,     1, 159, 0, Z)," &
        "159 (BC_0,  *,			   control,   0)," &
        "158 (BC_0,  cpu_nmi_n,		   input,     1)," &
        "157 (BC_0,  pci_ad(0),		   bidir,     1, 156, 0, Z)," &
        "156 (BC_0,  *,			   control,   0)," &
        "155 (BC_0,  pci_ad(1),		   bidir,     1, 154, 0, Z)," &
        "154 (BC_0,  *,			   control,   0)," &
        "153 (BC_0,  pci_ad(2),		   bidir,     1, 152, 0, Z)," &
        "152 (BC_0,  *,			   control,   0)," &
        "151 (BC_0,  pci_ad(3),		   bidir,     1, 150, 0, Z)," &
        "150 (BC_0,  *,			   control,   0)," &
        "149 (BC_0,  pci_ad(4),		   bidir,     1, 148, 0, Z)," &
        "148 (BC_0,  *,			   control,   0)," &
        "147 (BC_0,  pci_ad(5),		   bidir,     1, 146, 0, Z)," &
        "146 (BC_0,  *,			   control,   0)," &
        "145 (BC_0,  pci_ad(6),		   bidir,     1, 144, 0, Z)," &
        "144 (BC_0,  *,			   control,   0)," &
        "143 (BC_0,  pci_ad(7),		   bidir,     1, 142, 0, Z)," &
        "142 (BC_0,  *,			   control,   0)," &
        "141 (BC_0,  pci_cbe_n(0),	   bidir,     1, 140, 0, Z)," &
        "140 (BC_0,  *,			   control,   0)," &
        "139 (BC_0,  pci_ad(8),		   bidir,     1, 138, 0, Z)," &
        "138 (BC_0,  *,			   control,   0)," &
        "137 (BC_0,  pci_ad(9),		   bidir,     1, 136, 0, Z)," &
        "136 (BC_0,  *,			   control,   0)," &
        "135 (BC_0,  pci_ad(10),	   bidir,     1, 134, 0, Z)," &
        "134 (BC_0,  *,			   control,   0)," &
        "133 (BC_0,  pci_ad(11),	   bidir,     1, 132, 0, Z)," &
        "132 (BC_0,  *,			   control,   0)," &
        "131 (BC_0,  pci_ad(12),	   bidir,     1, 130, 0, Z)," &
        "130 (BC_0,  *,			   control,   0)," &
        "129 (BC_0,  pci_ad(13),	   bidir,     1, 128, 0, Z)," &
        "128 (BC_0,  *,			   control,   0)," &
        "127 (BC_0,  pci_ad(14),	   bidir,     1, 126, 0, Z)," &
        "126 (BC_0,  *,			   control,   0)," &
        "125 (BC_0,  pci_ad(15),	   bidir,     1, 124, 0, Z)," &
        "124 (BC_0,  *,			   control,   0)," &
        "123 (BC_0,  pci_cbe_n(1),	   bidir,     1, 122, 0, Z)," &
        "122 (BC_0,  *,			   control,   0)," &
        "121 (BC_0,  pci_par,		   bidir,     1, 120, 0, Z)," &
        "120 (BC_0,  *,			   control,   0)," &
        "119 (BC_0,  pci_serr_n,	   bidir,     1, 118, 0, Z)," &
        "118 (BC_0,  *,			   control,   0)," &
        "117 (BC_0,  pci_perr_n,	   bidir,     1, 116, 0, Z)," &
        "116 (BC_0,  *,			   control,   0)," &
        "115 (BC_0,  pci_lock_n,	   input,     1)," &
        "114 (BC_0,  pci_stop_n,	   bidir,     1, 113, 0, Z)," &
        "113 (BC_0,  *,			   control,   0)," &
        "112 (BC_0,  pci_devsel_n,	   bidir,     1, 111, 0, Z)," &
        "111 (BC_0,  *,			   control,   0)," &
        "110 (BC_0,  pci_trdy_n,	   bidir,     1, 109, 0, Z)," &
        "109 (BC_0,  *,			   control,   0)," &
        "108 (BC_0,  pci_irdy_n,	   bidir,     1, 107, 0, Z)," &
        "107 (BC_0,  *,			   control,   0)," &
        "106 (BC_0,  pci_frame_n,	   bidir,     1, 105, 0, Z)," &
        "105 (BC_0,  *,			   control,   0)," &
        "104 (BC_0,  pci_cbe_n(2),	   bidir,     1, 103, 0, Z)," &
        "103 (BC_0,  *,			   control,   0)," &
        "102 (BC_0,  pci_ad(16),	   bidir,     1, 101, 0, Z)," &
        "101 (BC_0,  *,			   control,   0)," &
        "100 (BC_0,  pci_ad(17),	   bidir,     1,  99, 0, Z)," &
        "99  (BC_0,  *,			   control,   0)," &
        "98  (BC_0,  pci_ad(18),	   bidir,     1,  97, 0, Z)," &
        "97  (BC_0,  *,			   control,   0)," &
        "96  (BC_0,  pci_ad(19),	   bidir,     1,  95, 0, Z)," &
        "95  (BC_0,  *,			   control,   0)," &
        "94  (BC_0,  pci_ad(20),	   bidir,     1,  93, 0, Z)," &
        "93  (BC_0,  *,			   control,   0)," &
        "92  (BC_0,  pci_ad(21),	   bidir,     1,  91, 0, Z)," &
        "91  (BC_0,  *,			   control,   0)," &
        "90  (BC_0,  pci_ad(22),	   bidir,     1,  89, 0, Z)," &
        "89  (BC_0,  *,			   control,   0)," &
        "88  (BC_0,  pci_ad(23),	   bidir,     1,  87, 0, Z)," &
        "87  (BC_0,  *,			   control,   0)," &
        "86  (BC_0,  pci_cbe_n(3),	   bidir,     1,  85, 0, Z)," &
        "85  (BC_0,  *,			   control,   0)," &
        "84  (BC_0,  pci_ad(24),	   bidir,     1,  83, 0, Z)," &
        "83  (BC_0,  *,			   control,   0)," &
        "82  (BC_0,  pci_ad(25),	   bidir,     1,  81, 0, Z)," &
        "81  (BC_0,  *,			   control,   0)," &
        "80  (BC_0,  pci_ad(26),	   bidir,     1,  79, 0, Z)," &
        "79  (BC_0,  *,			   control,   0)," &
        "78  (BC_0,  pci_ad(27),	   bidir,     1,  77, 0, Z)," &
        "77  (BC_0,  *,			   control,   0)," &
        "76  (BC_0,  pci_ad(28),	   bidir,     1,  75, 0, Z)," &
        "75  (BC_0,  *,			   control,   0)," &
        "74  (BC_0,  pci_ad(29),	   bidir,     1,  73, 0, Z)," &
        "73  (BC_0,  *,			   control,   0)," &
        "72  (BC_0,  pci_ad(30),	   bidir,     1,  71, 0, Z)," &
        "71  (BC_0,  *,			   control,   0)," &
        "70  (BC_0,  pci_ad(31),	   bidir,     1,  69, 0, Z)," &
        "69  (BC_0,  *,			   control,   0)," &
        "68  (BC_0,  pci_req_n_0,	   bidir,     1,  67, 0, Z)," &
        "67  (BC_0,  *,			   control,   0)," &
        "66  (BC_0,  pci_gnt_n_0,	   bidir,     1,  65, 0, Z)," &
        "65  (BC_0,  *,			   control,   0)," &
        "64  (BC_0,  pci_clk,		   input,     1)," &
        "63  (BC_0,  pci_gnt_n_1,	   bidir,     1,  62, 0, Z)," &
        "62  (BC_0,  *,			   control,   0)," &
        "61  (BC_0,  pci_gnt_n_2,	   output3,   1,  60, 0, Z)," &
        "60  (BC_0,  *,			   control,   0)," &
        "59  (BC_0,  pci_req_n_2,	   input,     1)," &
        "58  (BC_0,  pci_rst_n,		   input,     1)," &
        "57  (BC_0,  cpu_int_n_0,	   input,     1)," &
        "56  (BC_0,  cpu_int_n_1,	   input,     1)," &
        "55  (BC_0,  ejtag_pcst(0),	   bidir,     1,  54, 0, Z)," &
        "54  (BC_0,  *,			   control,   0)," &
        "53  (BC_0,  ejtag_pcst(1),	   bidir,     1,  52, 0, Z)," &
        "52  (BC_0,  *,			   control,   0)," &
        "51  (BC_0,  ejtag_pcst(2),	   bidir,     1,  50, 0, Z)," &
        "50  (BC_0,  *,			   control,   0)," &
        "49  (BC_0,  ejtag_dclk,	   output3,   1,  48, 0, Z)," &
        "48  (BC_0,  *,			   control,   0)," &
        "47  (BC_0,  ejtag_debugboot,	   input,     0)," &
        "46  (BC_0,  debug_cpu_i_d_n,	   bidir,     1,  45, 0, Z)," &
        "45  (BC_0,  *,			   control,   0)," &
        "44  (BC_0,  debug_cpu_ads_n,	   bidir,     1,  43, 0, Z)," &
        "43  (BC_0,  *,			   control,   0)," &
        "42  (BC_0,  debug_cpu_ack_n,	   bidir,     1,  41, 0, Z)," &
        "41  (BC_0,  *,			   control,   0)," &
        "40  (BC_0,  debug_cpu_dma_n,	   bidir,     1,  39, 0, Z)," &
        "39  (BC_0,  *,			   control,   0)," &
        "38  (BC_0,  spi_ss_n,		   bidir,     1,  37, 0, Z)," &
        "37  (BC_0,  *,			   control,   0)," &
        "36  (BC_0,  spi_sck,		   bidir,     1,  35, 0, Z)," &
        "35  (BC_0,  *,			   control,   0)," &
        "34  (BC_0,  spi_miso,		   bidir,     1,  33, 0, Z)," &
        "33  (BC_0,  *,			   control,   0)," &
        "32  (BC_0,  spi_mosi,		   bidir,     1,  31, 0, Z)," &
        "31  (BC_0,  *,			   control,   0)," &
        "30  (BC_0,  dma_ready_n_0,	   bidir,     1,  29, 0, Z)," &
        "29  (BC_0,  *,			   control,   0)," &
        "28  (BC_0,  mem_245_oe_n,	   bidir,     1,  27, 0, Z)," &
        "27  (BC_0,  *,			   control,   0)," &
        "26  (BC_0,  mem_wait_n,	   input,     1)," &
        "25  (BC_0,  mem_oe_n,		   bidir,     1,  24, 0, Z)," &
        "24  (BC_0,  *,			   control,   0)," &
        "23  (BC_0,  mem_cs_n(0),	   output3,   1,  22, 0, Z)," &
        "22  (BC_0,  *,			   control,   0)," &
        "21  (BC_0,  mem_cs_n(1),	   output3,   1,  20, 0, Z)," &
        "20  (BC_0,  *,			   control,   0)," &
        "19  (BC_0,  mem_cs_n(2),	   output3,   1,  18, 0, Z)," &
        "18  (BC_0,  *,			   control,   0)," &
        "17  (BC_0,  mem_cs_n(3),	   output3,   1,  16, 0, Z)," &
        "16  (BC_0,  *,			   control,   0)," &
        "15  (BC_0,  mem_cs_n(4),	   output3,   1,  14, 0, Z)," &
        "14  (BC_0,  *,			   control,   0)," &
        "13  (BC_0,  mem_cs_n(5),	   output3,   1,  12, 0, Z)," &
        "12  (BC_0,  *,			   control,   0)," &
        "11  (BC_0,  mem_we_n(0),	   output3,   1,  10, 0, Z)," &
        "10  (BC_0,  *,			   control,   0)," &
        "9   (BC_0,  mem_we_n(1),	   output3,   1,   8, 0, Z)," &
        "8   (BC_0,  *,			   control,   0)," &
        "7   (BC_0,  mem_we_n(2),	   output3,   1,   6, 0, Z)," &
        "6   (BC_0,  *,			   control,   0)," &
        "5   (BC_0,  mem_we_n(3),	   output3,   1,   4, 0, Z)," &
        "4   (BC_0,  *,			   control,   0)," &
        "3   (BC_0,  uart_tx_0,		   bidir,     1,   2, 0, Z)," &
        "2   (BC_0,  *,			   control,   0)," &
        "1   (BC_0,  uart_rx_0,	  	   bidir,     1,   0, 0, Z)," &
        "0   (BC_0,  *,			   control,   0)";

end idt79rc32t332;