--$ XILINX$RCSfile: xc18v512_so20.bsd,v $
--$ XILINX$Revision: 1.4 $
--
-- BSDL file for device XC18V512_SO20, package SO20
-- Xilinx, Inc. $State: ADVANCED $ $Date: 2003-06-02 15:39:57-07 $
--
-- For technical support, find answers or contact information at:
-- http://www.support.xilinx.com
--
-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect
-- the post-configuration JTAG behavior (if any), edit this file as described
-- below:
--
-- 1. Rename entity if necessary to avoid name collisions.
-- 2. Modify USERCODE value in USERCODE_REGISTER declaration.
-- 3. Set safe state of boundary cells as necessary.
entity XC18V512_SO20 is
generic (PHYSICAL_PIN_MAP : string := "SO20" );
port (
TDI: in bit;
TMS: in bit;
TCK: in bit;
D4_CF: out bit;
Reset_OE: inout bit;
D6: out bit;
CE: in bit;
Gnd_3: linkage bit;
D7: out bit;
CEO: out bit;
D5: out bit;
D3: out bit;
D1: out bit;
TDO: out bit;
Vpp: linkage bit;
Vcco_4: linkage bit;
Vcc_2: linkage bit;
D0: out bit;
D2: out bit;
CLK: in bit
); --end port list
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of XC18V512_SO20 : entity is
"STD_1149_1_1993";
attribute PIN_MAP of XC18V512_SO20 : entity is PHYSICAL_PIN_MAP;
constant SO20: PIN_MAP_STRING:=
"TDI:4," &
"TMS:5," &
"TCK:6," &
"D4_CF:7," &
"Reset_OE:8," &
"D6:9," &
"CE:10," &
"Gnd_3:11," &
"D7:12," &
"CEO:13," &
"D5:14," &
"D3:15," &
"D1:16," &
"TDO:17," &
"Vpp:18," &
"Vcco_4:19," &
"Vcc_2:20," &
"D0:1," &
"D2:2," &
"CLK:3";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (1.00e+07, BOTH);
attribute INSTRUCTION_LENGTH of XC18V512_SO20 : entity is 8;
attribute INSTRUCTION_OPCODE of XC18V512_SO20 : entity is
"BYPASS ( 11111111)," &
"SAMPLE ( 00000001)," &
"EXTEST ( 00000000)," &
"IDCODE ( 11111110)," &
"USERCODE ( 11111101)," &
"HIGHZ ( 11111100)," &
"CLAMP ( 11111010)," &
"ISPEN ( 11101000)," &
"ISPENC ( 11101001)," &
"FPGM ( 11101010)," &
"FADDR ( 11101011)," &
"FVFY0 ( 11101111)," &
"FVFY1 ( 11111000)," &
"FVFY3 ( 11100010)," &
"FVFY6 ( 11100110)," &
"FERASE ( 11101100)," &
"SERASE ( 00001010)," &
"FDATA0 ( 11101101)," &
"FDATA3 ( 11110011)," &
"FBLANK0 ( 11100101)," &
"FBLANK3 ( 11100001)," &
"FBLANK6 ( 11100100)," &
"NORMRST ( 11110000)," &
"CONFIG ( 11101110)," &
"priv1 ( 11110001)," &
"ISCTESTSTATUS ( 11100011)," &
"priv3 ( 11100111)," &
"priv4 ( 11110110)," &
"priv5 ( 11100000)," &
"priv6 ( 11110111)," &
"priv7 ( 11110010)," &
"ISCCLRSTATUS ( 11110100)," &
"priv9 ( 11110101)";
attribute INSTRUCTION_CAPTURE of XC18V512_SO20: entity is "XXXXXX01";
attribute INSTRUCTION_PRIVATE of XC18V512_SO20: entity is
"priv1," &
"ISCTESTSTATUS," &
"priv3," &
"priv4," &
"priv5," &
"priv6," &
"priv7," &
"ISCCLRSTATUS," &
"priv9";
attribute IDCODE_REGISTER of XC18V512_SO20: entity is
"XXXX" & -- version
"01010000001X0011" & -- part number
"00001001001" & -- manufacturer's id
"1"; -- required by standard
attribute USERCODE_REGISTER of XC18V512_SO20: entity is
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
attribute REGISTER_ACCESS of XC18V512_SO20 : entity is
"BYPASS ( BYPASS, HIGHZ, CLAMP, FPGM, NORMRST, CONFIG )," &
"ISPENABLE[6] ( ISPEN, ISPENC )," &
"DATA0[2048] ( FVFY0, FDATA0 ),"&
"DATA1[524288] ( FVFY1, FBLANK0 ),"&
"DATA3[6] ( FVFY3, FDATA3, FBLANK3 ),"&
"ADDRESS[16] ( FADDR, FERASE, SERASE ),"&
"DEVICE_ID ( IDCODE, USERCODE ),"&
"USERCODEV[32] ( FVFY6, FBLANK6 )";
-- Readback image of the USERCODE register contents
attribute BOUNDARY_LENGTH of XC18V512_SO20 : entity is 25;
attribute BOUNDARY_REGISTER of XC18V512_SO20 : entity is
" 0 (BC_1, CLK, input, X)," &
" 1 (BC_1, *, controlr, 0)," &
" 2 (BC_1, D2, output3, X, 1, 0, Z)," &
" 3 (BC_1, *, controlr, 0)," &
" 4 (BC_1, D0, output3, X, 3, 0, Z)," &
" 5 (BC_1, *, controlr, 0)," &
" 6 (BC_1, D1, output3, X, 5, 0, Z)," &
" 7 (BC_1, *, controlr, 0)," &
" 8 (BC_1, D3, output3, X, 7, 0, Z)," &
" 9 (BC_1, *, controlr, 0)," &
" 10 (BC_1, D5, output3, X, 9, 0, Z)," &
" 11 (BC_1, *, controlr, 0)," &
" 12 (BC_1, CEO, output3, X, 11, 0, Z)," &
" 13 (BC_1, *, controlr, 0)," &
" 14 (BC_1, D7, output3, X, 13, 0, Z)," &
" 15 (BC_1, CE, input, X)," &
" 16 (BC_1, *, controlr, 0)," &
" 17 (BC_1, D6, output3, X, 16, 0, Z)," &
" 18 (BC_1, *, controlr, 0)," &
" 19 (BC_1, Reset_OE, output3, X, 18, 0, Z)," &
" 20 (BC_1, Reset_OE, input, X)," &
" 21 (BC_1, *, internal, X)," &
" 22 (BC_1, *, internal, X)," &
" 23 (BC_1, *, controlr, 0)," &
" 24 (BC_1, D4_CF, output3, X, 23, 0, Z)";
attribute DESIGN_WARNING of XC18V512_SO20 : entity is
"The BOUNDARY_REGISTER input and control cell SAMPLE values are inverted " &
"in devices with IDCODE_REGISTER==00000101000000100011000010010011." &
"Pin 20 is a no connect, i.e. the Vcc_2 port is not bonded to pin 20, " &
"in devices with IDCODE_REGISTER==00000101000000110011000010010011.";
end XC18V512_SO20;