BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: S32R274

-- *****************************************************************************
--    BSDL file for design   --> S32R274
--    Company  --> Freescale Semiconductor
--    Designer --> b49034
--    BSDL file generated on --> 07-Sep-2015
--    Tool --> BSDL_GEN, Version 5.0
-- *****************************************************************************


 entity S32R274 is

   generic (PHYSICAL_PIN_MAP: string:= "BGA_257");

-- This section declares all the ports in the design.

   port (
           RESET_B			:		linkage		  bit;
           TCK			:		in		  bit;
           PB_4			:		out		  bit;
           TMS			:		in		  bit;
           PB_5			:		in		  bit;
           JCOMP			:		linkage		  bit;
           PA_0			:		inout		  bit;
           PA_1			:		inout		  bit;
           PA_2			:		inout		  bit;
           PA_3			:		inout		  bit;
           PA_4			:		inout		  bit;
           PA_5			:		inout		  bit;
           PA_6			:		inout		  bit;
           PA_7			:		inout		  bit;
           PA_8			:		inout		  bit;
           PA_9			:		inout		  bit;
           PA_10			:		inout		  bit;
           PA_11			:		inout		  bit;
           PA_12			:		inout		  bit;
           PA_13			:		inout		  bit;
           PA_14			:		inout		  bit;
           PA_15			:		inout		  bit;
           PB_0			:		inout		  bit;
           PB_1			:		inout		  bit;
           PB_2			:		inout		  bit;
           PB_3			:		inout		  bit;
           PB_6			:		inout		  bit;
           PC_10			:		inout		  bit;
           PC_11			:		inout		  bit;
           PC_12			:		inout		  bit;
           PD_8			:		inout		  bit;
           PD_11			:		inout		  bit;
           PD_14			:		inout		  bit;
           PE_13			:		inout		  bit;
           PE_15			:		inout		  bit;
           PF_0			:		inout		  bit;
           PF_14			:		inout		  bit;
           PF_15			:		inout		  bit;
           PG_5			:		inout		  bit;
           PG_8			:		inout		  bit;
           PG_9			:		inout		  bit;
           PH_6			:		inout		  bit;
           PH_7			:		inout		  bit;
           PH_11			:		inout		  bit;
           PH_12			:		inout		  bit;
           PI_0			:		inout		  bit;
           PI_1			:		inout		  bit;
           PI_4			:		inout		  bit;
           PI_5			:		inout		  bit;
           PI_6			:		inout		  bit;
           PI_7			:		inout		  bit;
           PI_8			:		inout		  bit;
           PI_9			:		inout		  bit;
           NMI			:		inout		  bit;
           FCCU_F0			:		inout		  bit;
           FCCU_F1			:		inout		  bit;
           PC_15			:		inout		  bit;
           PD_0			:		inout		  bit;
           PD_1			:		inout		  bit;
           PD_2			:		inout		  bit;
           PD_3			:		inout		  bit;
           PD_4			:		inout		  bit;
           PD_5			:		inout		  bit;
           PD_6			:		inout		  bit;
           PG_10			:		inout		  bit;
           PG_11			:		inout		  bit;
           PH_4			:		inout		  bit;
           PH_5			:		inout		  bit;
           PH_8			:		inout		  bit;
           PH_9			:		inout		  bit;
           PH_13			:		inout		  bit;
           PI_2			:		inout		  bit;
           PB_7			:		in		  bit;
           PB_8			:		in		  bit;
           PC_1			:		in		  bit;
           PC_2			:		in		  bit;
           PE_6			:		in		  bit;
           PE_2			:		in		  bit;
           PE_7			:		in		  bit;
           PE_4			:		in		  bit;
           PE_5			:		in		  bit;
           PB_13			:		in		  bit;
           PB_14			:		in		  bit;
           PB_15			:		in		  bit;
           PC_0			:		in		  bit;
           PB_9		:		in		  bit;
           PB_10		:		in		  bit;
           PB_11		:		in		  bit;
           PB_12		:		in		  bit;
           AFE_FILTER			:		linkage		  bit;
           MTI_N0			:		linkage		  bit;
           MTI_N1			:		linkage		  bit;
           MTI_N2			:		linkage		  bit;
           MTI_N3			:		linkage		  bit;
           MTI_P0			:		linkage		  bit;
           MTI_P1			:		linkage		  bit;
           MTI_P2			:		linkage		  bit;
           MTI_P3			:		linkage		  bit;
           VDD			:		linkage		  bit_vector(24 downto 0);
           VSS			:		linkage		  bit_vector(23 downto 0);
           VDD_HV_IO			:		linkage		  bit_vector(4 downto 0);
           VSS_HV_IO			:		linkage		  bit_vector(6 downto 0);
           SD_0_ADCN			:		linkage		  bit;
           SD_0_ADCP			:		linkage		  bit;
           SD_CM			:		linkage		  bit;
           VDD_HV_RAW			:		linkage		  bit;
           XOSC_XTAL			:		linkage		  bit_vector(1 downto 0);
           VDD_HV_ADCREF1			:		linkage		  bit;
           VSS_HV_ADC			:		linkage		  bit_vector(2 downto 0);
           SD_1_ADCN			:		linkage		  bit;
           SD_1_ADCP			:		linkage		  bit;
           SD_R			:		linkage		  bit;
           VSS_HV_RAW			:		linkage		  bit;
           VDD_LV_SDPLL			:		linkage		  bit;
           VSS_LV_OSC			:		linkage		  bit;
           VSS_HV_ADCREF1			:		linkage		  bit;
           VDD_HV_ADCREF0			:		linkage		  bit;
           VSS_HV_ADCREF0			:		linkage		  bit;
           VSS_LV_DPHY			:		linkage		  bit_vector(3 downto 0);
           SD_2_ADCN			:		linkage		  bit;
           SD_2_ADCP			:		linkage		  bit;
           VDD_LV_RADARREF			:		linkage		  bit;
           VDD_LV_RADARDIG			:		linkage		  bit;
           VSS_LV_RADARDIG			:		linkage		  bit;
           VDD_LV_OSC			:		linkage		  bit;
           VDD_LV_SDCLK			:		linkage		  bit;
           VSS_SUB_INPWB0			:		linkage		  bit;
           VDD_LV_IO_MTI			:		linkage		  bit;
           VSS_LV_IO_MTI			:		linkage		  bit;
           VDD_HV_ADC			:		linkage		  bit_vector(1 downto 0);
           AR_CLKN_0			:		linkage		  bit;
           SD_3_ADCN			:		linkage		  bit;
           SD_3_ADCP			:		linkage		  bit;
           VSS_LV_SDADC			:		linkage		  bit;
           VDD_LV_SDADC			:		linkage		  bit;
           VSS_LV_SDPLL			:		linkage		  bit;
           VSS_LV_SDCLK			:		linkage		  bit;
           VSS_SUB_OUTPWB			:		linkage		  bit;
           VSS_LV_IO_AURORA			:		linkage		  bit_vector(1 downto 0);
           AR_TXP_0			:		linkage		  bit;
           AR_CLKP_0			:		linkage		  bit;
           CSI_LANE2N			:		linkage		  bit;
           CSI_LANE2P			:		linkage		  bit;
           DAC_C			:		linkage		  bit;
           VSS_HV_REGDAC			:		linkage		  bit;
           CSI_LANE0N			:		linkage		  bit;
           CSI_LANE0P			:		linkage		  bit;
           VDD_HV_DAC_2V5			:		linkage		  bit;
           VSS_SUB_INPWB1			:		linkage		  bit;
           CSI_CLKN			:		linkage		  bit;
           CSI_CLKP			:		linkage		  bit;
           DAC_AP			:		linkage		  bit;
           VSS_HV_DAC			:		linkage		  bit;
           CSI_LANE1N			:		linkage		  bit;
           CSI_LANE1P			:		linkage		  bit;
           DAC_AN			:		linkage		  bit;
           VDD_HV_DAC			:		linkage		  bit;
           CSI_LANE3N			:		linkage		  bit;
           CSI_LANE3P			:		linkage		  bit;
           REXT			:		linkage		  bit;
           VDD_LV_DPHY			:		linkage		  bit;
           VDD_HV_IO_PWM			:		linkage		  bit;
           VSS_HV_IO_PWM			:		linkage		  bit;
           VDD_HV_FLA			:		linkage		  bit;
           VPP0			:		linkage		  bit;
           AR_TXP_2			:		linkage		  bit;
           AR_TXN_0			:		linkage		  bit;
           AR_TXP_1			:		linkage		  bit;
           AR_TXN_1			:		linkage		  bit;
           VDD_LV_IO_AURORA			:		linkage		  bit_vector(1 downto 0);
           AR_TXN_2			:		linkage		  bit;
           AR_TXP_3			:		linkage		  bit;
           AR_TXN_3			:		linkage		  bit;
           VDD_LV_LFASTPLL			:		linkage		  bit;
           VSS_LV_LFASTPLL			:		linkage		  bit;
           VDD_HV_IO_DIGRF			:		linkage		  bit;
           LFAST_RXP			:		linkage		  bit;
           LFAST_RXN			:		linkage		  bit;
           VSS_LV_PLL0			:		linkage		  bit;
           VDD_LV_PLL0			:		linkage		  bit;
           LFAST_TXN			:		linkage		  bit;
           LFAST_TXP			:		linkage		  bit;
           VDD_HV_IO_RGMII			:		linkage		  bit;
           VREG_SEL			:		linkage		  bit;
           VREG_ISENS			:		linkage		  bit;
           VDD_HV_PMU			:		linkage		  bit;
           VSS_HV_PMU			:		linkage		  bit;
           VDD_HV_REG3V8			:		linkage		  bit;
           VREG_POR_B			:		linkage		  bit;
           VREG_SWP			:		linkage		  bit;
           VSS_HV_REG3V8			:		linkage		  bit
   );

   use STD_1149_1_2001.all;

   attribute COMPONENT_CONFORMANCE of S32R274: entity is "STD_1149_1_2001";

   attribute PIN_MAP of S32R274: entity is PHYSICAL_PIN_MAP;

-- This section specifies the pin map for each port.

     constant BGA_257: PIN_MAP_STRING :=
        "RESET_B			:	T17,"  &
        "TCK			:	H15,"  &
        "PB_4			:	K16,"  &
        "TMS			:	J15,"  &
        "PB_5			:	H14,"  &
        "JCOMP			:	G17,"  &
        "PA_0			:	A11,"  &
        "PA_1			:	B11,"  &
        "PA_2			:	A12,"  &
        "PA_3			:	B12,"  &
        "PA_4			:	G15,"  &
        "PA_5			:	F14,"  &
        "PA_6			:	H17,"  &
        "PA_7			:	A15,"  &
        "PA_8			:	D15,"  &
        "PA_9			:	L17,"  &
        "PA_10			:	C16,"  &
        "PA_11			:	F15,"  &
        "PA_12			:	B16,"  &
        "PA_13			:	D17,"  &
        "PA_14			:	M15,"  &
        "PA_15			:	L16,"  &
        "PB_0			:	L15,"  &
        "PB_1			:	M17,"  &
        "PB_2			:	K17,"  &
        "PB_3			:	D16,"  &
        "PB_6			:	J14,"  &
        "PC_10			:	D14,"  &
        "PC_11			:	A14,"  &
        "PC_12			:	B14,"  &
        "PD_8			:	B13,"  &
        "PD_11			:	A13,"  &
        "PD_14			:	C12,"  &
        "PE_13			:	B15,"  &
        "PE_15			:	C15,"  &
        "PF_0			:	B17,"  &
        "PF_14			:	F16,"  &
        "PF_15			:	J17,"  &
        "PG_5			:	K15,"  &
        "PG_8			:	C17,"  &
        "PG_9			:	C13,"  &
        "PH_6			:	J16,"  &
        "PH_7			:	R14,"  &
        "PH_11			:	C14,"  &
        "PH_12			:	D13,"  &
        "PI_0			:	D12,"  &
        "PI_1			:	H16,"  &
        "PI_4			:	U10,"  &
        "PI_5			:	M16,"  &
        "PI_6			:	E16,"  &
        "PI_7			:	U15,"  &
        "PI_8			:	E17,"  &
        "PI_9			:	G14,"  &
        "NMI			:	N16,"  &
        "FCCU_F0			:	R17,"  &
        "FCCU_F1			:	M14,"  &
        "PC_15			:	P11,"  &
        "PD_0			:	R10,"  &
        "PD_1			:	T13,"  &
        "PD_2			:	U14,"  &
        "PD_3			:	P10,"  &
        "PD_4			:	T11,"  &
        "PD_5			:	T12,"  &
        "PD_6			:	U13,"  &
        "PG_10			:	R11,"  &
        "PG_11			:	U11,"  &
        "PH_4			:	R13,"  &
        "PH_5			:	P13,"  &
        "PH_8			:	T14,"  &
        "PH_9			:	T10,"  &
        "PH_13			:	P14,"  &
        "PI_2			:	U12,"  &
        "PB_7			:	M3,"  &
        "PB_8			:	N1,"  &
        "PC_1			:	N3,"  &
        "PC_2			:	P1,"  &
        "PE_6			:	M4,"  &
        "PE_2			:	R1,"  &
        "PE_7			:	T1,"  &
        "PE_4			:	P3,"  &
        "PE_5			:	R2,"  &
        "PB_13			:	J4,"  &
        "PB_14			:	L1,"  &
        "PB_15			:	K4,"  &
        "PC_0			:	L2,"  &
        "PB_9			:	T3,"  &
        "PB_10		:	R3,"  &
        "PB_11		:	T2,"  &
        "PB_12		:	U2,"  &
        "AFE_FILTER			:	D4,"  &
        "MTI_N0			:	G1,"  &
        "MTI_N1			:	H1,"  &
        "MTI_N2			:	J1,"  &
        "MTI_N3			:	K1,"  &
        "MTI_P0			:	G2,"  &
        "MTI_P1			:	H2,"  &
        "MTI_P2			:	J2,"  &
        "MTI_P3			:	K2,"  &
        "VDD			:	(F6,F8,F10,F12,G6,G7,G8,G9,G10,G11,H6,H8,H12,K6,K10,K12,L7,L8,L9,L10,L11,M6,M8,M10,M12),"  &
        "VSS			:	(F7,F9,F11,G12,H7,H9,H10,H11,J6,J7,J8,J9,J10,J11,J12,K7,K8,K9,K11,L6,L12,M7,M9,M11),"  &
        "VDD_HV_IO			:	(A16,E15,K14,N17,U16),"  &
        "VSS_HV_IO			:	(A17,E14,L14,P8,P12,P17,U17),"  &
        "SD_0_ADCN			:	A1,"  &
        "SD_0_ADCP			:	B1,"  &
        "SD_CM			:	C1,"  &
        "VDD_HV_RAW			:	D1,"  &
        "XOSC_XTAL			:	(E1,F1),"  &
        "VDD_HV_ADCREF1			:	M1,"  &
        "VSS_HV_ADC			:	(U1,P4,L4),"  &
        "SD_1_ADCN			:	A2,"  &
        "SD_1_ADCP			:	B2,"  &
        "SD_R			:	C2,"  &
        "VSS_HV_RAW			:	D2,"  &
        "VDD_LV_SDPLL			:	E2,"  &
        "VSS_LV_OSC			:	F2,"  &
        "VSS_HV_ADCREF1			:	M2,"  &
        "VDD_HV_ADCREF0			:	N2,"  &
        "VSS_HV_ADCREF0			:	P2,"  &
        "VSS_LV_DPHY			:	(A10,B10,C10,D10),"  &
        "SD_2_ADCN			:	A3,"  &
        "SD_2_ADCP			:	B3,"  &
        "VDD_LV_RADARREF			:	C3,"  &
        "VDD_LV_RADARDIG			:	D3,"  &
        "VSS_LV_RADARDIG			:	E3,"  &
        "VDD_LV_OSC			:	F3,"  &
        "VDD_LV_SDCLK			:	G3,"  &
        "VSS_SUB_INPWB0			:	H3,"  &
        "VDD_LV_IO_MTI			:	J3,"  &
        "VSS_LV_IO_MTI			:	K3,"  &
        "VDD_HV_ADC			:	(L3,N4),"  &
        "AR_CLKN_0			:	U3,"  &
        "SD_3_ADCN			:	A4,"  &
        "SD_3_ADCP			:	B4,"  &
        "VSS_LV_SDADC			:	C4,"  &
        "VDD_LV_SDADC			:	E4,"  &
        "VSS_LV_SDPLL			:	F4,"  &
        "VSS_LV_SDCLK			:	G4,"  &
        "VSS_SUB_OUTPWB			:	H4,"  &
        "VSS_LV_IO_AURORA			:	(R4,P7),"  &
        "AR_TXP_0			:	T4,"  &
        "AR_CLKP_0			:	U4,"  &
        "CSI_LANE2N			:	A5,"  &
        "CSI_LANE2P			:	B5,"  &
        "DAC_C			:	C5,"  &
        "VSS_HV_REGDAC			:	D5,"  &
        "CSI_LANE0N			:	A6,"  &
        "CSI_LANE0P			:	B6,"  &
        "VDD_HV_DAC_2V5			:	C6,"  &
        "VSS_SUB_INPWB1			:	D6,"  &
        "CSI_CLKN			:	A7,"  &
        "CSI_CLKP			:	B7,"  &
        "DAC_AP			:	C7,"  &
        "VSS_HV_DAC			:	D7,"  &
        "CSI_LANE1N			:	A8,"  &
        "CSI_LANE1P			:	B8,"  &
        "DAC_AN			:	C8,"  &
        "VDD_HV_DAC			:	D8,"  &
        "CSI_LANE3N			:	A9,"  &
        "CSI_LANE3P			:	B9,"  &
        "REXT			:	C9,"  &
        "VDD_LV_DPHY			:	D9,"  &
        "VDD_HV_IO_PWM			:	C11,"  &
        "VSS_HV_IO_PWM			:	D11,"  &
        "VDD_HV_FLA			:	F17,"  &
        "VPP0			:	G16,"  &
        "AR_TXP_2			:	P5,"  &
        "AR_TXN_0			:	R5,"  &
        "AR_TXP_1			:	T5,"  &
        "AR_TXN_1			:	U5,"  &
        "VDD_LV_IO_AURORA			:	(P6,R7),"  &
        "AR_TXN_2			:	R6,"  &
        "AR_TXP_3			:	T6,"  &
        "AR_TXN_3			:	U6,"  &
        "VDD_LV_LFASTPLL			:	T7,"  &
        "VSS_LV_LFASTPLL			:	U7,"  &
        "VDD_HV_IO_DIGRF			:	R8,"  &
        "LFAST_RXP			:	T8,"  &
        "LFAST_RXN			:	U8,"  &
        "VSS_LV_PLL0			:	P9,"  &
        "VDD_LV_PLL0			:	R9,"  &
        "LFAST_TXN			:	T9,"  &
        "LFAST_TXP			:	U9,"  &
        "VDD_HV_IO_RGMII			:	R12,"  &
        "VREG_SEL			:	N14,"  &
        "VREG_ISENS			:	N15,"  &
        "VDD_HV_PMU			:	P15,"  &
        "VSS_HV_PMU			:	R15,"  &
        "VDD_HV_REG3V8			:	T15,"  &
        "VREG_POR_B			:	P16,"  &
        "VREG_SWP			:	R16,"  &
        "VSS_HV_REG3V8			:	T16";

-- This section specifies the TAP ports. For the TAP TCK port, the parameters in
-- the brackets are:
--        First Field : Maximum  TCK frequency.
--        Second Field: Allowable states TCK may be stopped in.

   attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
   attribute TAP_SCAN_IN    of PB_5 : signal is true;
   attribute TAP_SCAN_MODE  of TMS : signal is true;
   attribute TAP_SCAN_OUT   of PB_4 : signal is true;

-- Specifies the compliance enable patterns for the design. It lists a set of
-- design ports and the values that they should be set to, in order to enable
-- compliance to IEEE Std 1149.1


-- Specifies the number of bits in the instruction register.

   attribute INSTRUCTION_LENGTH of S32R274: entity is 5;

-- SPecifies the boundary-scan instructions implemented in the design and thier
-- opcodes.

   attribute INSTRUCTION_OPCODE of S32R274: entity is
      "IDCODE			(00001)," &
      "EXTEST			(00100)," &
      "PRELOAD			(00010)," &
      "SAMPLE			(00011)," &
      "CLAMP			(01100)," &
      "HIGHZ			(01001)," &
      "BYPASS			(11111)," &
      "PRIVATE1			(00101)," &
      "PRIVATE2			(00110)," &
      "PRIVATE3			(00111)," &
      "PRIVATE4			(01000)," &
      "PRIVATE5			(01010)," &
      "PRIVATE6			(01011)," &
      "PRIVATE7			(01101)," &
      "PRIVATE8			(01110)," &
      "PRIVATE9			(01111)," &
      "PRIVATE10			(10000, 10001, 10010, 10011, 10100, 10101, 10110, 10111, 11000, 11001, 11010, 11011, 11100, 11101, 11110)";

-- Specifies the bit pattern that is loaded into the instruction register when
-- the TAP controller passes through the Capture-IR state. The standard mandates
-- that the two LSBs must be "01". The remaining bits are design specific.

   attribute INSTRUCTION_CAPTURE of S32R274: entity is "00001";
   attribute INSTRUCTION_PRIVATE of S32R274: entity is
      "PRIVATE1," &
      "PRIVATE2," &
      "PRIVATE3," &
      "PRIVATE4," &
      "PRIVATE5," &
      "PRIVATE6," &
      "PRIVATE7," &
      "PRIVATE8," &
      "PRIVATE9," &
      "PRIVATE10" ;



-- Specifies the bit pattern that is loaded into the DEVICE_ID register during
-- the IDCODE instruction when the TAP controller passes through the Capture-DR
-- state.
   attribute IDCODE_REGISTER of S32R274: entity is
     "0000" &                -- version number
     "100110" &              -- design center
     "0011011000" &          -- part number
     "00000001110" &         -- manufacturer ID (Freescale)
     "1";                    -- Required by IEEE Std 1149.1

-- This section specifies the test data register placed between TDI and TDO for
-- each implemented instruction.


-- Specifies the length of the boundary scan register.

   attribute BOUNDARY_LENGTH of S32R274: entity is 152;

-- The following list specifies the characteristics of each cell in the boundary 
-- scan register from TDI to TDO. The following is a description of the label 
-- fields:
--      num     : Is the cell number.
--      cell    : Is the cell type as defined by the standard.
--      port    : Is the design port name. Control cells do not have a port 
--                name.
--      function: Is the function of the cell as defined by the standard. Is one 
--                of input, output2, output3, bidir, control or controlr.
--      safe    : Specifies the value that the BSR cell should be loaded with 
--                for safe operation when the software might otherwise choose a 
--                random value.
--      ccell   : The control cell number. Specifies the control cell that 
--                drives the output enable for this port.
--      disval  : Specifies the value that is loaded into the control cell to 
--                disable the output enable for the corresponding port.
--      rslt    : Resulting state. Shows the state of the driver when it is 
--                disabled.

   attribute BOUNDARY_REGISTER of S32R274: entity is
--
--    num	cell	port		function	safe	_ccell	disval	rslt
--
      "0	(BC_3,	PB_12,		input,	X)," &
      "1	(BC_3,	PB_11,		input,	X)," &
      "2	(BC_3,	PB_10,		input,	X)," &
      "3	(BC_3,	PB_9,		input,	X)," &
      "4	(BC_3,	PC_0,		input,	X)," &
      "5	(BC_3,	PB_15,		input,	X)," &
      "6	(BC_3,	PB_14,		input,	X)," &
      "7	(BC_3,	PB_13,		input,	X)," &
      "8	(BC_3,	PE_5,		input,	X)," &
      "9	(BC_3,	PE_4,		input,	X)," &
      "10	(BC_3,	PE_7,		input,	X)," &
      "11	(BC_3,	PE_2,		input,	X)," &
      "12	(BC_3,	PE_6,		input,	X)," &
      "13	(BC_3,	PC_2,		input,	X)," &
      "14	(BC_3,	PC_1,		input,	X)," &
      "15	(BC_3,	PB_8,		input,	X)," &
      "16	(BC_3,	PB_7,		input,	X)," &
      "17	(BC_2,	*,		control,	0)," &
      "18	(BC_7,	PI_2,		bidir,	X,	17,	0,	Z)," &
      "19	(BC_2,	*,		control,	0)," &
      "20	(BC_7,	PH_13,		bidir,	X,	19,	0,	Z)," &
      "21	(BC_2,	*,		control,	0)," &
      "22	(BC_7,	PH_9,		bidir,	X,	21,	0,	Z)," &
      "23	(BC_2,	*,		control,	0)," &
      "24	(BC_7,	PH_8,		bidir,	X,	23,	0,	Z)," &
      "25	(BC_2,	*,		control,	0)," &
      "26	(BC_7,	PH_5,		bidir,	X,	25,	0,	Z)," &
      "27	(BC_2,	*,		control,	0)," &
      "28	(BC_7,	PH_4,		bidir,	X,	27,	0,	Z)," &
      "29	(BC_2,	*,		control,	0)," &
      "30	(BC_7,	PG_11,		bidir,	X,	29,	0,	Z)," &
      "31	(BC_2,	*,		control,	0)," &
      "32	(BC_7,	PG_10,		bidir,	X,	31,	0,	Z)," &
      "33	(BC_2,	*,		control,	0)," &
      "34	(BC_7,	PD_6,		bidir,	X,	33,	0,	Z)," &
      "35	(BC_2,	*,		control,	0)," &
      "36	(BC_7,	PD_5,		bidir,	X,	35,	0,	Z)," &
      "37	(BC_2,	*,		control,	0)," &
      "38	(BC_7,	PD_4,		bidir,	X,	37,	0,	Z)," &
      "39	(BC_2,	*,		control,	0)," &
      "40	(BC_7,	PD_3,		bidir,	X,	39,	0,	Z)," &
      "41	(BC_2,	*,		control,	0)," &
      "42	(BC_7,	PD_2,		bidir,	X,	41,	0,	Z)," &
      "43	(BC_2,	*,		control,	0)," &
      "44	(BC_7,	PD_1,		bidir,	X,	43,	0,	Z)," &
      "45	(BC_2,	*,		control,	0)," &
      "46	(BC_7,	PD_0,		bidir,	X,	45,	0,	Z)," &
      "47	(BC_2,	*,		control,	0)," &
      "48	(BC_7,	PC_15,		bidir,	X,	47,	0,	Z)," &
      "49	(BC_2,	*,		control,	0)," &
      "50	(BC_7,	FCCU_F1,		bidir,	X,	49,	0,	Z)," &
      "51	(BC_2,	*,		control,	0)," &
      "52	(BC_7,	FCCU_F0,		bidir,	X,	51,	0,	Z)," &
      "53	(BC_2,	*,		control,	0)," &
      "54	(BC_7,	NMI,		bidir,	X,	53,	0,	Z)," &
      "55	(BC_2,	*,		control,	0)," &
      "56	(BC_7,	PI_9,		bidir,	X,	55,	0,	Z)," &
      "57	(BC_2,	*,		control,	0)," &
      "58	(BC_7,	PI_8,		bidir,	X,	57,	0,	Z)," &
      "59	(BC_2,	*,		control,	0)," &
      "60	(BC_7,	PI_7,		bidir,	X,	59,	0,	Z)," &
      "61	(BC_2,	*,		control,	0)," &
      "62	(BC_7,	PI_6,		bidir,	X,	61,	0,	Z)," &
      "63	(BC_2,	*,		control,	0)," &
      "64	(BC_7,	PI_5,		bidir,	X,	63,	0,	Z)," &
      "65	(BC_2,	*,		control,	0)," &
      "66	(BC_7,	PI_4,		bidir,	X,	65,	0,	Z)," &
      "67	(BC_2,	*,		control,	0)," &
      "68	(BC_7,	PI_1,		bidir,	X,	67,	0,	Z)," &
      "69	(BC_2,	*,		control,	0)," &
      "70	(BC_7,	PI_0,		bidir,	X,	69,	0,	Z)," &
      "71	(BC_2,	*,		control,	0)," &
      "72	(BC_7,	PH_12,		bidir,	X,	71,	0,	Z)," &
      "73	(BC_2,	*,		control,	0)," &
      "74	(BC_7,	PH_11,		bidir,	X,	73,	0,	Z)," &
      "75	(BC_2,	*,		control,	0)," &
      "76	(BC_7,	PH_7,		bidir,	X,	75,	0,	Z)," &
      "77	(BC_2,	*,		control,	0)," &
      "78	(BC_7,	PH_6,		bidir,	X,	77,	0,	Z)," &
      "79	(BC_2,	*,		control,	0)," &
      "80	(BC_7,	PG_9,		bidir,	X,	79,	0,	Z)," &
      "81	(BC_2,	*,		control,	0)," &
      "82	(BC_7,	PG_8,		bidir,	X,	81,	0,	Z)," &
      "83	(BC_2,	*,		control,	0)," &
      "84	(BC_7,	PG_5,		bidir,	X,	83,	0,	Z)," &
      "85	(BC_2,	*,		control,	0)," &
      "86	(BC_7,	PF_15,		bidir,	X,	85,	0,	Z)," &
      "87	(BC_2,	*,		control,	0)," &
      "88	(BC_7,	PF_14,		bidir,	X,	87,	0,	Z)," &
      "89	(BC_2,	*,		control,	0)," &
      "90	(BC_7,	PF_0,		bidir,	X,	89,	0,	Z)," &
      "91	(BC_2,	*,		control,	0)," &
      "92	(BC_7,	PE_15,		bidir,	X,	91,	0,	Z)," &
      "93	(BC_2,	*,		control,	0)," &
      "94	(BC_7,	PE_13,		bidir,	X,	93,	0,	Z)," &
      "95	(BC_2,	*,		control,	0)," &
      "96	(BC_7,	PD_14,		bidir,	X,	95,	0,	Z)," &
      "97	(BC_2,	*,		control,	0)," &
      "98	(BC_7,	PD_11,		bidir,	X,	97,	0,	Z)," &
      "99	(BC_2,	*,		control,	0)," &
      "100	(BC_7,	PD_8,		bidir,	X,	99,	0,	Z)," &
      "101	(BC_2,	*,		control,	0)," &
      "102	(BC_7,	PC_12,		bidir,	X,	101,	0,	Z)," &
      "103	(BC_2,	*,		control,	0)," &
      "104	(BC_7,	PC_11,		bidir,	X,	103,	0,	Z)," &
      "105	(BC_2,	*,		control,	0)," &
      "106	(BC_7,	PC_10,		bidir,	X,	105,	0,	Z)," &
      "107	(BC_2,	*,		control,	0)," &
      "108	(BC_7,	PB_6,		bidir,	X,	107,	0,	Z)," &
      "109	(BC_2,	*,		control,	0)," &
      "110	(BC_7,	PB_3,		bidir,	X,	109,	0,	Z)," &
      "111	(BC_2,	*,		control,	0)," &
      "112	(BC_7,	PB_2,		bidir,	X,	111,	0,	Z)," &
      "113	(BC_2,	*,		control,	0)," &
      "114	(BC_7,	PB_1,		bidir,	X,	113,	0,	Z)," &
      "115	(BC_2,	*,		control,	0)," &
      "116	(BC_7,	PB_0,		bidir,	X,	115,	0,	Z)," &
      "117	(BC_2,	*,		control,	0)," &
      "118	(BC_7,	PA_15,		bidir,	X,	117,	0,	Z)," &
      "119	(BC_2,	*,		control,	0)," &
      "120	(BC_7,	PA_14,		bidir,	X,	119,	0,	Z)," &
      "121	(BC_2,	*,		control,	0)," &
      "122	(BC_7,	PA_13,		bidir,	X,	121,	0,	Z)," &
      "123	(BC_2,	*,		control,	0)," &
      "124	(BC_7,	PA_12,		bidir,	X,	123,	0,	Z)," &
      "125	(BC_2,	*,		control,	0)," &
      "126	(BC_7,	PA_11,		bidir,	X,	125,	0,	Z)," &
      "127	(BC_2,	*,		control,	0)," &
      "128	(BC_7,	PA_10,		bidir,	X,	127,	0,	Z)," &
      "129	(BC_2,	*,		control,	0)," &
      "130	(BC_7,	PA_9,		bidir,	X,	129,	0,	Z)," &
      "131	(BC_2,	*,		control,	0)," &
      "132	(BC_7,	PA_8,		bidir,	X,	131,	0,	Z)," &
      "133	(BC_2,	*,		control,	0)," &
      "134	(BC_7,	PA_7,		bidir,	X,	133,	0,	Z)," &
      "135	(BC_2,	*,		control,	0)," &
      "136	(BC_7,	PA_6,		bidir,	X,	135,	0,	Z)," &
      "137	(BC_2,	*,		control,	0)," &
      "138	(BC_7,	PA_5,		bidir,	X,	137,	0,	Z)," &
      "139	(BC_2,	*,		control,	0)," &
      "140	(BC_7,	PA_4,		bidir,	X,	139,	0,	Z)," &
      "141	(BC_2,	*,		control,	0)," &
      "142	(BC_7,	PA_3,		bidir,	X,	141,	0,	Z)," &
      "143	(BC_2,	*,		control,	0)," &
      "144	(BC_7,	PA_2,		bidir,	X,	143,	0,	Z)," &
      "145	(BC_2,	*,		control,	0)," &
      "146	(BC_7,	PA_1,		bidir,	X,	145,	0,	Z)," &
      "147	(BC_2,	*,		control,	0)," &
      "148	(BC_7,	PA_0,		bidir,	X,	147,	0,	Z)," &
      "149	(BC_2,	*,		internal,	X)," &
      "150	(BC_2,	*,		internal,	X)," &
      "151	(BC_2,	*,		internal,	X)";

 end S32R274;