BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: IDT72V51336

-- Part: IDT72V51336 (512Kbit, 3.3V, x36, 8Q)
-- Ver: 0.1        Thu Sep 13 14:27:16 2001  MRZ

entity IDT72V51336 is


  -- Generic parameter

  generic (PHYSICAL_PIN_MAP: string := "BB256");


  -- Logical port description

  port (
        BM    :     in        bit;
        D     :     in        bit_vector(0 to 35);
        DF    :     in        bit;
        DFM   :     in        bit;
        ESTR  :     in        bit;
        ESYNC :     buffer    bit;
        EXI   :     in        bit;
        EXO   :     buffer    bit;
        FFB   :     out       bit;
        FM    :     in        bit;
        FSTR  :     in        bit;
        FSYNC :     buffer    bit;
        FXI   :     in        bit;
        FXO   :     buffer    bit;
        ID    :     in        bit_vector(0 to 2);
        IW    :     in        bit;
        MASTER:     in        bit;
        MRSB  :     in        bit;
        OEB   :     in        bit;
        OVB   :     out       bit;
        OW    :     in        bit;
        PAEB  :     out       bit;
        PAEnB :     out       bit_vector(0 to 7);
        PAFB  :     out       bit;
        PAFnB :     out       bit_vector(0 to 7);
        PKT   :     in        bit;
        PRB   :     out       bit;
        PRSB  :     in        bit;
        Q     :     out       bit_vector(0 to 35);
        RADEN :     in        bit;
        RCLK  :     in        bit;
        RENB  :     in        bit;
        RDADD :     in        bit_vector(0 to 6);
        SCLK  :     in        bit;
        SENIB :     in        bit;
        SENOB :     buffer    bit;
        SI    :     in        bit;
        SO    :     buffer    bit;
        TCK   :     in        bit;
        TDI   :     in        bit;
        TDO   :     out       bit;
        TMS   :     in        bit;
        TRSTB :     in        bit;
        WADEN :     in        bit;
        WCLK  :     in        bit;
        WENB  :     in        bit;
        WRADD :     in        bit_vector(0 to 5);
        VDD   :     linkage   bit_vector(0 to 55);
        GND   :     linkage   bit_vector(0 to 53);
        DNC   :     linkage   bit_vector(0 to 1)
        );


  -- Standard

  use STD_1149_1_1994.all;


  -- Component conformance

  attribute COMPONENT_CONFORMANCE of IDT72V51336: entity is "STD_1149_1_1993";


  -- Device package pin mappings

  attribute PIN_MAP of IDT72V51336: entity is PHYSICAL_PIN_MAP;


  -- Pin-port map for package BB256

  constant BB256: PIN_MAP_STRING :=
    "BM    : L14, " &
    "D     : (B7, A7, C6, B6, A6, C5, B5, A5, C4, B4, A4, B3,  " &
    "         A3, A2, A1, B1, B2, C1, C2, C3, D1, D2, D3, E1,  " &
    "         E2, E3, F1, F2, F3, G1, G2, G3, H1, H2, H3, J3), " &
    "DF    : L3,  " &
    "DFM   : L2,  " &
    "ESTR  : R15, " &
    "ESYNC : R16, " &
    "EXI   : T16, " &
    "EXO   : T15, " &
    "FFB   : P8,  " &
    "FM    : K16, " &
    "FSTR  : R4,  " &
    "FSYNC : R3,  " &
    "FXI   : T2,  " &
    "FXO   : T3,  " &
    "ID    : (B10, A10, C9), " &
    "IW    : L15, " &
    "MASTER: K15, " &
    "MRSB  : T9,  " &
    "OEB   : M14, " &
    "OVB   : P9,  " &
    "OW    : L16, " &
    "PAEB  : P10, " &
    "PAEnB : (T14, T13, R13, P13, T12, R12, P12, P11), " &
    "PAFB  : R8,  " &
    "PAFnB : (T4, T5, R5, P5, R7, R6, P6, P7), " &
    "PKT   : J14, " &
    "PRB   : R9,  " &
    "PRSB  : T8,  " &
    "Q     : (C10, C11, B11, A11, C12, B12, A12, C13, B13, A13, C14, B14,  " &
    "         A14, B15, A15, A16, D14, C15, C16, B16, D16, D15, E16, E15,  " &
    "         E14, F16, F15, F14, G16, G15, G14, H16, H15, H14, J16, J15), " &
    "RADEN : R14, " &
    "RCLK  : T10, " &
    "RENB  : T11, " &
    "RDADD : (M15, M16, N14, N15, P14, P15, P16), " &
    "SCLK  : N3,  " &
    "SENIB : M2,  " &
    "SENOB : M1,  " &
    "SI    : L1,  " &
    "SO    : M3,  " &
    "TCK   : A8,  " &
    "TDI   : B9,  " &
    "TDO   : A9,  " &
    "TMS   : B8,  " &
    "TRSTB : C7,  " &
    "WADEN : P4,  " &
    "WCLK  : T7,  " &
    "WENB  : T6,  " &
    "WRADD : (N2, N1, P3, R2, R1, T1), " &
    "VDD   : (D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, E4, E5,   " &
    "         E6, E7, E10, E11, E12, E13, F4, F5, F12, F13, G4, G5, " &
    "         G12, G13, H4, H13, J4, J13, K4, K5, K12, K13, L4, L5, " &
    "         L12, L13, M4, M5, M6, M7, M10, M11, M12, M13, N4, N5, " &
    "         N6, N7, N8, N9, N10, N11, N12, N13),                  " &
    "GND   : (E8, E9, F6, F7, F8, F9, F10, F11, G6, G7, G8, G9,    " &
    "         G10, G11, H5, H6, H7, H8, H9, H10, H11, H12, J1, J2, " &
    "         J5, J6, J7, J8, J9, J10, J11, J12, K2, K6, K7, K8,   " &
    "         K9, K10, K11, K14, L6, L7, L8, L9, L10, L11, M8, M9, " &
    "         C8, K3, K1, " &
    "         N16, P2, P1), " &
    "DNC   : (R10, R11)";


  -- Scan port identification

  attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
  attribute TAP_SCAN_IN of TDI : signal is true;
  attribute TAP_SCAN_MODE of TMS : signal is true;
  attribute TAP_SCAN_OUT of TDO : signal is true;
  attribute TAP_SCAN_RESET of TRSTB : signal is true;


  -- Instruction register description

  attribute INSTRUCTION_LENGTH of IDT72V51336: entity is 4;

  attribute INSTRUCTION_OPCODE of IDT72V51336: entity is
    "SAMPLE     (0001)," &
    "EXTEST     (0000)," &
    "IDCODE     (0010)," &
    "HIGHZ      (0100)," &
    "CLAMP      (0011)," &
    "BYPASS     (1111)," &
    "PRIVATE    (0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110)";

  attribute INSTRUCTION_CAPTURE of IDT72V51336: entity is "0101";

  attribute INSTRUCTION_PRIVATE of IDT72V51336: entity is "PRIVATE";


  -- Optional register description

  attribute IDCODE_REGISTER of IDT72V51336: entity is
    "0000" &                -- version
    "0000010000101011" &    -- part number
    "00000110011" &         -- manufacturer's identity
    "1";                    -- required by 1149.1


  -- Register access description

  attribute REGISTER_ACCESS of IDT72V51336: entity is
    "BYPASS     (BYPASS, HIGHZ, CLAMP), " &
    "BOUNDARY   (SAMPLE, EXTEST), " &
    "DEVICE_ID  (IDCODE)";


  -- Boundary-Scan register description

  attribute BOUNDARY_LENGTH of IDT72V51336: entity is 153;

  attribute BOUNDARY_REGISTER of IDT72V51336: entity is
  --
  -- num  cell   port           function   safe [ccell disval rslt]
  --
    "152 (BC_4,  ID(2),         input,     X),                    " &
    "151 (BC_4,  ID(1),         input,     X),                    " &
    "150 (BC_4,  ID(0),         input,     X),                    " &
    "149 (BC_1,  Q(0),          output3,   X,    107,    1,   Z), " &
    "148 (BC_1,  Q(1),          output3,   X,    107,    1,   Z), " &
    "147 (BC_1,  Q(2),          output3,   X,    107,    1,   Z), " &
    "146 (BC_1,  Q(3),          output3,   X,    107,    1,   Z), " &
    "145 (BC_1,  Q(4),          output3,   X,    107,    1,   Z), " &
    "144 (BC_1,  Q(5),          output3,   X,    107,    1,   Z), " &
    "143 (BC_1,  Q(6),          output3,   X,    107,    1,   Z), " &
    "142 (BC_1,  Q(7),          output3,   X,    107,    1,   Z), " &
    "141 (BC_1,  Q(8),          output3,   X,    107,    1,   Z), " &
    "140 (BC_1,  Q(9),          output3,   X,    107,    1,   Z), " &
    "139 (BC_1,  Q(10),         output3,   X,    107,    1,   Z), " &
    "138 (BC_1,  Q(11),         output3,   X,    107,    1,   Z), " &
    "137 (BC_1,  Q(12),         output3,   X,    107,    1,   Z), " &
    "136 (BC_1,  Q(13),         output3,   X,    107,    1,   Z), " &
    "135 (BC_1,  Q(14),         output3,   X,    107,    1,   Z), " &
    "134 (BC_1,  Q(15),         output3,   X,    107,    1,   Z), " &
    "133 (BC_1,  Q(16),         output3,   X,    107,    1,   Z), " &
    "132 (BC_1,  Q(17),         output3,   X,    107,    1,   Z), " &
    "131 (BC_1,  Q(18),         output3,   X,    107,    1,   Z), " &
    "130 (BC_1,  Q(19),         output3,   X,    107,    1,   Z), " &
    "129 (BC_1,  Q(20),         output3,   X,    107,    1,   Z), " &
    "128 (BC_1,  Q(21),         output3,   X,    107,    1,   Z), " &
    "127 (BC_1,  Q(22),         output3,   X,    107,    1,   Z), " &
    "126 (BC_1,  Q(23),         output3,   X,    107,    1,   Z), " &
    "125 (BC_1,  Q(24),         output3,   X,    107,    1,   Z), " &
    "124 (BC_1,  Q(25),         output3,   X,    107,    1,   Z), " &
    "123 (BC_1,  Q(26),         output3,   X,    107,    1,   Z), " &
    "122 (BC_1,  Q(27),         output3,   X,    107,    1,   Z), " &
    "121 (BC_1,  Q(28),         output3,   X,    107,    1,   Z), " &
    "120 (BC_1,  Q(29),         output3,   X,    107,    1,   Z), " &
    "119 (BC_1,  Q(30),         output3,   X,    107,    1,   Z), " &
    "118 (BC_1,  Q(31),         output3,   X,    107,    1,   Z), " &
    "117 (BC_1,  Q(32),         output3,   X,    107,    1,   Z), " &
    "116 (BC_1,  Q(33),         output3,   X,    107,    1,   Z), " &
    "115 (BC_1,  Q(34),         output3,   X,    107,    1,   Z), " &
    "114 (BC_1,  Q(35),         output3,   X,    107,    1,   Z), " &
    "113 (BC_4,  PKT,           input,     X),                    " &
    "112 (BC_4,  MASTER,        input,     X),                    " &
    "111 (BC_4,  FM,            input,     X),                    " &
    "110 (BC_4,  BM,            input,     X),                    " &
    "109 (BC_4,  IW,            input,     X),                    " &
    "108 (BC_4,  OW,            input,     X),                    " &
    "107 (BC_1,  OEB,           input,     1),                    " &
    "107 (BC_1,  *,             control,   1),                    " &
    "106 (BC_4,  RDADD(0),      input,     X),                    " &
    "105 (BC_4,  RDADD(1),      input,     X),                    " &
    "104 (BC_4,  RDADD(2),      input,     X),                    " &
    "103 (BC_4,  RDADD(3),      input,     X),                    " &
    "102 (BC_4,  *,             internal,  X),                    " &
    "101 (BC_4,  RDADD(4),      input,     X),                    " &
    "100 (BC_4,  RDADD(5),      input,     X),                    " &
    " 99 (BC_4,  RDADD(6),      input,     X),                    " &
    " 98 (BC_4,  RADEN,         input,     X),                    " &
    " 97 (BC_4,  ESTR,          input,     X),                    " &
    " 96 (BC_1,  ESYNC,         output2,   X),                    " &
    " 95 (BC_1,  EXO,           output2,   X),                    " &
    " 94 (BC_4,  EXI,           input,     X),                    " &
    " 93 (BC_1,  *,             control,   1),                    " &
    " 92 (BC_1,  PAEnB(0),      output3,   X,     93,    1,   Z), " &
    " 91 (BC_1,  PAEnB(1),      output3,   X,     93,    1,   Z), " &
    " 90 (BC_1,  PAEnB(2),      output3,   X,     93,    1,   Z), " &
    " 89 (BC_1,  PAEnB(3),      output3,   X,     93,    1,   Z), " &
    " 88 (BC_1,  PAEnB(4),      output3,   X,     93,    1,   Z), " &
    " 87 (BC_1,  PAEnB(5),      output3,   X,     93,    1,   Z), " &
    " 86 (BC_1,  PAEnB(6),      output3,   X,     93,    1,   Z), " &
    " 85 (BC_1,  PAEnB(7),      output3,   X,     93,    1,   Z), " &
    " 84 (BC_1,  *,             control,   1),                    " &
    " 83 (BC_1,  PRB,           output3,   X,     84,    1,   Z), " &
    " 82 (BC_1,  *,             control,   1),                    " &
    " 81 (BC_1,  PAEB,          output3,   X,     82,    1,   Z), " &
    " 80 (BC_1,  *,             control,   1),                    " &
    " 79 (BC_1,  OVB,           output3,   X,     80,    1,   Z), " &
    " 78 (BC_1,  *,             internal,  X),                    " &
    " 77 (BC_1,  *,             internal,  X),                    " &
    " 76 (BC_4,  RENB,          input,     X),                    " &
    " 75 (BC_4,  RCLK,          clock,     X),                    " &
    " 74 (BC_4,  MRSB,          input,     X),                    " &
    " 73 (BC_4,  WCLK,          clock,     X),                    " &
    " 72 (BC_4,  WENB,          input,     X),                    " &
    " 71 (BC_4,  PRSB,          input,     X),                    " &
    " 70 (BC_1,  *,             control,   1),                    " &
    " 69 (BC_1,  FFB,           output3,   X,     70,    1,   Z), " &
    " 68 (BC_1,  *,             control,   1),                    " &
    " 67 (BC_1,  PAFB,          output3,   X,     68,    1,   Z), " &
    " 66 (BC_1,  *,             control,   1),                    " &
    " 65 (BC_1,  PAFnB(7),      output3,   X,     66,    1,   Z), " &
    " 64 (BC_1,  PAFnB(6),      output3,   X,     66,    1,   Z), " &
    " 63 (BC_1,  PAFnB(5),      output3,   X,     66,    1,   Z), " &
    " 62 (BC_1,  PAFnB(4),      output3,   X,     66,    1,   Z), " &
    " 61 (BC_1,  PAFnB(3),      output3,   X,     66,    1,   Z), " &
    " 60 (BC_1,  PAFnB(2),      output3,   X,     66,    1,   Z), " &
    " 59 (BC_1,  PAFnB(1),      output3,   X,     66,    1,   Z), " &
    " 58 (BC_1,  PAFnB(0),      output3,   X,     66,    1,   Z), " &
    " 57 (BC_4,  FXI,           input,     X),                    " &
    " 56 (BC_1,  FXO,           output2,   X),                    " &
    " 55 (BC_1,  FSYNC,         output2,   X),                    " &
    " 54 (BC_4,  FSTR,          input,     X),                    " &
    " 53 (BC_4,  WADEN,         input,     X),                    " &
    " 52 (BC_4,  WRADD(5),      input,     X),                    " &
    " 51 (BC_4,  WRADD(4),      input,     X),                    " &
    " 50 (BC_4,  WRADD(3),      input,     X),                    " &
    " 49 (BC_4,  *,             internal,  X),                    " &
    " 48 (BC_4,  *,             internal,  X),                    " &
    " 47 (BC_4,  WRADD(2),      input,     X),                    " &
    " 46 (BC_4,  WRADD(1),      input,     X),                    " &
    " 45 (BC_4,  WRADD(0),      input,     X),                    " &
    " 44 (BC_4,  SCLK,          input,     X),                    " &
    " 43 (BC_1,  SENOB,         output2,   X),                    " &
    " 42 (BC_4,  SENIB,         input,     X),                    " &
    " 41 (BC_1,  SO,            output2,   X),                    " &
    " 40 (BC_4,  SI,            input,     X),                    " &
    " 39 (BC_4,  DFM,           input,     X),                    " &
    " 38 (BC_4,  DF,            input,     X),                    " &
    " 37 (BC_4,  *,             internal,  X),                    " &
    " 36 (BC_4,  D(35),         input,     X),                    " &
    " 35 (BC_4,  D(34),         input,     X),                    " &
    " 34 (BC_4,  D(33),         input,     X),                    " &
    " 33 (BC_4,  D(32),         input,     X),                    " &
    " 32 (BC_4,  D(31),         input,     X),                    " &
    " 31 (BC_4,  D(30),         input,     X),                    " &
    " 30 (BC_4,  D(29),         input,     X),                    " &
    " 29 (BC_4,  D(28),         input,     X),                    " &
    " 28 (BC_4,  D(27),         input,     X),                    " &
    " 27 (BC_4,  D(26),         input,     X),                    " &
    " 26 (BC_4,  D(25),         input,     X),                    " &
    " 25 (BC_4,  D(24),         input,     X),                    " &
    " 24 (BC_4,  D(23),         input,     X),                    " &
    " 23 (BC_4,  D(22),         input,     X),                    " &
    " 22 (BC_4,  D(21),         input,     X),                    " &
    " 21 (BC_4,  D(20),         input,     X),                    " &
    " 20 (BC_4,  D(19),         input,     X),                    " &
    " 19 (BC_4,  D(18),         input,     X),                    " &
    " 18 (BC_4,  D(17),         input,     X),                    " &
    " 17 (BC_4,  D(16),         input,     X),                    " &
    " 16 (BC_4,  D(15),         input,     X),                    " &
    " 15 (BC_4,  D(14),         input,     X),                    " &
    " 14 (BC_4,  D(13),         input,     X),                    " &
    " 13 (BC_4,  D(12),         input,     X),                    " &
    " 12 (BC_4,  D(11),         input,     X),                    " &
    " 11 (BC_4,  D(10),         input,     X),                    " &
    " 10 (BC_4,  D(9),          input,     X),                    " &
    "  9 (BC_4,  D(8),          input,     X),                    " &
    "  8 (BC_4,  D(7),          input,     X),                    " &
    "  7 (BC_4,  D(6),          input,     X),                    " &
    "  6 (BC_4,  D(5),          input,     X),                    " &
    "  5 (BC_4,  D(4),          input,     X),                    " &
    "  4 (BC_4,  D(3),          input,     X),                    " &
    "  3 (BC_4,  D(2),          input,     X),                    " &
    "  2 (BC_4,  D(1),          input,     X),                    " &
    "  1 (BC_4,  D(0),          input,     X),                    " &
    "  0 (BC_4,  *,             internal,  X)                     ";

end IDT72V51336;