-- ****************** (C) COPYRIGHT 2019 STMicroelectronics **************************
-- * File Name : STM32WB55_BGA129.bsd *
-- * Author : STMicroelectronics www.st.com *
-- * Version : V1.0 *
-- * Date : 11-February-2019 *
-- * Description : Boundary Scan Description Language (BSDL) file for the *
-- * STM32WB55_BGA129 Microcontrollers. *
-- ***********************************************************************************
-- * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS *
-- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.*
-- * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, *
-- * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE *
-- * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING *
-- * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
-- ***********************************************************************************
-- * This BSDL file has been syntaxed checked and validated by: *
-- * GOEPEL SyntaxChecker Version 3.1.2 *
-- ***********************************************************************************
entity STM32WB55_BGA129 is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "GENERIC_PACKAGE");
-- This section declares all the ports in the design.
port (
PE2 : inout bit;
PE3 : inout bit;
PE4 : inout bit;
VBAT : linkage bit;
PC13 : inout bit;
PC14 : inout bit;
PC15 : inout bit;
PH0 : inout bit;
PH1 : inout bit;
PC0 : inout bit;
PC1 : inout bit;
PC2 : inout bit;
PC3 : inout bit;
PA0 : inout bit;
PA1 : inout bit;
PA2 : inout bit;
PA3 : inout bit;
PA4 : inout bit;
PA5 : inout bit;
PA6 : inout bit;
PA7 : inout bit;
PC4 : inout bit;
PC5 : inout bit;
PB0 : inout bit;
PB1 : inout bit;
PB2 : inout bit;
PB10 : inout bit;
PB11 : inout bit;
PB12 : inout bit;
PB13 : inout bit;
PB14 : inout bit;
PB15 : inout bit;
PD8 : inout bit;
PD9 : inout bit;
PD10 : inout bit;
PD11 : inout bit;
PD12 : inout bit;
PD13 : inout bit;
PD14 : inout bit;
PD15 : inout bit;
VDDT : linkage bit;
RF1 : linkage bit;
VSSRF : linkage bit_vector(0 to 12);
VDDRF : linkage bit;
VSSA : linkage bit;
VREFP : linkage bit;
VDDA : linkage bit;
OSC_OUT : linkage bit;
OSC_IN : linkage bit;
AT0 : linkage bit;
AT1 : linkage bit;
PC6 : inout bit;
PC7 : inout bit;
PC8 : inout bit;
PC9 : inout bit;
PA8 : inout bit;
PA9 : inout bit;
VDDCAP : linkage bit_vector(0 to 3);
VFBSMPS : linkage bit;
VSSSMPS : linkage bit_vector(0 to 1);
VLXSMPS : linkage bit_vector(0 to 1);
VDDSMPS : linkage bit_vector(0 to 1);
PA10 : inout bit;
PA11 : inout bit;
PA12 : inout bit;
VDDUSB : linkage bit;
PC10 : inout bit;
PC11 : inout bit;
PC12 : inout bit;
PD0 : inout bit;
PD1 : inout bit;
PD2 : inout bit;
PD3 : inout bit;
PD4 : inout bit;
PD5 : inout bit;
PD6 : inout bit;
PD7 : inout bit;
PB5 : inout bit;
PB6 : inout bit;
PB7 : inout bit;
PH3 : inout bit;
PB8 : inout bit;
PB9 : inout bit;
PE0 : inout bit;
PE1 : inout bit;
JTDI : in bit;
JTMS : in bit;
JTCK : in bit;
JTRST : in bit;
JTDO : out bit;
VDD : linkage bit_vector(0 to 4);
VSS : linkage bit_vector(0 to 15);
NRST : in bit
);
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of STM32WB55_BGA129: entity is "STD_1149_1_2001";
attribute PIN_MAP of STM32WB55_BGA129 : entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information is extracted from the
-- port-to-pin map file that was read in using the "read_pin_map" command.
constant GENERIC_PACKAGE: PIN_MAP_STRING :=
"PE2 : B1 ," &
"PE3 : H12 ," &
"PE4 : H13 ," &
"VBAT : D2 ," &
"PC13 : F4 ," &
"PC14 : E3 ," &
"PC15 : E2 ," &
"PH0 : F1 ," &
"PH1 : G2 ," &
"PC0 : H3 ," &
"PC1 : H1 ," &
"PC2 : J2 ," &
"PC3 : J3 ," &
"NRST : H2 ," &
"VSSA : K2 ," &
"VREFP: L1 ," &
"VDDA : K3 ," &
"PA0 : M1 ," &
"PA1 : L2 ," &
"PA2 : N1 ," &
"PA3 : M2 ," &
"PA4 : L3 ," &
"PA5 : N2 ," &
"PA6 : M3 ," &
"PA7 : N3 ," &
"PC4 : M5 ," &
"PC5 : L5 ," &
"PB0 : L13 ," &
"PB1 : L12 ," &
"PB2 : N6 ," &
"PB10 : L6 ," &
"PB11 : M6 ," &
"PB12 : H10 ," &
"PB13 : E12 ," &
"PB14 : E11 ," &
"PB15 : F10 ," &
"PD8 : B6 ," &
"PD9 : D4 ," &
"PD10 : A10 ," &
"PD11 : B5 ," &
"PD12 : B4 ," &
"PD13 : C1 ," &
"PD14 : D3 ," &
"PD15 : C2 ," &
"VDDCAP : (F2, N7, A8, J12 )," &
"RF1 : M9 ," &
"VSSRF: (L7, K8, L8, M8, N8, L9, K10, L10, M10, L11, M11, N11, M12)," &
"VDDRF: N12 ," &
"OSC_OUT : N13 ," &
"OSC_IN : M13 ," &
"AT0 : K11 ," &
"AT1 : K12 ," &
"PC6 : D10 ," &
"PC7 : D12 ," &
"PC8 : D11 ," &
"PC9 : C13 ," &
"PA8 : M4 ," &
"PA9 : L4 ," &
"VFBSMPS : H11 ," &
"VSSSMPS : (G12, G13)," &
"VLXSMPS : (F11, G11)," &
"VDDSMPS : (F12, F13)," &
"PA10 : C12 ," &
"PA11 : B13 ," &
"PA12 : A13 ," &
"JTMS : A11 ," &
"JTCK : C10 ," &
"JTDI : C9 ," &
"VDDUSB : A12 ," &
"PC10 : B9 ," &
"PC11 : C8 ," &
"PC12 : B10 ," &
"PD0 : B11 ," &
"PD1 : C7 ," &
"PD2 : B7 ," &
"PD3 : D8 ," &
"PD4 : C6 ," &
"JTDO : C4 ," &
"JTRST : B3 ," &
"PD5 : A6 ," &
"PD6 : D6 ," &
"PD7 : C5 ," &
"PB5 : A3 ," &
"PB6 : A2 ," &
"PB7 : C3 ," &
"PH3 : G1 ," &
"PB8 : G3 ," &
"PB9 : H4 ," &
"PE0 : B2 ," &
"PE1 : A1 ," &
"VDD : (F6, H6, G7, F8, H8)," &
"VSS : (F3, K4, E5, G5, J5, K6, E7, J7, M7, B8, E9, G9, J9, J11, C11, B12) " ;
-- This section specifies the TAP ports. For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of JTCK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of JTDI : signal is true;
attribute TAP_SCAN_MODE of JTMS : signal is true;
attribute TAP_SCAN_OUT of JTDO : signal is true;
attribute TAP_SCAN_RESET of JTRST : signal is true;
-- Specifies the compliance enable patterns for the design. It lists a set of
-- design ports and the values that they should be set to, in order to enable
-- compliance to IEEE Std 1149.1
attribute COMPLIANCE_PATTERNS of STM32WB55_BGA129: entity is
"(NRST) (0)";
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of STM32WB55_BGA129: entity is 5;
-- Specifies the boundary-scan instructions implemented in the design and their opcodes.
attribute INSTRUCTION_OPCODE of STM32WB55_BGA129: entity is
"BYPASS (11111)," &
"EXTEST (00000)," &
"SAMPLE (00010)," &
"PRELOAD (00010)," &
"IDCODE (00001)";
-- Specifies the bit pattern that is loaded into the instruction register when the TAP controller
-- passes through the Capture-IR state. The standard mandates that the two LSBs must be "01". The
-- remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of STM32WB55_BGA129: entity is "XXX01";
-- Specifies the bit pattern that is loaded into the DEVICE_ID register during the IDCODE
-- instruction when the TAP controller passes through the Capture-DR state.
attribute IDCODE_REGISTER of STM32WB55_BGA129: entity is
"XXXX" & -- 4-bit version number
"0110010010010101" & -- 16-bit part number
"00000100000" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI and TDO for each implemented
-- instruction.
attribute REGISTER_ACCESS of STM32WB55_BGA129: entity is
"BYPASS (BYPASS)," &
"BOUNDARY (EXTEST, SAMPLE, PRELOAD)," &
"DEVICE_ID (IDCODE)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of STM32WB55_BGA129: entity is 201;
-- The following list specifies the characteristics of each cell in the boundary scan register from
-- TDI to TDO. The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not have a port name.
-- function: Is the function of the cell as defined by the standard. Is one of input, output2,
-- output3, bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be loaded with for safe operation
-- when the software might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control cell that drives the output enable
-- for this port.
-- disval : Specifies the value that is loaded into the control cell to disable the output
-- enable for the corresponding port.
-- rslt : Resulting state. Shows the state of the driver when it is disabled.
attribute BOUNDARY_REGISTER of STM32WB55_BGA129: entity is
--
-- num cell port function safe [ccell disval rslt]
--
--------------------------------------------------------------------------------
"200 (BC_1, *, CONTROL, 1) ," &
"199 (BC_1, PE2, OUTPUT3, X, 200, 1, Z) ," &
"198 (BC_4, PE2, INPUT, X) ," &
"197 (BC_1, *, CONTROL, 1) ," &
"196 (BC_1, PE3, OUTPUT3, X, 197, 1, Z) ," &
"195 (BC_4, PE3, INPUT, X) ," &
"194 (BC_1, *, CONTROL, 1) ," &
"193 (BC_1, PE4, OUTPUT3, X, 194, 1, Z) ," &
"192 (BC_4, PE4, INPUT, X) ," &
"191 (BC_1, *, CONTROL, 1) ," &
"190 (BC_1, PC13, OUTPUT3, X, 191, 1, Z) ," &
"189 (BC_4, PC13, INPUT, X) ," &
"188 (BC_1, *, CONTROL, 1) ," &
"187 (BC_1, PC14, OUTPUT3, X, 188, 1, Z) ," &
"186 (BC_4, PC14, INPUT, X) ," &
"185 (BC_1, *, CONTROL, 1) ," &
"184 (BC_1, PC15, OUTPUT3, X, 185, 1, Z) ," &
"183 (BC_4, PC15, INPUT, X) ," &
"182 (BC_1, *, CONTROL, 1) ," &
"181 (BC_1, PH0, OUTPUT3, X, 182, 1, Z) ," &
"180 (BC_4, PH0, INPUT, X) ," &
"179 (BC_1, *, CONTROL, 1) ," &
"178 (BC_1, PH1, OUTPUT3, X, 179, 1, Z) ," &
"177 (BC_4, PH1, INPUT, X) ," &
"176 (BC_1, *, CONTROL, 1) ," &
"175 (BC_1, PC0, OUTPUT3, X, 176, 1, Z) ," &
"174 (BC_4, PC0, INPUT, X) ," &
"173 (BC_1, *, CONTROL, 1) ," &
"172 (BC_1, PC1, OUTPUT3, X, 173, 1, Z) ," &
"171 (BC_4, PC1, INPUT, X) ," &
"170 (BC_1, *, CONTROL, 1) ," &
"169 (BC_1, PC2, OUTPUT3, X, 170, 1, Z) ," &
"168 (BC_4, PC2, INPUT, X) ," &
"167 (BC_1, *, CONTROL, 1) ," &
"166 (BC_1, PC3, OUTPUT3, X, 167, 1, Z) ," &
"165 (BC_4, PC3, INPUT, X) ," &
"164 (BC_1, *, CONTROL, 1) ," &
"163 (BC_1, PA0, OUTPUT3, X, 164, 1, Z) ," &
"162 (BC_4, PA0, INPUT, X) ," &
"161 (BC_1, *, CONTROL, 1) ," &
"160 (BC_1, PA1, OUTPUT3, X, 161, 1, Z) ," &
"159 (BC_4, PA1, INPUT, X) ," &
"158 (BC_1, *, CONTROL, 1) ," &
"157 (BC_1, PA2, OUTPUT3, X, 158, 1, Z) ," &
"156 (BC_4, PA2, INPUT, X) ," &
"155 (BC_1, *, CONTROL, 1) ," &
"154 (BC_1, PA3, OUTPUT3, X, 155, 1, Z) ," &
"153 (BC_4, PA3, INPUT, X) ," &
"152 (BC_1, *, CONTROL, 1) ," &
"151 (BC_1, PA4, OUTPUT3, X, 152, 1, Z) ," &
"150 (BC_4, PA4, INPUT, X) ," &
"149 (BC_1, *, CONTROL, 1) ," &
"148 (BC_1, PA5, OUTPUT3, X, 149, 1, Z) ," &
"147 (BC_4, PA5, INPUT, X) ," &
"146 (BC_1, *, CONTROL, 1) ," &
"145 (BC_1, PA6, OUTPUT3, X, 146, 1, Z) ," &
"144 (BC_4, PA6, INPUT, X) ," &
"143 (BC_1, *, CONTROL, 1) ," &
"142 (BC_1, PA7, OUTPUT3, X, 143, 1, Z) ," &
"141 (BC_4, PA7, INPUT, X) ," &
"140 (BC_1, *, CONTROL, 1) ," &
"139 (BC_1, PC4, OUTPUT3, X, 140, 1, Z) ," &
"138 (BC_4, PC4, INPUT, X) ," &
"137 (BC_1, *, CONTROL, 1) ," &
"136 (BC_1, PC5, OUTPUT3, X, 137, 1, Z) ," &
"135 (BC_4, PC5, INPUT, X) ," &
"134 (BC_1, *, CONTROL, 1) ," &
"133 (BC_1, PB0, OUTPUT3, X, 134, 1, Z) ," &
"132 (BC_4, PB0, INPUT, X) ," &
"131 (BC_1, *, CONTROL, 1) ," &
"130 (BC_1, PB1, OUTPUT3, X, 131, 1, Z) ," &
"129 (BC_4, PB1, INPUT, X) ," &
"128 (BC_1, *, CONTROL, 1) ," &
"127 (BC_1, PB2, OUTPUT3, X, 128, 1, Z) ," &
"126 (BC_4, PB2, INPUT, X) ," &
"125 (BC_1, *, CONTROL, 1) ," &
"124 (BC_1, PB10, OUTPUT3, X, 125, 1, Z) ," &
"123 (BC_4, PB10, INPUT, X) ," &
"122 (BC_1, *, CONTROL, 1) ," &
"121 (BC_1, PB11, OUTPUT3, X, 122, 1, Z) ," &
"120 (BC_4, PB11, INPUT, X) ," &
"119 (BC_1, *, CONTROL, 1) ," &
"118 (BC_1, PB12, OUTPUT3, X, 119, 1, Z) ," &
"117 (BC_4, PB12, INPUT, X) ," &
"116 (BC_1, *, CONTROL, 1) ," &
"115 (BC_1, PB13, OUTPUT3, X, 116, 1, Z) ," &
"114 (BC_4, PB13, INPUT, X) ," &
"113 (BC_1, *, CONTROL, 1) ," &
"112 (BC_1, PB14, OUTPUT3, X, 113, 1, Z) ," &
"111 (BC_4, PB14, INPUT, X) ," &
"110 (BC_1, *, CONTROL, 1) ," &
"109 (BC_1, PB15, OUTPUT3, X, 110, 1, Z) ," &
"108 (BC_4, PB15, INPUT, X) ," &
"107 (BC_1, *, CONTROL, 1) ," &
"106 (BC_1, PD8, OUTPUT3, X, 107, 1, Z) ," &
"105 (BC_4, PD8, INPUT, X) ," &
"104 (BC_1, *, CONTROL, 1) ," &
"103 (BC_1, PD9, OUTPUT3, X, 104, 1, Z) ," &
"102 (BC_4, PD9, INPUT, X) ," &
"101 (BC_1, *, CONTROL, 1) ," &
"100 (BC_1, PD10, OUTPUT3, X, 101, 1, Z) ," &
"99 (BC_4, PD10, INPUT, X) ," &
"98 (BC_1, *, CONTROL, 1) ," &
"97 (BC_1, PD11, OUTPUT3, X, 98, 1, Z) ," &
"96 (BC_4, PD11, INPUT, X) ," &
"95 (BC_1, *, CONTROL, 1) ," &
"94 (BC_1, PD12, OUTPUT3, X, 95, 1, Z) ," &
"93 (BC_4, PD12, INPUT, X) ," &
"92 (BC_1, *, CONTROL, 1) ," &
"91 (BC_1, PD13, OUTPUT3, X, 92, 1, Z) ," &
"90 (BC_4, PD13, INPUT, X) ," &
"89 (BC_1, *, CONTROL, 1) ," &
"88 (BC_1, PD14, OUTPUT3, X, 89, 1, Z) ," &
"87 (BC_4, PD14, INPUT, X) ," &
"86 (BC_1, *, CONTROL, 1) ," &
"85 (BC_1, PD15, OUTPUT3, X, 86, 1, Z) ," &
"84 (BC_4, PD15, INPUT, X) ," &
"83 (BC_1, *, CONTROL, 1) ," &
"82 (BC_1, PC6, OUTPUT3, X, 83, 1, Z) ," &
"81 (BC_4, PC6, INPUT, X) ," &
"80 (BC_1, *, CONTROL, 1) ," &
"79 (BC_1, PC7, OUTPUT3, X, 80, 1, Z) ," &
"78 (BC_4, PC7, INPUT, X) ," &
"77 (BC_1, *, CONTROL, 1) ," &
"76 (BC_1, PC8, OUTPUT3, X, 77, 1, Z) ," &
"75 (BC_4, PC8, INPUT, X) ," &
"74 (BC_1, *, CONTROL, 1) ," &
"73 (BC_1, PC9, OUTPUT3, X, 74, 1, Z) ," &
"72 (BC_4, PC9, INPUT, X) ," &
"71 (BC_1, *, CONTROL, 1) ," &
"70 (BC_1, PA8, OUTPUT3, X, 71, 1, Z) ," &
"69 (BC_4, PA8, INPUT, X) ," &
"68 (BC_1, *, CONTROL, 1) ," &
"67 (BC_1, PA9, OUTPUT3, X, 68, 1, Z) ," &
"66 (BC_4, PA9, INPUT, X) ," &
"65 (BC_1, *, CONTROL, 1) ," &
"64 (BC_1, PA10, OUTPUT3, X, 65, 1, Z) ," &
"63 (BC_4, PA10, INPUT, X) ," &
"62 (BC_1, *, CONTROL, 1) ," &
"61 (BC_1, PA11, OUTPUT3, X, 62, 1, Z) ," &
"60 (BC_4, PA11, INPUT, X) ," &
"59 (BC_1, *, CONTROL, 1) ," &
"58 (BC_1, PA12, OUTPUT3, X, 59, 1, Z) ," &
"57 (BC_4, PA12, INPUT, X) ," &
"56 (BC_1, *, CONTROL, 1) ," &
"55 (BC_1, PC10, OUTPUT3, X, 56, 1, Z) ," &
"54 (BC_4, PC10, INPUT, X) ," &
"53 (BC_1, *, CONTROL, 1) ," &
"52 (BC_1, PC11, OUTPUT3, X, 53, 1, Z) ," &
"51 (BC_4, PC11, INPUT, X) ," &
"50 (BC_1, *, CONTROL, 1) ," &
"49 (BC_1, PC12, OUTPUT3, X, 50, 1, Z) ," &
"48 (BC_4, PC12, INPUT, X) ," &
"47 (BC_1, *, CONTROL, 1) ," &
"46 (BC_1, PD0, OUTPUT3, X, 47, 1, Z) ," &
"45 (BC_4, PD0, INPUT, X) ," &
"44 (BC_1, *, CONTROL, 1) ," &
"43 (BC_1, PD1, OUTPUT3, X, 44, 1, Z) ," &
"42 (BC_4, PD1, INPUT, X) ," &
"41 (BC_1, *, CONTROL, 1) ," &
"40 (BC_1, PD2, OUTPUT3, X, 41, 1, Z) ," &
"39 (BC_4, PD2, INPUT, X) ," &
"38 (BC_1, *, CONTROL, 1) ," &
"37 (BC_1, PD3, OUTPUT3, X, 38, 1, Z) ," &
"36 (BC_4, PD3, INPUT, X) ," &
"35 (BC_1, *, CONTROL, 1) ," &
"34 (BC_1, PD4, OUTPUT3, X, 35, 1, Z) ," &
"33 (BC_4, PD4, INPUT, X) ," &
"32 (BC_1, *, CONTROL, 1) ," &
"31 (BC_1, PD5, OUTPUT3, X, 32, 1, Z) ," &
"30 (BC_4, PD5, INPUT, X) ," &
"29 (BC_1, *, CONTROL, 1) ," &
"28 (BC_1, PD6, OUTPUT3, X, 29, 1, Z) ," &
"27 (BC_4, PD6, INPUT, X) ," &
"26 (BC_1, *, CONTROL, 1) ," &
"25 (BC_1, PD7, OUTPUT3, X, 26, 1, Z) ," &
"24 (BC_4, PD7, INPUT, X) ," &
"23 (BC_1, *, CONTROL, 1) ," &
"22 (BC_1, PB5, OUTPUT3, X, 23, 1, Z) ," &
"21 (BC_4, PB5, INPUT, X) ," &
"20 (BC_1, *, CONTROL, 1) ," &
"19 (BC_1, PB6, OUTPUT3, X, 20, 1, Z) ," &
"18 (BC_4, PB6, INPUT, X) ," &
"17 (BC_1, *, CONTROL, 1) ," &
"16 (BC_1, PB7, OUTPUT3, X, 17, 1, Z) ," &
"15 (BC_4, PB7, INPUT, X) ," &
"14 (BC_1, *, CONTROL, 1) ," &
"13 (BC_1, PH3, OUTPUT3, X, 14, 1, Z) ," &
"12 (BC_4, PH3, INPUT, X) ," &
"11 (BC_1, *, CONTROL, 1) ," &
"10 (BC_1, PB8, OUTPUT3, X, 11, 1, Z) ," &
"9 (BC_4, PB8, INPUT, X) ," &
"8 (BC_1, *, CONTROL, 1) ," &
"7 (BC_1, PB9, OUTPUT3, X, 8, 1, Z) ," &
"6 (BC_4, PB9, INPUT, X) ," &
"5 (BC_1, *, CONTROL, 1) ," &
"4 (BC_1, PE0, OUTPUT3, X, 5, 1, Z) ," &
"3 (BC_4, PE0, INPUT, X) ," &
"2 (BC_1, *, CONTROL, 1) ," &
"1 (BC_1, PE1, OUTPUT3, X, 2, 1, Z) ," &
"0 (BC_4, PE1, INPUT, X) " ;
attribute DESIGN_WARNING of STM32WB55_BGA129: entity is
"Device configuration can effect boundary scan behavior. " &
"Keep the NRST pin low to ensure default boundary scan operation " &
"as described in this file." ;
end STM32WB55_BGA129;
-- ******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE********
