BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: XC2S15_VQ100 latest version

--$ XILINX$RCSfile: xc2s15_vq100.bsd,v $
--$ XILINX$Revision: 1.1 $
--
-- BSDL file for device XC2S15, package VQ100
-- Xilinx, Inc. $State: PRELIMINARY $ $Date: 2000-08-16 09:46:08-07 $
-- Generated by createBSDL 2.20
--
-- For technical support, contact Xilinx as follows:
--	North America	1-800-255-7778		hotline@xilinx.com
--	United Kingdom	(44) 1932 820821	ukhelp@xilinx.com
--	France		(33) 1 3463 0100	frhelp@xilinx.com
--	Germany		(49) 89 991 54930	dlhelp@xilinx.com
--	Japan		(81) 3-3297-9163	jhotline@xilinx.com
--

-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect
-- the post-configuration JTAG behavior (if any), edit this file as described
-- below. Many of these changes are demonstrated by commented-out template
-- lines preceeding the lines they would replace:
--
-- 1. Enable USER instructions as appropriate (see below).
-- 2. Set disable result of all pads as configured.
-- 3. Set safe state of boundary cells as necessary.
-- 4. Rename entity if necessary to avoid name collisions.
-- 5. Modify USERCODE value in USERCODE_REGISTER declaration.
--
-- The boundary scan test vectors must keep the PROGRAM pin either 3-stated
-- or driving high. If the PROGRAM pin is driven low through any means,
-- the TAP controller will reset.
--
-- All IOBs prior to configuration, and unused and output-only IOBs following
-- configuration, will sense their pad values during boundary-scan with an LVTTL
-- input buffer. In order to properly capture a logic high value driven from one
-- of these IOBs into an input boundary scan cell, VCCO must be
-- at least 2V (Vih for LVTTL).
--
-- For post-configuration boundary scan only: If an IOB is configured to use
-- an input standard that uses VREF pins, then the boundary scan test vectors
-- must keep the used VREF pins 3-stated.
--
-- The disable value of a 3-stated I/O is set to PULL0 - the proper value
-- for configuration modes without the pre-configuration
-- pullups (M2,M1,M0 set to 000, 101, 110, or 111). If not in one of
-- these modes, all PULL0's should be PULL1's. Additionally, when in
-- EXTEST updating the values for M2, M1, and M0 will directly affect
-- the existence of the pre-configuration pullup.
-- It is therefore recommended to shift in the same mode being driven
-- externally when relying upon the these values.



entity XC2S15_VQ100 is

generic (PHYSICAL_PIN_MAP : string := "VQ100" );

port (
	CCLK_P75: inout bit;
	DONE_P49: inout bit;
	GCK0_P39: in bit;
	GCK1_P36: in bit;
	GCK2_P88: in bit;
	GCK3_P91: in bit;
	GND: linkage bit_vector (1 to 8);
	INIT_P52: inout bit; --  PAD48
	M0_P25: in bit;
	M1_P23: in bit;
	M2_P27: in bit;
	PROGRAM: in bit;
	PWDNB: in bit;
	STATUSB: linkage bit;
	TCK: in bit;
	TDI: in bit;
	TDO: out bit;
	TMS: in bit;
	VCCINT: linkage bit_vector (1 to 8);
	VCCO: linkage bit_vector (1 to 8);
	IO_P3: inout bit; --  PAD95
	IO_P4: inout bit; --  PAD93
	IO_P5: inout bit; --  PAD92
	IO_P6: inout bit; --  PAD91
	IO_P7: inout bit; --  PAD90
	IO_P8: inout bit; --  PAD88
	IO_P9: inout bit; --  PAD87
	IO_P10: inout bit; --  PAD85
	IO_P13: inout bit; --  PAD84
	IO_P15: inout bit; --  PAD82
	IO_P16: inout bit; --  PAD81
	IO_P17: inout bit; --  PAD79
	IO_P18: inout bit; --  PAD78
	IO_P19: inout bit; --  PAD77
	IO_P20: inout bit; --  PAD76
	IO_P21: inout bit; --  PAD74
	IO_P22: inout bit; --  PAD73
	IO_P30: inout bit; --  PAD69
	IO_P31: inout bit; --  PAD68
	IO_P32: inout bit; --  PAD67
	IO_P34: inout bit; --  PAD64
	IO_P40: inout bit; --  PAD59
	IO_P41: inout bit; --  PAD57
	IO_P43: inout bit; --  PAD54
	IO_P44: inout bit; --  PAD53
	IO_P45: inout bit; --  PAD52
	IO_P46: inout bit; --  PAD50
	IO_P47: inout bit; --  PAD49
	IO_P53: inout bit; --  PAD47
	IO_P54: inout bit; --  PAD45
	IO_P55: inout bit; --  PAD44
	IO_P56: inout bit; --  PAD43
	IO_P57: inout bit; --  PAD42
	IO_P58: inout bit; --  PAD41
	IO_P59: inout bit; --  PAD40
	IO_P60: inout bit; --  PAD39
	IO_P62: inout bit; --  PAD37
	IO_P65: inout bit; --  PAD36
	IO_P66: inout bit; --  PAD34
	IO_P67: inout bit; --  PAD33
	IO_P68: inout bit; --  PAD32
	IO_P69: inout bit; --  PAD31
	IO_P70: inout bit; --  PAD30
	IO_P71: inout bit; --  PAD29
	IO_P72: inout bit; --  PAD28
	IO_P73: inout bit; --  PAD26
	IO_P74: inout bit; --  PAD25
	IO_P80: inout bit; --  PAD24
	IO_P81: inout bit; --  PAD23
	IO_P82: inout bit; --  PAD21
	IO_P83: inout bit; --  PAD20
	IO_P84: inout bit; --  PAD19
	IO_P86: inout bit; --  PAD16
	IO_P87: inout bit; --  PAD14
	IO_P93: inout bit; --  PAD9
	IO_P95: inout bit; --  PAD6
	IO_P96: inout bit; --  PAD5
	IO_P97: inout bit; --  PAD4
	IO_P98: inout bit --  PAD2
); --end port list

use STD_1149_1_1994.all;

attribute COMPONENT_CONFORMANCE of XC2S15_VQ100 : entity is
	"STD_1149_1_1993";

attribute PIN_MAP of XC2S15_VQ100 : entity is PHYSICAL_PIN_MAP;

constant VQ100: PIN_MAP_STRING:=
	"CCLK_P75:P75," &
	"DONE_P49:P49," &
	"GCK0_P39:P39," &
	"GCK1_P36:P36," &
	"GCK2_P88:P88," &
	"GCK3_P91:P91," &
	"GND:(P1,P11,P24,P38,P48,P64,P78,P89)," &
	"INIT_P52:P52," &
	"M0_P25:P25," &
	"M1_P23:P23," &
	"M2_P27:P27," &
	"PROGRAM:P51," &
	"PWDNB:P28," &
	"STATUSB:P29," &
	"TCK:P99," &
	"TDI:P79," &
	"TDO:P77," &
	"TMS:P2," &
	"VCCINT:(P14,P33,P35,P42,P61,P85,P92,P94)," &
	"VCCO:(P12,P26,P37,P50,P63,P76,P90,P100)," &
	"IO_P3:P3," &
	"IO_P4:P4," &
	"IO_P5:P5," &
	"IO_P6:P6," &
	"IO_P7:P7," &
	"IO_P8:P8," &
	"IO_P9:P9," &
	"IO_P10:P10," &
	"IO_P13:P13," &
	"IO_P15:P15," &
	"IO_P16:P16," &
	"IO_P17:P17," &
	"IO_P18:P18," &
	"IO_P19:P19," &
	"IO_P20:P20," &
	"IO_P21:P21," &
	"IO_P22:P22," &
	"IO_P30:P30," &
	"IO_P31:P31," &
	"IO_P32:P32," &
	"IO_P34:P34," &
	"IO_P40:P40," &
	"IO_P41:P41," &
	"IO_P43:P43," &
	"IO_P44:P44," &
	"IO_P45:P45," &
	"IO_P46:P46," &
	"IO_P47:P47," &
	"IO_P53:P53," &
	"IO_P54:P54," &
	"IO_P55:P55," &
	"IO_P56:P56," &
	"IO_P57:P57," &
	"IO_P58:P58," &
	"IO_P59:P59," &
	"IO_P60:P60," &
	"IO_P62:P62," &
	"IO_P65:P65," &
	"IO_P66:P66," &
	"IO_P67:P67," &
	"IO_P68:P68," &
	"IO_P69:P69," &
	"IO_P70:P70," &
	"IO_P71:P71," &
	"IO_P72:P72," &
	"IO_P73:P73," &
	"IO_P74:P74," &
	"IO_P80:P80," &
	"IO_P81:P81," &
	"IO_P82:P82," &
	"IO_P83:P83," &
	"IO_P84:P84," &
	"IO_P86:P86," &
	"IO_P87:P87," &
	"IO_P93:P93," &
	"IO_P95:P95," &
	"IO_P96:P96," &
	"IO_P97:P97," &
	"IO_P98:P98";


attribute TAP_SCAN_IN    of TDI : signal is true;
attribute TAP_SCAN_MODE  of TMS : signal is true;
attribute TAP_SCAN_OUT   of TDO : signal is true;


attribute TAP_SCAN_CLOCK of TCK : signal is (33.0e6, BOTH);



attribute COMPLIANCE_PATTERNS of XC2S15_VQ100 : entity is
        "(PROGRAM, PWDNB) (11)";

attribute INSTRUCTION_LENGTH of XC2S15_VQ100 : entity is 5;

attribute INSTRUCTION_OPCODE of XC2S15_VQ100 : entity is
	"SAMPLE (00001)," &
	"INTEST (00111)," &
	"USERCODE (01000)," &
	"IDCODE (01001)," &
	"HIGHZ (01010)," &
	"JSTART (01100)," & -- Not available during configuration with another mode.
	"RESERVED (00110)," &
	"CFG_OUT (00100)," & -- Not available during configuration with another mode.
	"CFG_IN (00101)," & -- Not available during configuration with another mode.
	"USER2 (00011)," & -- Not available until after configuration
	"USER1 (00010)," & -- Not available until after configuration
	"EXTEST (00000)," &
	"BYPASS (11111)";


attribute INSTRUCTION_CAPTURE of XC2S15_VQ100 : entity is "XXX01";
-- Bit 4 of instruction capture is PROGRAM. Bit 3 is INIT.  Bit 2 is DONE.

  
-- If the device is configured, and a USER instruction is implemented
-- and not private to the FPGA designer, then it should be removed
-- from INSTRUCTION_PRIVATE, and the target register should be defined
-- in REGISTER_ACCESS.
 

 
attribute INSTRUCTION_PRIVATE of XC2S15_VQ100 : entity is
	"USER1," &
	"USER2," &
	"JSTART," &
	"CFG_IN," &
	"RESERVED," &
	"CFG_OUT";

 

 
attribute IDCODE_REGISTER of XC2S15_VQ100 : entity is
	"XXXX" &	-- version
	"0000011" &	-- family
	"000001000" &	-- array size
	"00001001001" &	-- manufacturer
	"1";		-- required by 1149.1

 

 
attribute USERCODE_REGISTER of XC2S15_VQ100 : entity is
	"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
 

 
attribute REGISTER_ACCESS of XC2S15_VQ100 : entity is
--	"<reg_name>[<length>] (USER1)," &
--	"<reg_name>[<length>] (USER2)," &
	"BYPASS (HIGHZ,BYPASS)," &
	"DEVICE_ID (USERCODE,IDCODE)," &
	"BOUNDARY (SAMPLE,INTEST,EXTEST)";

 

attribute BOUNDARY_LENGTH of XC2S15_VQ100 : entity is 302;

attribute BOUNDARY_REGISTER of XC2S15_VQ100 : entity is
-- cellnum (type, port, function, safe[, ccell, disval, disrslt])
	"   0 (BC_1, *, controlr, 1)," &
	"   1 (BC_1, IO_P80, output3, X, 0, 1, PULL0)," & --  PAD24
	"   2 (BC_1, IO_P80, input, X)," & --  PAD24
	"   3 (BC_1, *, controlr, 1)," &
	"   4 (BC_1, IO_P81, output3, X, 3, 1, PULL0)," & --  PAD23
	"   5 (BC_1, IO_P81, input, X)," & --  PAD23
	"   6 (BC_1, *, internal, 1)," & -- PAD22.T
	"   7 (BC_1, *, internal, X)," & -- PAD22.O
	"   8 (BC_1, *, internal, X)," & -- PAD22.I
	"   9 (BC_1, *, controlr, 1)," &
	"  10 (BC_1, IO_P82, output3, X, 9, 1, PULL0)," & --  PAD21
	"  11 (BC_1, IO_P82, input, X)," & --  PAD21
	"  12 (BC_1, *, controlr, 1)," &
	"  13 (BC_1, IO_P83, output3, X, 12, 1, PULL0)," & --  PAD20
	"  14 (BC_1, IO_P83, input, X)," & --  PAD20
	"  15 (BC_1, *, controlr, 1)," &
	"  16 (BC_1, IO_P84, output3, X, 15, 1, PULL0)," & --  PAD19
	"  17 (BC_1, IO_P84, input, X)," & --  PAD19
	"  18 (BC_1, *, internal, 1)," & -- PAD18.T
	"  19 (BC_1, *, internal, X)," & -- PAD18.O
	"  20 (BC_1, *, internal, X)," & -- PAD18.I
	"  21 (BC_1, *, internal, 1)," & -- PAD17.T
	"  22 (BC_1, *, internal, X)," & -- PAD17.O
	"  23 (BC_1, *, internal, X)," & -- PAD17.I
	"  24 (BC_1, *, controlr, 1)," &
	"  25 (BC_1, IO_P86, output3, X, 24, 1, PULL0)," & --  PAD16
	"  26 (BC_1, IO_P86, input, X)," & --  PAD16
	"  27 (BC_1, *, internal, 1)," & -- PAD15.T
	"  28 (BC_1, *, internal, X)," & -- PAD15.O
	"  29 (BC_1, *, internal, X)," & -- PAD15.I
	"  30 (BC_1, *, controlr, 1)," &
	"  31 (BC_1, IO_P87, output3, X, 30, 1, PULL0)," & --  PAD14
	"  32 (BC_1, IO_P87, input, X)," & --  PAD14
	"  33 (BC_1, *, internal, 1)," & -- PAD13.T
	"  34 (BC_1, *, internal, X)," & -- PAD13.O
	"  35 (BC_1, *, internal, X)," & -- PAD13.I
	"  36 (BC_1, GCK2_P88, input, X)," &
	"  37 (BC_1, GCK3_P91, input, X)," &
	"  38 (BC_1, *, internal, 1)," & -- PAD12.T
	"  39 (BC_1, *, internal, X)," & -- PAD12.O
	"  40 (BC_1, *, internal, X)," & -- PAD12.I
	"  41 (BC_1, *, internal, 1)," & -- PAD11.T
	"  42 (BC_1, *, internal, X)," & -- PAD11.O
	"  43 (BC_1, *, internal, X)," & -- PAD11.I
	"  44 (BC_1, *, internal, 1)," & -- PAD10.T
	"  45 (BC_1, *, internal, X)," & -- PAD10.O
	"  46 (BC_1, *, internal, X)," & -- PAD10.I
	"  47 (BC_1, *, controlr, 1)," &
	"  48 (BC_1, IO_P93, output3, X, 47, 1, PULL0)," & --  PAD9
	"  49 (BC_1, IO_P93, input, X)," & --  PAD9
	"  50 (BC_1, *, internal, 1)," & -- PAD8.T
	"  51 (BC_1, *, internal, X)," & -- PAD8.O
	"  52 (BC_1, *, internal, X)," & -- PAD8.I
	"  53 (BC_1, *, internal, 1)," & -- PAD7.T
	"  54 (BC_1, *, internal, X)," & -- PAD7.O
	"  55 (BC_1, *, internal, X)," & -- PAD7.I
	"  56 (BC_1, *, controlr, 1)," &
	"  57 (BC_1, IO_P95, output3, X, 56, 1, PULL0)," & --  PAD6
	"  58 (BC_1, IO_P95, input, X)," & --  PAD6
	"  59 (BC_1, *, controlr, 1)," &
	"  60 (BC_1, IO_P96, output3, X, 59, 1, PULL0)," & --  PAD5
	"  61 (BC_1, IO_P96, input, X)," & --  PAD5
	"  62 (BC_1, *, controlr, 1)," &
	"  63 (BC_1, IO_P97, output3, X, 62, 1, PULL0)," & --  PAD4
	"  64 (BC_1, IO_P97, input, X)," & --  PAD4
	"  65 (BC_1, *, internal, 1)," & -- PAD3.T
	"  66 (BC_1, *, internal, X)," & -- PAD3.O
	"  67 (BC_1, *, internal, X)," & -- PAD3.I
	"  68 (BC_1, *, controlr, 1)," &
	"  69 (BC_1, IO_P98, output3, X, 68, 1, PULL0)," & --  PAD2
	"  70 (BC_1, IO_P98, input, X)," & --  PAD2
	"  71 (BC_1, *, internal, 1)," & -- PAD1.T
	"  72 (BC_1, *, internal, X)," & -- PAD1.O
	"  73 (BC_1, *, internal, X)," & -- PAD1.I
	"  74 (BC_1, *, internal, 1)," & -- PAD96.T
	"  75 (BC_1, *, internal, X)," & -- PAD96.O
	"  76 (BC_1, *, internal, X)," & -- PAD96.I
	"  77 (BC_1, *, controlr, 1)," &
	"  78 (BC_1, IO_P3, output3, X, 77, 1, PULL0)," & --  PAD95
	"  79 (BC_1, IO_P3, input, X)," & --  PAD95
	"  80 (BC_1, *, internal, 1)," & -- PAD94.T
	"  81 (BC_1, *, internal, X)," & -- PAD94.O
	"  82 (BC_1, *, internal, X)," & -- PAD94.I
	"  83 (BC_1, *, controlr, 1)," &
	"  84 (BC_1, IO_P4, output3, X, 83, 1, PULL0)," & --  PAD93
	"  85 (BC_1, IO_P4, input, X)," & --  PAD93
	"  86 (BC_1, *, controlr, 1)," &
	"  87 (BC_1, IO_P5, output3, X, 86, 1, PULL0)," & --  PAD92
	"  88 (BC_1, IO_P5, input, X)," & --  PAD92
	"  89 (BC_1, *, controlr, 1)," &
	"  90 (BC_1, IO_P6, output3, X, 89, 1, PULL0)," & --  PAD91
	"  91 (BC_1, IO_P6, input, X)," & --  PAD91
	"  92 (BC_1, *, controlr, 1)," &
	"  93 (BC_1, IO_P7, output3, X, 92, 1, PULL0)," & --  PAD90
	"  94 (BC_1, IO_P7, input, X)," & --  PAD90
	"  95 (BC_1, *, internal, 1)," & -- PAD89.T
	"  96 (BC_1, *, internal, X)," & -- PAD89.O
	"  97 (BC_1, *, internal, X)," & -- PAD89.I
	"  98 (BC_1, *, controlr, 1)," &
	"  99 (BC_1, IO_P8, output3, X, 98, 1, PULL0)," & --  PAD88
	" 100 (BC_1, IO_P8, input, X)," & --  PAD88
	" 101 (BC_1, *, controlr, 1)," &
	" 102 (BC_1, IO_P9, output3, X, 101, 1, PULL0)," & --  PAD87
	" 103 (BC_1, IO_P9, input, X)," & --  PAD87
	" 104 (BC_1, *, internal, 1)," & -- PAD86.T
	" 105 (BC_1, *, internal, X)," & -- PAD86.O
	" 106 (BC_1, *, internal, X)," & -- PAD86.I
	" 107 (BC_1, *, controlr, 1)," &
	" 108 (BC_1, IO_P10, output3, X, 107, 1, PULL0)," & --  PAD85
	" 109 (BC_1, IO_P10, input, X)," & --  PAD85
	" 110 (BC_1, *, controlr, 1)," &
	" 111 (BC_1, IO_P13, output3, X, 110, 1, PULL0)," & --  PAD84
	" 112 (BC_1, IO_P13, input, X)," & --  PAD84
	" 113 (BC_1, *, internal, 1)," & -- PAD83.T
	" 114 (BC_1, *, internal, X)," & -- PAD83.O
	" 115 (BC_1, *, internal, X)," & -- PAD83.I
	" 116 (BC_1, *, controlr, 1)," &
	" 117 (BC_1, IO_P15, output3, X, 116, 1, PULL0)," & --  PAD82
	" 118 (BC_1, IO_P15, input, X)," & --  PAD82
	" 119 (BC_1, *, controlr, 1)," &
	" 120 (BC_1, IO_P16, output3, X, 119, 1, PULL0)," & --  PAD81
	" 121 (BC_1, IO_P16, input, X)," & --  PAD81
	" 122 (BC_1, *, internal, 1)," & -- PAD80.T
	" 123 (BC_1, *, internal, X)," & -- PAD80.O
	" 124 (BC_1, *, internal, X)," & -- PAD80.I
	" 125 (BC_1, *, controlr, 1)," &
	" 126 (BC_1, IO_P17, output3, X, 125, 1, PULL0)," & --  PAD79
	" 127 (BC_1, IO_P17, input, X)," & --  PAD79
	" 128 (BC_1, *, controlr, 1)," &
	" 129 (BC_1, IO_P18, output3, X, 128, 1, PULL0)," & --  PAD78
	" 130 (BC_1, IO_P18, input, X)," & --  PAD78
	" 131 (BC_1, *, controlr, 1)," &
	" 132 (BC_1, IO_P19, output3, X, 131, 1, PULL0)," & --  PAD77
	" 133 (BC_1, IO_P19, input, X)," & --  PAD77
	" 134 (BC_1, *, controlr, 1)," &
	" 135 (BC_1, IO_P20, output3, X, 134, 1, PULL0)," & --  PAD76
	" 136 (BC_1, IO_P20, input, X)," & --  PAD76
	" 137 (BC_1, *, internal, 1)," & -- PAD75.T
	" 138 (BC_1, *, internal, X)," & -- PAD75.O
	" 139 (BC_1, *, internal, X)," & -- PAD75.I
	" 140 (BC_1, *, controlr, 1)," &
	" 141 (BC_1, IO_P21, output3, X, 140, 1, PULL0)," & --  PAD74
	" 142 (BC_1, IO_P21, input, X)," & --  PAD74
	" 143 (BC_1, *, controlr, 1)," &
	" 144 (BC_1, IO_P22, output3, X, 143, 1, PULL0)," & --  PAD73
	" 145 (BC_1, IO_P22, input, X)," & --  PAD73
	" 146 (BC_1, M1_P23, input, X)," &
	" 147 (BC_1, M0_P25, input, X)," &
	" 148 (BC_1, M2_P27, input, X)," &
	" 149 (BC_1, *, internal, 1)," & -- PAD72.T
	" 150 (BC_1, *, internal, X)," & -- PAD72.O
	" 151 (BC_1, *, internal, X)," & -- PAD72.I
	" 152 (BC_1, *, internal, 1)," & -- PAD71.T
	" 153 (BC_1, *, internal, X)," & -- PAD71.O
	" 154 (BC_1, *, internal, X)," & -- PAD71.I
	" 155 (BC_1, *, internal, 1)," & -- PAD70.T
	" 156 (BC_1, *, internal, X)," & -- PAD70.O
	" 157 (BC_1, *, internal, X)," & -- PAD70.I
	" 158 (BC_1, *, controlr, 1)," &
	" 159 (BC_1, IO_P30, output3, X, 158, 1, PULL0)," & --  PAD69
	" 160 (BC_1, IO_P30, input, X)," & --  PAD69
	" 161 (BC_1, *, controlr, 1)," &
	" 162 (BC_1, IO_P31, output3, X, 161, 1, PULL0)," & --  PAD68
	" 163 (BC_1, IO_P31, input, X)," & --  PAD68
	" 164 (BC_1, *, controlr, 1)," &
	" 165 (BC_1, IO_P32, output3, X, 164, 1, PULL0)," & --  PAD67
	" 166 (BC_1, IO_P32, input, X)," & --  PAD67
	" 167 (BC_1, *, internal, 1)," & -- PAD66.T
	" 168 (BC_1, *, internal, X)," & -- PAD66.O
	" 169 (BC_1, *, internal, X)," & -- PAD66.I
	" 170 (BC_1, *, internal, 1)," & -- PAD65.T
	" 171 (BC_1, *, internal, X)," & -- PAD65.O
	" 172 (BC_1, *, internal, X)," & -- PAD65.I
	" 173 (BC_1, *, controlr, 1)," &
	" 174 (BC_1, IO_P34, output3, X, 173, 1, PULL0)," & --  PAD64
	" 175 (BC_1, IO_P34, input, X)," & --  PAD64
	" 176 (BC_1, *, internal, 1)," & -- PAD63.T
	" 177 (BC_1, *, internal, X)," & -- PAD63.O
	" 178 (BC_1, *, internal, X)," & -- PAD63.I
	" 179 (BC_1, *, internal, 1)," & -- PAD62.T
	" 180 (BC_1, *, internal, X)," & -- PAD62.O
	" 181 (BC_1, *, internal, X)," & -- PAD62.I
	" 182 (BC_1, *, internal, 1)," & -- PAD61.T
	" 183 (BC_1, *, internal, X)," & -- PAD61.O
	" 184 (BC_1, *, internal, X)," & -- PAD61.I
	" 185 (BC_1, GCK1_P36, input, X)," &
	" 186 (BC_1, GCK0_P39, input, X)," &
	" 187 (BC_1, *, internal, 1)," & -- PAD60.T
	" 188 (BC_1, *, internal, X)," & -- PAD60.O
	" 189 (BC_1, *, internal, X)," & -- PAD60.I
	" 190 (BC_1, *, controlr, 1)," &
	" 191 (BC_1, IO_P40, output3, X, 190, 1, PULL0)," & --  PAD59
	" 192 (BC_1, IO_P40, input, X)," & --  PAD59
	" 193 (BC_1, *, internal, 1)," & -- PAD58.T
	" 194 (BC_1, *, internal, X)," & -- PAD58.O
	" 195 (BC_1, *, internal, X)," & -- PAD58.I
	" 196 (BC_1, *, controlr, 1)," &
	" 197 (BC_1, IO_P41, output3, X, 196, 1, PULL0)," & --  PAD57
	" 198 (BC_1, IO_P41, input, X)," & --  PAD57
	" 199 (BC_1, *, internal, 1)," & -- PAD56.T
	" 200 (BC_1, *, internal, X)," & -- PAD56.O
	" 201 (BC_1, *, internal, X)," & -- PAD56.I
	" 202 (BC_1, *, internal, 1)," & -- PAD55.T
	" 203 (BC_1, *, internal, X)," & -- PAD55.O
	" 204 (BC_1, *, internal, X)," & -- PAD55.I
	" 205 (BC_1, *, controlr, 1)," &
	" 206 (BC_1, IO_P43, output3, X, 205, 1, PULL0)," & --  PAD54
	" 207 (BC_1, IO_P43, input, X)," & --  PAD54
	" 208 (BC_1, *, controlr, 1)," &
	" 209 (BC_1, IO_P44, output3, X, 208, 1, PULL0)," & --  PAD53
	" 210 (BC_1, IO_P44, input, X)," & --  PAD53
	" 211 (BC_1, *, controlr, 1)," &
	" 212 (BC_1, IO_P45, output3, X, 211, 1, PULL0)," & --  PAD52
	" 213 (BC_1, IO_P45, input, X)," & --  PAD52
	" 214 (BC_1, *, internal, 1)," & -- PAD51.T
	" 215 (BC_1, *, internal, X)," & -- PAD51.O
	" 216 (BC_1, *, internal, X)," & -- PAD51.I
	" 217 (BC_1, *, controlr, 1)," &
	" 218 (BC_1, IO_P46, output3, X, 217, 1, PULL0)," & --  PAD50
	" 219 (BC_1, IO_P46, input, X)," & --  PAD50
	" 220 (BC_1, *, controlr, 1)," &
	" 221 (BC_1, IO_P47, output3, X, 220, 1, PULL0)," & --  PAD49
	" 222 (BC_1, IO_P47, input, X)," & --  PAD49
	" 223 (BC_1, *, controlr, 1)," &
	" 224 (BC_1, DONE_P49, output3, X, 223, 1, PULL1)," &
	" 225 (BC_1, DONE_P49, input, X)," &
	" 226 (BC_1, *, internal, 1)," & -- PROGRAM_B.I
	" 227 (BC_1, *, controlr, 1)," &
	" 228 (BC_1, INIT_P52, output3, X, 227, 1, PULL1)," & --  PAD48
	" 229 (BC_1, INIT_P52, input, X)," & --  PAD48
	" 230 (BC_1, *, controlr, 1)," &
	" 231 (BC_1, IO_P53, output3, X, 230, 1, PULL0)," & --  PAD47
	" 232 (BC_1, IO_P53, input, X)," & --  PAD47
	" 233 (BC_1, *, internal, 1)," & -- PAD46.T
	" 234 (BC_1, *, internal, X)," & -- PAD46.O
	" 235 (BC_1, *, internal, X)," & -- PAD46.I
	" 236 (BC_1, *, controlr, 1)," &
	" 237 (BC_1, IO_P54, output3, X, 236, 1, PULL0)," & --  PAD45
	" 238 (BC_1, IO_P54, input, X)," & --  PAD45
	" 239 (BC_1, *, controlr, 1)," &
	" 240 (BC_1, IO_P55, output3, X, 239, 1, PULL0)," & --  PAD44
	" 241 (BC_1, IO_P55, input, X)," & --  PAD44
	" 242 (BC_1, *, controlr, 1)," &
	" 243 (BC_1, IO_P56, output3, X, 242, 1, PULL0)," & --  PAD43
	" 244 (BC_1, IO_P56, input, X)," & --  PAD43
	" 245 (BC_1, *, controlr, 1)," &
	" 246 (BC_1, IO_P57, output3, X, 245, 1, PULL0)," & --  PAD42
	" 247 (BC_1, IO_P57, input, X)," & --  PAD42
	" 248 (BC_1, *, controlr, 1)," &
	" 249 (BC_1, IO_P58, output3, X, 248, 1, PULL0)," & --  PAD41
	" 250 (BC_1, IO_P58, input, X)," & --  PAD41
	" 251 (BC_1, *, controlr, 1)," &
	" 252 (BC_1, IO_P59, output3, X, 251, 1, PULL0)," & --  PAD40
	" 253 (BC_1, IO_P59, input, X)," & --  PAD40
	" 254 (BC_1, *, controlr, 1)," &
	" 255 (BC_1, IO_P60, output3, X, 254, 1, PULL0)," & --  PAD39
	" 256 (BC_1, IO_P60, input, X)," & --  PAD39
	" 257 (BC_1, *, internal, 1)," & -- PAD38.T
	" 258 (BC_1, *, internal, X)," & -- PAD38.O
	" 259 (BC_1, *, internal, X)," & -- PAD38.I
	" 260 (BC_1, *, controlr, 1)," &
	" 261 (BC_1, IO_P62, output3, X, 260, 1, PULL0)," & --  PAD37
	" 262 (BC_1, IO_P62, input, X)," & --  PAD37
	" 263 (BC_1, *, controlr, 1)," &
	" 264 (BC_1, IO_P65, output3, X, 263, 1, PULL0)," & --  PAD36
	" 265 (BC_1, IO_P65, input, X)," & --  PAD36
	" 266 (BC_1, *, internal, 1)," & -- PAD35.T
	" 267 (BC_1, *, internal, X)," & -- PAD35.O
	" 268 (BC_1, *, internal, X)," & -- PAD35.I
	" 269 (BC_1, *, controlr, 1)," &
	" 270 (BC_1, IO_P66, output3, X, 269, 1, PULL0)," & --  PAD34
	" 271 (BC_1, IO_P66, input, X)," & --  PAD34
	" 272 (BC_1, *, controlr, 1)," &
	" 273 (BC_1, IO_P67, output3, X, 272, 1, PULL0)," & --  PAD33
	" 274 (BC_1, IO_P67, input, X)," & --  PAD33
	" 275 (BC_1, *, controlr, 1)," &
	" 276 (BC_1, IO_P68, output3, X, 275, 1, PULL0)," & --  PAD32
	" 277 (BC_1, IO_P68, input, X)," & --  PAD32
	" 278 (BC_1, *, controlr, 1)," &
	" 279 (BC_1, IO_P69, output3, X, 278, 1, PULL0)," & --  PAD31
	" 280 (BC_1, IO_P69, input, X)," & --  PAD31
	" 281 (BC_1, *, controlr, 1)," &
	" 282 (BC_1, IO_P70, output3, X, 281, 1, PULL0)," & --  PAD30
	" 283 (BC_1, IO_P70, input, X)," & --  PAD30
	" 284 (BC_1, *, controlr, 1)," &
	" 285 (BC_1, IO_P71, output3, X, 284, 1, PULL0)," & --  PAD29
	" 286 (BC_1, IO_P71, input, X)," & --  PAD29
	" 287 (BC_1, *, controlr, 1)," &
	" 288 (BC_1, IO_P72, output3, X, 287, 1, PULL0)," & --  PAD28
	" 289 (BC_1, IO_P72, input, X)," & --  PAD28
	" 290 (BC_1, *, internal, 1)," & -- PAD27.T
	" 291 (BC_1, *, internal, X)," & -- PAD27.O
	" 292 (BC_1, *, internal, X)," & -- PAD27.I
	" 293 (BC_1, *, controlr, 1)," &
	" 294 (BC_1, IO_P73, output3, X, 293, 1, PULL0)," & --  PAD26
	" 295 (BC_1, IO_P73, input, X)," & --  PAD26
	" 296 (BC_1, *, controlr, 1)," &
	" 297 (BC_1, IO_P74, output3, X, 296, 1, PULL0)," & --  PAD25
	" 298 (BC_1, IO_P74, input, X)," & --  PAD25
	" 299 (BC_1, *, controlr, 1)," &
	" 300 (BC_1, CCLK_P75, output3, X, 299, 1, PULL1)," &
	" 301 (BC_1, CCLK_P75, input, X)";

	
attribute DESIGN_WARNING of XC2S15_VQ100 : entity is
        "This is a preliminary BSDL file which has not been verified." &
        "This BSDL file must be modified by the FPGA designer in order to" &
                "reflect post-configuration behavior (if any)." &
        "The boundary scan test vectors must keep the PROGRAM pin" &
                "either 3-stated or driving high.  If the PROGRAM pin" &
                "is driven low through any means, the TAP controller" &
                "will reset." &
        "The boundary scan test vectors must keep the PWDNB pin" &
                "either 3-stated or driving high.  If the PWDNB pin" &
                "is driven low through any means, the TAP controller" &
                "will reset." &
        "The output and tristate capture values are not valid until after" &
                "the device is configured." &
        "The tristate control is not captured properly when" &
                "GTS is activated." &
        "In EXTEST, output and tristate values are not captured in the" &
                "Capture-DR state - those register cells are unchanged." &
        "In INTEST, the pin input values are not captured in the" &
                "Capture-DR state - those register cells are unchanged." &
	"The disable values of a 3-stated I/O in this file" &
		"correspond with configuration mode pin settings without" &
		"pre-configuration pull-up resistors.  For the" &
                "modes with pull-up resistors, change PULL0 to PULL1." &
	"In EXTEST, the determination of whether this is" &
		"a pull-up configuration mode depends upon the values" &
		"shifted in for the mode pin register cells.";

end XC2S15_VQ100;