-- MODIFIED BY fix_bsdl
-- M O T O R O L A FlexIOR Design Compiler Software
--
-- Revision History:
-- 1.4 10-18-02 Changed Version number to '0010' -KGP
--
-- Jtag BSDL File Generated by FlexIOR Design Compiler
-- using the cdr2_device_chassis.flex template file
--
-- Package type: 196 lead Ball Grid Array (VF suffix)
entity MCF5272_1K75N is
generic (PHYSICAL_PIN_MAP : string := "BGA_VF");
-- KEY:
-- in = input only
-- out = three-state output or open-drain
-- buffer = two-state output
-- inout = bidirectional
-- linkage = pins not included in jtag chain
-- i.e. power, ground, clocks etc.
port ( EXTAL:in bit;
RESETB:in bit;
DRESETB:in bit;
RSTOB:out bit;
TESTB:in bit;
BS0B:inout bit;
BS1B:inout bit;
BS2B:inout bit;
BS3B:inout bit;
OEB:inout bit;
WEB:inout bit;
CS0B:inout bit;
CS1B:out bit;
CS2B:out bit;
CS3B:out bit;
CS4B:out bit;
CS5B:out bit;
CS6B:out bit;
SDRASB:inout bit;
SDCASB:inout bit;
SDCLK:inout bit;
SDCLKE:inout bit;
SDCSB:inout bit;
SDWEB:inout bit;
SDA10:inout bit;
SDBA0:inout bit;
SDBA1:inout bit;
D0:inout bit;
D1:inout bit;
D2:inout bit;
D3:inout bit;
D4:inout bit;
D5:inout bit;
D6:inout bit;
D7:inout bit;
D8:inout bit;
D9:inout bit;
D10:inout bit;
D11:inout bit;
D12:inout bit;
D13:inout bit;
D14:inout bit;
D15:inout bit;
D16:inout bit;
D17:inout bit;
D18:inout bit;
D19:inout bit;
D20:inout bit;
D21:inout bit;
D22:inout bit;
D23:inout bit;
D24:inout bit;
D25:inout bit;
D26:inout bit;
D27:inout bit;
D28:inout bit;
D29:inout bit;
D30:inout bit;
D31:inout bit;
A0:inout bit;
A1:inout bit;
A2:inout bit;
A3:inout bit;
A4:inout bit;
A5:out bit;
A6:out bit;
A7:out bit;
A8:out bit;
A9:out bit;
A10:out bit;
A11:inout bit;
A12:inout bit;
A13:inout bit;
A14:inout bit;
A15:inout bit;
A16:inout bit;
A17:inout bit;
A18:inout bit;
A19:inout bit;
A20:inout bit;
A21:inout bit;
A22:inout bit;
TDO:out bit;
TDI:in bit;
TMS:in bit;
TCK:in bit;
TRSTB:in bit;
DTEAB:in bit;
MTMOD:linkage bit;
DDATA0:inout bit;
DDATA1:inout bit;
DDATA2:inout bit;
DDATA3:inout bit;
PST0:inout bit;
PST1:inout bit;
PST2:inout bit;
PST3:inout bit;
PA0:inout bit;
PA1:inout bit;
PA2:inout bit;
PA3:inout bit;
PA4:inout bit;
PA5:inout bit;
PA6:inout bit;
PA7:inout bit;
O1F4K:inout bit;
O192K:inout bit;
O1FCK:inout bit;
SB1RD:inout bit;
SB2RD:inout bit;
SDSRD:inout bit;
SB1SD:inout bit;
SB2SD:inout bit;
SDQSD:inout bit;
DFSC2:inout bit;
DFSC3:inout bit;
FSC1:inout bit;
DCL1:inout bit;
DREQ1:inout bit;
DGNT1:inout bit;
DOUT1:out bit;
DIN1:inout bit;
INT4:inout bit;
PB5:inout bit;
PB6:inout bit;
TXD1:inout bit;
RXD1:inout bit;
CTS1:inout bit;
RTS1:inout bit;
CLK1:inout bit;
UEXTAL:in bit;
USBH:linkage bit;
USBL:linkage bit;
TIN1:inout bit;
TOUT1:inout bit;
INT1:inout bit;
INT2:inout bit;
INT3:inout bit;
SPMOSI:inout bit;
SPMISO:inout bit;
SPCLK:inout bit;
SPCS0B:inout bit;
PWM1:inout bit;
PWM2:inout bit;
PWM3:inout bit;
ETXCLK:in bit;
ETXD:out bit;
ECOL:in bit;
ERXDV:inout bit;
ERXCLK:in bit;
ERXD:inout bit;
ETXEN:out bit;
ETXD3:inout bit;
ETXD2:inout bit;
ETXD1:inout bit;
ERXD3:inout bit;
ERXD2:inout bit;
ERXD1:inout bit;
ERXERR:inout bit;
EMDC:inout bit;
EMDIO:inout bit;
ETXERR:inout bit;
ECRS:inout bit;
HIZ:in bit;
GND:linkage bit_vector (1 to 15);
VDD:linkage bit_vector (1 to 16));
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of MCF5272_1K75N : entity is "STD_1149_1_1993";
attribute PIN_MAP of MCF5272_1K75N : entity is PHYSICAL_PIN_MAP;
constant BGA_VF : PIN_MAP_STRING :=
"EXTAL: M14, " &
"RESETB: M12, " &
"DRESETB: N12, " &
"RSTOB: F4, " &
"TESTB: E6, " &
"BS0B: A9, " &
"BS1B: C8, " &
"BS2B: E12, " &
"BS3B: E13, " &
"OEB: P13, " &
"WEB: P14, " &
"CS0B: K9, " &
"CS1B: K10, " &
"CS2B: P11, " &
"CS3B: N11, " &
"CS4B: M11, " &
"CS5B: L11, " &
"CS6B: P12, " &
"SDRASB: A10, " &
"SDCASB: C9, " &
"SDCLK: E14, " &
"SDCLKE: D13, " &
"SDCSB: B10, " &
"SDWEB: B9, " &
"SDA10: D14, " &
"SDBA0: J14, " &
"SDBA1: H12, " &
"D0: L12, " &
"D1: L13, " &
"D2: L14, " &
"D3: K11, " &
"D4: K12, " &
"D5: K13, " &
"D6: K14, " &
"D7: J11, " &
"D8: J12, " &
"D9: J13, " &
"D10: H11, " &
"D11: G11, " &
"D12: F11, " &
"D13: E11, " &
"D14: D11, " &
"D15: E10, " &
"D16: A5, " &
"D17: B6, " &
"D18: A6, " &
"D19: C7, " &
"D20: B7, " &
"D21: A7, " &
"D22: A8, " &
"D23: B8, " &
"D24: F12, " &
"D25: F13, " &
"D26: F14, " &
"D27: G12, " &
"D28: G13, " &
"D29: G14, " &
"D30: H14, " &
"D31: H13, " &
"A0: D10, " &
"A1: B12, " &
"A2: A12, " &
"A3: A13, " &
"A4: A14, " &
"A5: B13, " &
"A6: B14, " &
"A7: C12, " &
"A8: C13, " &
"A9: C14, " &
"A10: D12, " &
"A11: C11, " &
"A12: B11, " &
"A13: A11, " &
"A14: C10, " &
"A15: D9, " &
"A16: D8, " &
"A17: D7, " &
"A18: C6, " &
"A19: D6, " &
"A20: B5, " &
"A21: C5, " &
"A22: E9, " &
"TDO: D5, " &
"TDI: A4, " &
"TMS: B4, " &
"TCK: C4, " &
"TRSTB: D4, " &
"DTEAB: A3, " &
"MTMOD: B3, " &
"DDATA0: C3, " &
"DDATA1: A2, " &
"DDATA2: B2, " &
"DDATA3: A1, " &
"PST0: B1, " &
"PST1: C2, " &
"PST2: C1, " &
"PST3: D3, " &
"PA0: D2, " &
"PA1: D1, " &
"PA2: E5, " &
"PA3: E4, " &
"PA4: E3, " &
"PA5: E2, " &
"PA6: E1, " &
"PA7: P1, " &
"O1F4K: J2, " &
"O192K: J3, " &
"O1FCK: J4, " &
"SB1RD: K1, " &
"SB2RD: K2, " &
"SDSRD: K3, " &
"SB1SD: K4, " &
"SB2SD: K5, " &
"SDQSD: L1, " &
"DFSC2: L2, " &
"DFSC3: L3, " &
"FSC1: L4, " &
"DCL1: M1, " &
"DREQ1: M2, " &
"DGNT1: M3, " &
"DOUT1: N1, " &
"DIN1: N2, " &
"INT4: P2, " &
"PB5: F3, " &
"PB6: G4, " &
"TXD1: H4, " &
"RXD1: H1, " &
"CTS1: H2, " &
"RTS1: H3, " &
"CLK1: G3, " &
"UEXTAL: J1, " &
"USBH: F1, " &
"USBL: F2, " &
"TIN1: L6, " &
"TOUT1: M6, " &
"INT1: M4, " &
"INT2: P3, " &
"INT3: N3, " &
"SPMOSI: N4, " &
"SPMISO: P4, " &
"SPCLK: L5, " &
"SPCS0B: M5, " &
"PWM1: N5, " &
"PWM2: P5, " &
"PWM3: K6, " &
"ETXCLK: L7, " &
"ETXD: N6, " &
"ECOL: P6, " &
"ERXDV: M7, " &
"ERXCLK: N7, " &
"ERXD: P7, " &
"ETXEN: P8, " &
"ETXD3: N8, " &
"ETXD2: M8, " &
"ETXD1: L8, " &
"ERXD3: P9, " &
"ERXD2: N9, " &
"ERXD1: M9, " &
"ERXERR: L9, " &
"EMDC: P10, " &
"EMDIO: N10, " &
"ETXERR: M10, " &
"ECRS: L10, " &
"HIZ: N14, " &
"GND: ( E7, E8, F7, F8, G2, G6, G7, G8, G9, H6, H7, H8, H9, J7, J8 ), " &
"VDD: ( F5, F6, F9, F10, G1, G5, G10, H5, H10, J5, J6, J9, J10, K7, K8, N13) ";
attribute TAP_SCAN_RESET of TRSTB : signal is true;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute COMPLIANCE_PATTERNS of MCF5272_1K75N : entity is
"(HIZ) (1)";
attribute INSTRUCTION_LENGTH of MCF5272_1K75N : entity is 4;
attribute INSTRUCTION_OPCODE of MCF5272_1K75N : entity is
"EXTEST (0000)," &
"SAMPLE (0010)," &
"IDCODE (0001)," &
"CLAMP (1100)," &
"HIGHZ (1001)," &
"RESERVED1 (0100)," &
"RESERVED2 (1000)," &
"BYPASS (1111)";
attribute INSTRUCTION_CAPTURE of MCF5272_1K75N : entity is "0001";
attribute INSTRUCTION_PRIVATE of MCF5272_1K75N : entity is "RESERVED1, RESERVED2";
attribute IDCODE_REGISTER of MCF5272_1K75N : entity is
"0010" & -- version
"010001" & -- manufacturer's use
"0000000011" & -- sequence number
"00000001110" & -- manufacturer identity
"1"; -- 1149.1 requirement
attribute REGISTER_ACCESS of MCF5272_1K75N : entity is
"BOUNDARY (RESERVED1,RESERVED2)" ;
attribute BOUNDARY_LENGTH of MCF5272_1K75N : entity is 265;
-- KEY:
-- cell:
-- BC_1 = output cells and control cells
-- BC_4 = input cells
-- BC_6 = bidirectional cells
-- func:
-- output2 = two-state output
-- bidir = bidirectional
-- input = input only
-- control = control cell with no reset or .pu, .pd or .de cell
-- internal = unused cells or rtc_osc_ENB, rtc_osc_CLK, main_osc_ENB
-- or main_osc_DI cells
-- safe:
-- value which makes a control cell into an input.
-- 0 for control, X for all else
-- ccell:
-- number of controlling cell
-- dis:
-- value of controlling cell to make it an input (disable cell,
-- same as safe value of control cell controlling it.
-- rslt:
-- result when disabled - Weak1 for open drains, DTACKB and RXD1,
-- Z for all else. (All other pull-ups or pull-downs are
-- programmable, controlled by .pu or .pd cells.)
attribute BOUNDARY_REGISTER of MCF5272_1K75N : entity is
-- num cell port func safe [ccell dis rslt]
"264 (BC_4, EXTAL, input, X)," &
"263 (BC_4, RESETB, input, X)," &
"262 (BC_4, DRESETB, input, X)," &
"261 (BC_1, *, control, 0)," & -- RSTOB.ctl
"260 (BC_1, RSTOB, output3, X, 261, 0, Z)," &
"259 (BC_4, TESTB, input, X)," &
"258 (BC_1, *, control, 0)," & -- BS0B.ctl
"257 (BC_6, BS0B, bidir, X, 258, 0, Z)," &
"256 (BC_1, *, control, 0)," & -- BS1B.ctl
"255 (BC_6, BS1B, bidir, X, 256, 0, Z)," &
"254 (BC_6, BS2B, bidir, X, 256, 0, Z)," &
"253 (BC_6, BS3B, bidir, X, 256, 0, Z)," &
"252 (BC_6, OEB, bidir, X, 256, 0, Z)," &
"251 (BC_6, WEB, bidir, X, 256, 0, Z)," &
"250 (BC_1, *, control, 0)," & -- CS0B.ctl
"249 (BC_6, CS0B, bidir, X, 250, 0, Z)," &
"248 (BC_1, CS1B, output3, X, 261, 0, Z)," &
"247 (BC_1, CS2B, output3, X, 261, 0, Z)," &
"246 (BC_1, CS3B, output3, X, 261, 0, Z)," &
"245 (BC_1, CS4B, output3, X, 261, 0, Z)," &
"244 (BC_1, CS5B, output3, X, 261, 0, Z)," &
"243 (BC_1, CS6B, output3, X, 261, 0, Z)," &
"242 (BC_1, *, control, 0)," & -- SDRASB.ctl
"241 (BC_6, SDRASB, bidir, X, 242, 0, Z)," &
"240 (BC_6, SDCASB, bidir, X, 242, 0, Z)," &
"239 (BC_1, *, control, 0)," & -- SDCLK.ctl
"238 (BC_6, SDCLK, bidir, X, 239, 0, Z)," &
"237 (BC_6, SDCLKE, bidir, X, 242, 0, Z)," &
"236 (BC_6, SDCSB, bidir, X, 242, 0, Z)," &
"235 (BC_6, SDWEB, bidir, X, 242, 0, Z)," &
"234 (BC_6, SDA10, bidir, X, 242, 0, Z)," &
"233 (BC_6, SDBA0, bidir, X, 242, 0, Z)," &
"232 (BC_6, SDBA1, bidir, X, 242, 0, Z)," &
"231 (BC_1, *, internal, X)," & -- DRQ.ctl
"230 (BC_1, *, internal, X)," & -- DRQ
"229 (BC_1, *, internal, X)," & -- DACK.ctl
"228 (BC_1, *, internal, X)," & -- DACK
"227 (BC_1, *, internal, X)," & -- DACK.pu
"226 (BC_1, *, internal, X)," & -- TC
"225 (BC_1, *, control, 0)," & -- D0.ctl
"224 (BC_6, D0, bidir, X, 225, 0, Z)," &
"223 (BC_1, *, internal, X)," & -- D0.pu
"222 (BC_1, *, control, 0)," & -- D1.ctl
"221 (BC_6, D1, bidir, X, 222, 0, Z)," &
"220 (BC_1, *, control, 0)," & -- D2.ctl
"219 (BC_6, D2, bidir, X, 220, 0, Z)," &
"218 (BC_1, *, control, 0)," & -- D3.ctl
"217 (BC_6, D3, bidir, X, 218, 0, Z)," &
"216 (BC_1, *, control, 0)," & -- D4.ctl
"215 (BC_6, D4, bidir, X, 216, 0, Z)," &
"214 (BC_1, *, control, 0)," & -- D5.ctl
"213 (BC_6, D5, bidir, X, 214, 0, Z)," &
"212 (BC_1, *, control, 0)," & -- D6.ctl
"211 (BC_6, D6, bidir, X, 212, 0, Z)," &
"210 (BC_1, *, control, 0)," & -- D7.ctl
"209 (BC_6, D7, bidir, X, 210, 0, Z)," &
"208 (BC_1, *, control, 0)," & -- D8.ctl
"207 (BC_6, D8, bidir, X, 208, 0, Z)," &
"206 (BC_1, *, control, 0)," & -- D9.ctl
"205 (BC_6, D9, bidir, X, 206, 0, Z)," &
"204 (BC_1, *, control, 0)," & -- D10.ctl
"203 (BC_6, D10, bidir, X, 204, 0, Z)," &
"202 (BC_1, *, control, 0)," & -- D11.ctl
"201 (BC_6, D11, bidir, X, 202, 0, Z)," &
"200 (BC_1, *, control, 0)," & -- D12.ctl
"199 (BC_6, D12, bidir, X, 200, 0, Z)," &
"198 (BC_1, *, control, 0)," & -- D13.ctl
"197 (BC_6, D13, bidir, X, 198, 0, Z)," &
"196 (BC_1, *, control, 0)," & -- D14.ctl
"195 (BC_6, D14, bidir, X, 196, 0, Z)," &
"194 (BC_1, *, control, 0)," & -- D15.ctl
"193 (BC_6, D15, bidir, X, 194, 0, Z)," &
"192 (BC_1, *, control, 0)," & -- D16.ctl
"191 (BC_6, D16, bidir, X, 192, 0, Z)," &
"190 (BC_6, D17, bidir, X, 192, 0, Z)," &
"189 (BC_6, D18, bidir, X, 192, 0, Z)," &
"188 (BC_6, D19, bidir, X, 192, 0, Z)," &
"187 (BC_6, D20, bidir, X, 192, 0, Z)," &
"186 (BC_6, D21, bidir, X, 192, 0, Z)," &
"185 (BC_6, D22, bidir, X, 192, 0, Z)," &
"184 (BC_6, D23, bidir, X, 192, 0, Z)," &
"183 (BC_6, D24, bidir, X, 192, 0, Z)," &
"182 (BC_6, D25, bidir, X, 192, 0, Z)," &
"181 (BC_6, D26, bidir, X, 192, 0, Z)," &
"180 (BC_6, D27, bidir, X, 192, 0, Z)," &
"179 (BC_6, D28, bidir, X, 192, 0, Z)," &
"178 (BC_6, D29, bidir, X, 192, 0, Z)," &
"177 (BC_6, D30, bidir, X, 192, 0, Z)," &
"176 (BC_6, D31, bidir, X, 192, 0, Z)," &
"175 (BC_1, *, control, 0)," & -- A0.ctl
"174 (BC_6, A0, bidir, X, 175, 0, Z)," &
"173 (BC_1, *, control, 0)," & -- A1.ctl
"172 (BC_6, A1, bidir, X, 173, 0, Z)," &
"171 (BC_1, *, control, 0)," & -- A2.ctl
"170 (BC_6, A2, bidir, X, 171, 0, Z)," &
"169 (BC_1, *, control, 0)," & -- A3.ctl
"168 (BC_6, A3, bidir, X, 169, 0, Z)," &
"167 (BC_1, *, internal, X)," & -- A3.pu
"166 (BC_6, A4, bidir, X, 169, 0, Z)," &
"165 (BC_1, *, control, 0)," & -- A5.ctl
"164 (BC_1, A5, output3, X, 165, 0, Z)," &
"163 (BC_1, A6, output3, X, 165, 0, Z)," &
"162 (BC_1, A7, output3, X, 165, 0, Z)," &
"161 (BC_1, A8, output3, X, 165, 0, Z)," &
"160 (BC_1, *, control, 0)," & -- A9.ctl
"159 (BC_1, A9, output3, X, 160, 0, Z)," &
"158 (BC_1, A10, output3, X, 160, 0, Z)," &
"157 (BC_1, *, control, 0)," & -- A11.ctl
"156 (BC_6, A11, bidir, X, 157, 0, Z)," &
"155 (BC_6, A12, bidir, X, 157, 0, Z)," &
"154 (BC_6, A13, bidir, X, 157, 0, Z)," &
"153 (BC_6, A14, bidir, X, 157, 0, Z)," &
"152 (BC_1, *, control, 0)," & -- A15.ctl
"151 (BC_6, A15, bidir, X, 152, 0, Z)," &
"150 (BC_6, A16, bidir, X, 157, 0, Z)," &
"149 (BC_6, A17, bidir, X, 157, 0, Z)," &
"148 (BC_6, A18, bidir, X, 157, 0, Z)," &
"147 (BC_6, A19, bidir, X, 157, 0, Z)," &
"146 (BC_1, *, control, 0)," & -- A20.ctl
"145 (BC_6, A20, bidir, X, 146, 0, Z)," &
"144 (BC_6, A21, bidir, X, 146, 0, Z)," &
"143 (BC_6, A22, bidir, X, 146, 0, Z)," &
"142 (BC_4, DTEAB, input, X)," &
"141 (BC_1, *, control, 0)," & -- DDATA0.ctl
"140 (BC_6, DDATA0, bidir, X, 141, 0, Z)," &
"139 (BC_6, DDATA1, bidir, X, 141, 0, Z)," &
"138 (BC_6, DDATA2, bidir, X, 141, 0, Z)," &
"137 (BC_1, *, control, 0)," & -- DDATA3.ctl
"136 (BC_6, DDATA3, bidir, X, 137, 0, Z)," &
"135 (BC_6, PST0, bidir, X, 137, 0, Z)," &
"134 (BC_6, PST1, bidir, X, 137, 0, Z)," &
"133 (BC_1, *, control, 0)," & -- PST2.ctl
"132 (BC_6, PST2, bidir, X, 133, 0, Z)," &
"131 (BC_6, PST3, bidir, X, 133, 0, Z)," &
"130 (BC_1, *, control, 0)," & -- PA0.ctl
"129 (BC_6, PA0, bidir, X, 130, 0, Z)," &
"128 (BC_1, *, internal, X)," & -- PA0.pu
"127 (BC_1, *, control, 0)," & -- PA1.ctl
"126 (BC_6, PA1, bidir, X, 127, 0, Z)," &
"125 (BC_1, *, control, 0)," & -- PA2.ctl
"124 (BC_6, PA2, bidir, X, 125, 0, Z)," &
"123 (BC_1, *, control, 0)," & -- PA3.ctl
"122 (BC_6, PA3, bidir, X, 123, 0, Z)," &
"121 (BC_1, *, control, 0)," & -- PA4.ctl
"120 (BC_6, PA4, bidir, X, 121, 0, Z)," &
"119 (BC_1, *, control, 0)," & -- PA5.ctl
"118 (BC_6, PA5, bidir, X, 119, 0, Z)," &
"117 (BC_1, *, control, 0)," & -- PA6.ctl
"116 (BC_6, PA6, bidir, X, 117, 0, Z)," &
"115 (BC_1, *, control, 0)," & -- PA7.ctl
"114 (BC_6, PA7, bidir, X, 115, 0, Z)," &
"113 (BC_1, *, internal, 0)," & -- PA7.pu
"112 (BC_1, *, control, 0)," & -- O1F4K.ctl
"111 (BC_6, O1F4K, bidir, X, 112, 0, Z)," &
"110 (BC_1, *, control, 0)," & -- O192K.ctl
"109 (BC_6, O192K, bidir, X, 110, 0, Z)," &
"108 (BC_1, *, control, 0)," & -- O1FCK.ctl
"107 (BC_6, O1FCK, bidir, X, 108, 0, Z)," &
"106 (BC_1, *, control, 0)," & -- SB1RD.ctl
"105 (BC_6, SB1RD, bidir, X, 106, 0, Z)," &
"104 (BC_1, *, control, 0)," & -- SB2RD.ctl
"103 (BC_6, SB2RD, bidir, X, 104, 0, Z)," &
"102 (BC_1, *, control, 0)," & -- SDSRD.ctl
"101 (BC_6, SDSRD, bidir, X, 102, 0, Z)," &
"100 (BC_1, *, control, 0)," & -- SB1SD.ctl
"99 (BC_6, SB1SD, bidir, X, 100, 0, Z)," &
"98 (BC_1, *, control, 0)," & -- SB2SD.ctl
"97 (BC_6, SB2SD, bidir, X, 98, 0, Z)," &
"96 (BC_1, *, control, 0)," & -- SDQSD.ctl
"95 (BC_6, SDQSD, bidir, X, 96, 0, Z)," &
"94 (BC_1, *, control, 0)," & -- DFSC2.ctl
"93 (BC_6, DFSC2, bidir, X, 94, 0, Z)," &
"92 (BC_1, *, control, 0)," & -- DFSC3.ctl
"91 (BC_6, DFSC3, bidir, X, 92, 0, Z)," &
"90 (BC_1, *, control, 0)," & -- FSC1.ctl
"89 (BC_6, FSC1, bidir, X, 90, 0, Z)," &
"88 (BC_1, *, control, 0)," & -- DCL1.ctl
"87 (BC_6, DCL1, bidir, X, 88, 0, Z)," &
"86 (BC_1, *, control, 0)," & -- DREQ1.ctl
"85 (BC_6, DREQ1, bidir, X, 86, 0, Z)," &
"84 (BC_1, *, control, 0)," & -- DGNT1.ctl
"83 (BC_6, DGNT1, bidir, X, 84, 0, Z)," &
"82 (BC_1, *, control, 0)," & -- DOUT1.ctl
"81 (BC_1, DOUT1, output3, X, 82, 0, Z)," &
"80 (BC_1, *, control, 0)," & -- DIN1.ctl
"79 (BC_6, DIN1, bidir, X, 80, 0, Z)," &
"78 (BC_1, *, control, 0)," & -- INT4.ctl
"77 (BC_6, INT4, bidir, X, 78, 0, Z)," &
"76 (BC_1, *, control, 0)," & -- PB5.ctl
"75 (BC_6, PB5, bidir, X, 76, 0, Z)," &
"74 (BC_1, *, internal, X)," & -- PB5.pu
"73 (BC_1, *, control, 0)," & -- PB6.ctl
"72 (BC_6, PB6, bidir, X, 73, 0, Z)," &
"71 (BC_1, *, control, 0)," & -- TXD1.ctl
"70 (BC_6, TXD1, bidir, X, 71, 0, Z)," &
"69 (BC_1, *, internal, X)," & -- TXD1.pu
"68 (BC_1, *, control, 0)," & -- RXD1.ctl
"67 (BC_6, RXD1, bidir, X, 68, 0, Z)," &
"66 (BC_1, *, control, 0)," & -- CTS1.ctl
"65 (BC_6, CTS1, bidir, X, 66, 0, Z)," &
"64 (BC_1, *, control, 0)," & -- RTS1.ctl
"63 (BC_6, RTS1, bidir, X, 64, 0, Z)," &
"62 (BC_1, *, control, 0)," & -- CLK1.ctl
"61 (BC_6, CLK1, bidir, X, 62, 0, Z)," &
"60 (BC_4, UEXTAL, input, X)," &
"59 (BC_1, *, internal,0)," & -- iousb_s8 iousb.vp output
"58 (BC_1, *, internal,0)," & -- iousb_s8 iousb.vn output
"57 (BC_1, *, internal,0)," & -- iousb_s8 iousb.rcv output
"56 (BC_1, *, internal,0)," & -- iousb_s8 iousb.d input
"55 (BC_1, *, internal,0)," & -- iousb_s8 iousb.db input
"54 (BC_1, *, internal,0)," & -- iousb_s8 iousb.enb input
"53 (BC_1, *, internal,0)," & -- iousb_s8 iousb.speed input
"52 (BC_1, *, internal,0)," & -- iousb_s8 iousb.off input
"51 (BC_6, TIN1, bidir, X, 80, 0, Z)," &
"50 (BC_1, *, control, 0)," & -- TOUT1.ctl
"49 (BC_6, TOUT1, bidir, X, 50, 0, Z)," &
"48 (BC_6, INT1, bidir, X, 80, 0, Z)," &
"47 (BC_6, INT2, bidir, X, 80, 0, Z)," &
"46 (BC_6, INT3, bidir, X, 80, 0, Z)," &
"45 (BC_1, *, control, 0)," & -- SPMOSI.ctl
"44 (BC_6, SPMOSI, bidir, X, 45, 0, Z)," &
"43 (BC_1, *, control, 0)," & -- SPMISO.ctl
"42 (BC_6, SPMISO, bidir, X, 43, 0, Z)," &
"41 (BC_1, *, control, 0)," & -- SPCLK.ctl
"40 (BC_6, SPCLK, bidir, X, 41, 0, Z)," &
"39 (BC_1, *, control, 0)," & -- SPCS0B.ctl
"38 (BC_6, SPCS0B, bidir, X, 39, 0, Z)," &
"37 (BC_1, *, control, 0)," & -- PWM1.ctl
"36 (BC_6, PWM1, bidir, X, 37, 0, Z)," &
"35 (BC_1, *, control, 0)," & -- PWM2.ctl
"34 (BC_6, PWM2, bidir, X, 35, 0, Z)," &
"33 (BC_1, *, control, 0)," & -- PWM3.ctl
"32 (BC_6, PWM3, bidir, X, 33, 0, Z)," &
"31 (BC_4, ETXCLK, input, X)," &
"30 (BC_1, *, control, 0)," & -- ETXD.ctl
"29 (BC_1, ETXD, output3, X, 30, 0, Z)," &
"28 (BC_4, ECOL, input, X)," &
"27 (BC_1, *, control, 0)," & -- ERXDV.ctl
"26 (BC_6, ERXDV, bidir, X, 27, 0, Z)," &
"25 (BC_4, ERXCLK, input, X)," &
"24 (BC_1, *, control, 0)," & -- ERXD.ctl
"23 (BC_6, ERXD, bidir, X, 24, 0, Z)," &
"22 (BC_1, *, control, 0)," & -- ETXEN.ctl
"21 (BC_1, ETXEN, output3, X, 22, 0, Z)," &
"20 (BC_1, *, control, 0)," & -- ETXD3.ctl
"19 (BC_6, ETXD3, bidir, X, 20, 0, Z)," &
"18 (BC_1, *, control, 0)," & -- ETXD2.ctl
"17 (BC_6, ETXD2, bidir, X, 18, 0, Z)," &
"16 (BC_1, *, control, 0)," & -- ETXD1.ctl
"15 (BC_6, ETXD1, bidir, X, 16, 0, Z)," &
"14 (BC_1, *, control, 0)," & -- ERXD3.ctl
"13 (BC_6, ERXD3, bidir, X, 14, 0, Z)," &
"12 (BC_1, *, control, 0)," & -- ERXD2.ctl
"11 (BC_6, ERXD2, bidir, X, 12, 0, Z)," &
"10 (BC_1, *, control, 0)," & -- ERXD1.ctl
"9 (BC_6, ERXD1, bidir, X, 10, 0, Z)," &
"8 (BC_1, *, control, 0)," & -- ERXERR.ctl
"7 (BC_6, ERXERR, bidir, X, 8, 0, Z)," &
"6 (BC_1, *, control, 0)," & -- EMDC.ctl
"5 (BC_6, EMDC, bidir, X, 6, 0, Z)," &
"4 (BC_1, *, control, 0)," & -- EMDIO.ctl
"3 (BC_6, EMDIO, bidir, X, 4, 0, Z)," &
"2 (BC_1, *, control, 0)," & -- ETXERR.ctl
"1 (BC_6, ETXERR, bidir, X, 2, 0, Z)," &
"0 (BC_6, ECRS, bidir, X, 24, 0, Z)";
end MCF5272_1K75N;