------------------------------------------------------------------------------------------------------
-- BSDL Description for TMS320TCI6487 / TMS320TCI6488
--- 1149.1
-- Version 02 (v02)
--- Updated file to reflect new silicon revision
-- Changed from v02 to v03 to denote update to Rev 1.3 silicon
--- BSDL file represents PG1.3 silicon
--- Variant code updated from revision PG1.2
--- BSDL file regenerated 20Jan09
--- Variant code changed to 0010
--- Generated by design, modified and checked by R. Lerner
--- BSDL file passed Parser-- Dated 28Jan09
------------------------------------------------------------------------------------------------------
entity TMS320TCI6487_88 is
generic( PHYSICAL_PIN_MAP : string := "ZUN" );
--
-- This is based on the RTL names
--
PORT ( -- dir
AIFRXN0 : IN BIT;
AIFRXP0 : IN BIT;
AIFRXN1 : IN BIT;
AIFRXP1 : IN BIT;
AIFRXN2 : IN BIT;
AIFRXP2 : IN BIT;
AIFRXN3 : IN BIT;
AIFRXP3 : IN BIT;
AIFRXN4 : IN BIT;
AIFRXP4 : IN BIT;
AIFRXN5 : IN BIT;
AIFRXP5 : IN BIT;
AIFTXN0 : BUFFER BIT;
AIFTXP0 : BUFFER BIT;
AIFTXN1 : BUFFER BIT;
AIFTXP1 : BUFFER BIT;
AIFTXN2 : BUFFER BIT;
AIFTXP2 : BUFFER BIT;
AIFTXN3 : BUFFER BIT;
AIFTXP3 : BUFFER BIT;
AIFTXN4 : BUFFER BIT;
AIFTXP4 : BUFFER BIT;
AIFTXN5 : BUFFER BIT;
AIFTXP5 : BUFFER BIT;
RSV01 : LINKAGE BIT;
RSV02 : LINKAGE BIT;
NMI0 : INOUT BIT;
NMI1 : INOUT BIT;
NMI2 : INOUT BIT;
XWRSTz : IN BIT;
RESETSTATz : INOUT BIT;
PORz : IN BIT;
RSV03 : LINKAGE BIT;
RSV04 : LINKAGE BIT;
RSV05 : LINKAGE BIT;
RSV06 : BUFFER BIT;
RSV07 : BUFFER BIT;
RSV08 : BUFFER BIT;
RSV09 : BUFFER BIT;
RSV23 : INOUT BIT;
RSV24 : INOUT BIT;
SYSCLKP : IN BIT;
SYSCLKN : IN BIT;
ALTCORECLKN : IN BIT;
ALTCORECLKP : IN BIT;
DDRREFCLKN : IN BIT;
DDRREFCLKP : IN BIT;
SYSCLKOUT : INOUT BIT;
CORECLKSEL : IN BIT;
RIOSGMIICLKN : IN BIT;
RIOSGMIICLKP : IN BIT;
DDRDQM0 : INOUT BIT;
DDRDQM1 : INOUT BIT;
DDRDQM2 : INOUT BIT;
DDRDQM3 : INOUT BIT;
DDRCEz : INOUT BIT;
DDRBA0 : INOUT BIT;
DDRBA1 : INOUT BIT;
DDRBA2 : INOUT BIT;
DDRA00 : INOUT BIT;
DDRA01 : INOUT BIT;
DDRA02 : INOUT BIT;
DDRA03 : INOUT BIT;
DDRA04 : INOUT BIT;
DDRA05 : INOUT BIT;
DDRA06 : INOUT BIT;
DDRA07 : INOUT BIT;
DDRA08 : INOUT BIT;
DDRA09 : INOUT BIT;
DDRA10 : INOUT BIT;
DDRA11 : INOUT BIT;
DDRA12 : INOUT BIT;
DDRA13 : INOUT BIT;
DDRCLKOUTP0 : INOUT BIT;
DDRCLKOUTN0 : INOUT BIT;
DDRCLKOUTP1 : LINKAGE BIT;
DDRCLKOUTN1 : LINKAGE BIT;
DDRD00 : INOUT BIT;
DDRD01 : INOUT BIT;
DDRD02 : INOUT BIT;
DDRD03 : INOUT BIT;
DDRD04 : INOUT BIT;
DDRD05 : INOUT BIT;
DDRD06 : INOUT BIT;
DDRD07 : INOUT BIT;
DDRD08 : INOUT BIT;
DDRD09 : INOUT BIT;
DDRD10 : INOUT BIT;
DDRD11 : INOUT BIT;
DDRD12 : INOUT BIT;
DDRD13 : INOUT BIT;
DDRD14 : INOUT BIT;
DDRD15 : INOUT BIT;
DDRD16 : INOUT BIT;
DDRD17 : INOUT BIT;
DDRD18 : INOUT BIT;
DDRD19 : INOUT BIT;
DDRD20 : INOUT BIT;
DDRD21 : INOUT BIT;
DDRD22 : INOUT BIT;
DDRD23 : INOUT BIT;
DDRD24 : INOUT BIT;
DDRD25 : INOUT BIT;
DDRD26 : INOUT BIT;
DDRD27 : INOUT BIT;
DDRD28 : INOUT BIT;
DDRD29 : INOUT BIT;
DDRD30 : INOUT BIT;
DDRD31 : INOUT BIT;
DDRCASz : INOUT BIT;
DDRRASz : INOUT BIT;
DDRWEz : INOUT BIT;
DDRCKE : INOUT BIT;
DDRDQS0P : INOUT BIT;
DDRDQS0N : INOUT BIT;
DDRDQS1P : INOUT BIT;
DDRDQS1N : INOUT BIT;
DDRDQS2P : INOUT BIT;
DDRDQS2N : INOUT BIT;
DDRDQS3P : INOUT BIT;
DDRDQS3N : INOUT BIT;
DDRRCVENIN0 : INOUT BIT;
DDRRCVENOUT0 : INOUT BIT;
DDRRCVENIN1 : INOUT BIT;
DDRRCVENOUT1 : INOUT BIT;
DDRODT : INOUT BIT;
DDRSLRATE : INOUT BIT;
VREFSSTL : LINKAGE BIT;
TCK : IN BIT;
TDI : IN BIT;
TDO : OUT BIT;
TMS : IN BIT;
TRSTz : IN BIT;
EMU00 : INOUT BIT;
EMU01 : INOUT BIT;
EMU02 : INOUT BIT;
EMU03 : INOUT BIT;
EMU04 : INOUT BIT;
EMU05 : INOUT BIT;
EMU06 : INOUT BIT;
EMU07 : INOUT BIT;
EMU08 : INOUT BIT;
EMU09 : INOUT BIT;
EMU10 : INOUT BIT;
EMU11 : INOUT BIT;
EMU12 : INOUT BIT;
EMU13 : INOUT BIT;
EMU14 : INOUT BIT;
EMU15 : INOUT BIT;
EMU16 : INOUT BIT;
EMU17 : INOUT BIT;
EMU18 : INOUT BIT;
RSV10 : INOUT BIT;
RSV11 : INOUT BIT;
RSV12 : INOUT BIT;
RSV13 : INOUT BIT;
RSV14 : INOUT BIT;
FSYNCCLKN : IN BIT;
FSYNCCLKP : IN BIT;
SMFRAMECLK : INOUT BIT;
FRAMEBURSTN : IN BIT;
FRAMEBURSTP : IN BIT;
ALTFSYNCCLK : INOUT BIT;
ALTFSYNCPULSE : INOUT BIT;
TRT : INOUT BIT;
TRTCLK : INOUT BIT;
GP00 : INOUT BIT;
GP01 : INOUT BIT;
GP02 : INOUT BIT;
GP03 : INOUT BIT;
GP04 : INOUT BIT;
GP05 : INOUT BIT;
GP06 : INOUT BIT;
GP07 : INOUT BIT;
GP08 : INOUT BIT;
GP09 : INOUT BIT;
GP10 : INOUT BIT;
GP11 : INOUT BIT;
GP12 : INOUT BIT;
GP13 : INOUT BIT;
GP14 : INOUT BIT;
GP15 : INOUT BIT;
SCL : INOUT BIT;
SDA : INOUT BIT;
CLKS0 : IN BIT;
CLKR0 : INOUT BIT;
CLKX0 : INOUT BIT;
DR0 : IN BIT;
DX0 : INOUT BIT;
FSR0 : INOUT BIT;
FSX0 : INOUT BIT;
CLKS1 : IN BIT;
CLKR1 : INOUT BIT;
CLKX1 : INOUT BIT;
DR1 : IN BIT;
DX1 : INOUT BIT;
FSR1 : INOUT BIT;
FSX1 : INOUT BIT;
RSV15 : LINKAGE BIT;
RSV16 : LINKAGE BIT;
THERMDIODEA0 : LINKAGE BIT;
THERMDIODEC0 : LINKAGE BIT;
RSV25 : LINKAGE BIT;
RSV26 : LINKAGE BIT;
VCNTL0 : LINKAGE BIT;
VCNTL1 : LINKAGE BIT;
VCNTL2 : LINKAGE BIT;
VCNTL3 : LINKAGE BIT;
HITEMPz : IN BIT;
RIORXN0 : IN BIT;
RIORXP0 : IN BIT;
RIORXN1 : IN BIT;
RIORXP1 : IN BIT;
RIOTXN0 : BUFFER BIT;
RIOTXP0 : BUFFER BIT;
RIOTXN1 : BUFFER BIT;
RIOTXP1 : BUFFER BIT;
RSV17 : LINKAGE BIT;
SGMIIRXN : IN BIT;
SGMIIRXP : IN BIT;
SGMIITXN : BUFFER BIT;
SGMIITXP : BUFFER BIT;
RSV18 : LINKAGE BIT;
MDIO : INOUT BIT;
MDCLK : INOUT BIT;
TIMI0 : IN BIT;
TIMI1 : IN BIT;
TIMO0 : INOUT BIT;
TIMO1 : INOUT BIT;
RSV19 : INOUT BIT;
RSV20 : INOUT BIT;
CVdd_MON : LINKAGE BIT;
DVdd_18_MON : LINKAGE BIT;
AVdd2_18 : LINKAGE BIT;
AVdd1_18 : LINKAGE BIT;
RSV21 : LINKAGE BIT;
RSV22 : LINKAGE BIT;
DVdd_18 : LINKAGE BIT_VECTOR(46 downto 0);
AIF_Vdda_11 : LINKAGE BIT_VECTOR(10 downto 0);
AIF_Vddr_18 : LINKAGE BIT_VECTOR(1 downto 0);
AIF_Vddt_11 : LINKAGE BIT_VECTOR(6 downto 0);
CVdd : LINKAGE BIT_VECTOR(49 downto 0);
Vss : LINKAGE BIT_VECTOR(189 downto 0);
SGR_Vdda_11 : LINKAGE BIT_VECTOR(3 downto 0);
SGR_Vddd_11 : LINKAGE BIT_VECTOR(4 downto 0);
SGR_Vddr_18 : LINKAGE BIT_VECTOR(1 downto 0);
SGR_Vddt_11 : LINKAGE BIT_VECTOR(5 downto 0)
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of TMS320TCI6487_88 : entity is "STD_1149_1_2001";
attribute PIN_MAP of TMS320TCI6487_88 : entity is PHYSICAL_PIN_MAP;
constant ZUN : PIN_MAP_STRING :=
"AIFRXN0 : AF22,"&
"AIFRXP0 : AF21,"&
"AIFRXN1 : AG20,"&
"AIFRXP1 : AG21,"&
"AIFRXN2 : AG18,"&
"AIFRXP2 : AG17,"&
"AIFRXN3 : AE17,"&
"AIFRXP3 : AE18,"&
"AIFRXN4 : AE14,"&
"AIFRXP4 : AE13,"&
"AIFRXN5 : AF12,"&
"AIFRXP5 : AF13,"&
"AIFTXN0 : AE21,"&
"AIFTXP0 : AE22,"&
"AIFTXN1 : AD21,"&
"AIFTXP1 : AD20,"&
"AIFTXN2 : AF16,"&
"AIFTXP2 : AF17,"&
"AIFTXN3 : AD17,"&
"AIFTXP3 : AD16,"&
"AIFTXN4 : AG13,"&
"AIFTXP4 : AG14,"&
"AIFTXN5 : AD13,"&
"AIFTXP5 : AD12,"&
"RSV01 : AE19,"&
"RSV02 : AD14,"&
"NMI0 : J4,"&
"NMI1 : J2,"&
"NMI2 : J1,"&
"XWRSTz : AD5,"&
"RESETSTATz : AF4,"&
"PORz : AE5,"&
"RSV03 : N24,"&
"RSV04 : AG10,"&
"RSV05 : AG24,"&
"RSV06 : AE7,"&
"RSV07 : AE8,"&
"RSV08 : AF24,"&
"RSV09 : AF25,"&
"RSV23 : AE4,"&
"RSV24 : AG25,"&
"SYSCLKP : AE9,"&
"SYSCLKN : AE10,"&
"ALTCORECLKN : AF10,"&
"ALTCORECLKP : AF9,"&
"DDRREFCLKN : AD23,"&
"DDRREFCLKP : AD24,"&
"SYSCLKOUT : AD6,"&
"CORECLKSEL : AF7,"&
"RIOSGMIICLKN : D9,"&
"RIOSGMIICLKP : C9,"&
"DDRDQM0 : W24,"&
"DDRDQM1 : AE24,"&
"DDRDQM2 : B24,"&
"DDRDQM3 : H24,"&
"DDRCEz : L24,"&
"DDRBA0 : T25,"&
"DDRBA1 : R25,"&
"DDRBA2 : U25,"&
"DDRA00 : K25,"&
"DDRA01 : N25,"&
"DDRA02 : M25,"&
"DDRA03 : R26,"&
"DDRA04 : L25,"&
"DDRA05 : N27,"&
"DDRA06 : L26,"&
"DDRA07 : U26,"&
"DDRA08 : K26,"&
"DDRA09 : R27,"&
"DDRA10 : P25,"&
"DDRA11 : L27,"&
"DDRA12 : U27,"&
"DDRA13 : K27,"&
"DDRCLKOUTP0 : V25,"&
"DDRCLKOUTN0 : V24,"&
"DDRCLKOUTP1 : J25,"&
"DDRCLKOUTN1 : J24,"&
"DDRD00 : W27,"&
"DDRD01 : W25,"&
"DDRD02 : Y27,"&
"DDRD03 : W26,"&
"DDRD04 : AA27,"&
"DDRD05 : AA26,"&
"DDRD06 : AA25,"&
"DDRD07 : AA24,"&
"DDRD08 : AC27,"&
"DDRD09 : AC26,"&
"DDRD10 : AC25,"&
"DDRD11 : AD27,"&
"DDRD12 : AC24,"&
"DDRD13 : AE26,"&
"DDRD14 : AE27,"&
"DDRD15 : AE25,"&
"DDRD16 : B25,"&
"DDRD17 : D25,"&
"DDRD18 : B26,"&
"DDRD19 : D24,"&
"DDRD20 : B27,"&
"DDRD21 : D26,"&
"DDRD22 : D27,"&
"DDRD23 : C27,"&
"DDRD24 : F24,"&
"DDRD25 : F25,"&
"DDRD26 : F26,"&
"DDRD27 : F27,"&
"DDRD28 : G27,"&
"DDRD29 : H25,"&
"DDRD30 : H26,"&
"DDRD31 : H27,"&
"DDRCASz : N26,"&
"DDRRASz : M24,"&
"DDRWEz : P24,"&
"DDRCKE : T24,"&
"DDRDQS0P : Y26,"&
"DDRDQS0N : Y25,"&
"DDRDQS1P : AD26,"&
"DDRDQS1N : AD25,"&
"DDRDQS2P : C26,"&
"DDRDQS2N : C25,"&
"DDRDQS3P : G25,"&
"DDRDQS3N : G26,"&
"DDRRCVENIN0 : AB25,"&
"DDRRCVENOUT0 : AB24,"&
"DDRRCVENIN1 : E24,"&
"DDRRCVENOUT1 : E25,"&
"DDRODT : K24,"&
"DDRSLRATE : AE23,"&
"VREFSSTL : T26,"&
"TCK : W4,"&
"TDI : V4,"&
"TDO : W3,"&
"TMS : W1,"&
"TRSTz : W2,"&
"EMU00 : R4,"&
"EMU01 : R2,"&
"EMU02 : N3,"&
"EMU03 : N1,"&
"EMU04 : M2,"&
"EMU05 : M1,"&
"EMU06 : N4,"&
"EMU07 : R3,"&
"EMU08 : M4,"&
"EMU09 : N2,"&
"EMU10 : R1,"&
"EMU11 : T2,"&
"EMU12 : L3,"&
"EMU13 : P4,"&
"EMU14 : K2,"&
"EMU15 : T1,"&
"EMU16 : P3,"&
"EMU17 : L4,"&
"EMU18 : M3,"&
"RSV10 : K4,"&
"RSV11 : K3,"&
"RSV12 : K1,"&
"RSV13 : G4,"&
"RSV14 : F3,"&
"FSYNCCLKN : AD8,"&
"FSYNCCLKP : AD7,"&
"SMFRAMECLK : AD4,"&
"FRAMEBURSTN : AD10,"&
"FRAMEBURSTP : AD9,"&
"ALTFSYNCCLK : AF6,"&
"ALTFSYNCPULSE : AE6,"&
"TRT : AD3,"&
"TRTCLK : AC4,"&
"GP00 : T3,"&
"GP01 : U4,"&
"GP02 : V1,"&
"GP03 : U3,"&
"GP04 : T4,"&
"GP05 : V2,"&
"GP06 : V3,"&
"GP07 : Y3,"&
"GP08 : Y4,"&
"GP09 : AA2,"&
"GP10 : AA3,"&
"GP11 : AB4,"&
"GP12 : AB3,"&
"GP13 : AB2,"&
"GP14 : AA4,"&
"GP15 : AC3,"&
"SCL : E4,"&
"SDA : D4,"&
"CLKS0 : D20,"&
"CLKR0 : B20,"&
"CLKX0 : C20,"&
"DR0 : A20,"&
"DX0 : D19,"&
"FSR0 : B21,"&
"FSX0 : A21,"&
"CLKS1 : A25,"&
"CLKR1 : A24,"&
"CLKX1 : C22,"&
"DR1 : D21,"&
"DX1 : B22,"&
"FSR1 : C21,"&
"FSX1 : A22,"&
"RSV15 : D7,"&
"RSV16 : C7,"&
"THERMDIODEA0 : D5,"&
"THERMDIODEC0 : C5,"&
"RSV25 : D22,"&
"RSV26 : C23,"&
"VCNTL0 : G3,"&
"VCNTL1 : G2,"&
"VCNTL2 : H4,"&
"VCNTL3 : H3,"&
"HITEMPz : J3,"&
"RIORXN0 : A9,"&
"RIORXP0 : A10,"&
"RIORXN1 : A13,"&
"RIORXP1 : A12,"&
"RIOTXN0 : C11,"&
"RIOTXP0 : C10,"&
"RIOTXN1 : C13,"&
"RIOTXP1 : C14,"&
"RSV17 : B12,"&
"SGMIIRXN : C16,"&
"SGMIIRXP : C17,"&
"SGMIITXN : A16,"&
"SGMIITXP : A15,"&
"RSV18 : B18,"&
"MDIO : B19,"&
"MDCLK : C19,"&
"TIMI0 : E3,"&
"TIMI1 : C4,"&
"TIMO0 : F2,"&
"TIMO1 : F4,"&
"RSV19 : D6,"&
"RSV20 : C6,"&
"CVdd_MON : AG6,"&
"DVdd_18_MON : AG7,"&
"AVdd2_18 : AG23,"&
"AVdd1_18 : AG9,"&
"RSV21 : E6,"&
"RSV22 : E7,"&
"DVdd_18 : (A1,A19,A23,A27,A5,AA23,AA5,AB26,AC1,AC23,AC5,AC7,"&
"AC9,AF5,AG1,AG27,AG8,E1,E19,E21,E23,E27,E5,G23,G5,H2,"&
"J23,J27,J5,L1,L23,L5,M26,N23,N5,P2,P26,R23,R5,U1,U23,"&
"U5,V26,W23,W5,Y2,Y24),"&
"AIF_Vdda_11 : (AC12,AC15,AC18,AC21,AG26,U17,V16,V18,W15,W17,W19),"&
"AIF_Vddr_18 : (AD19,AD15),"&
"AIF_Vddt_11 : (AC11,AC14,AC17,AC20,AF15,AF19,AG11),"&
"CVdd : (J11,J17,J19,J9,K10,K18,L11,L13,L15,L17,L19,L9,"&
"M10,M12,M14,M16,M18,N11,N13,N15,N17,N19,N9,P10,"&
"P12,P14,P16,P18,R11,R13,R15,R17,R19,R9,T10,T12,"&
"T14,T16,T18,U11,U13,U15,U19,U9,V10,V12,V14,W11,"&
"W13,W9),"&
"Vss : (A11,A14,A17,A2,A26,A3,A4,A6,A7,A8,AA1,AB1,AB23,"&
"AB27,AB5,AC10,AC13,AC16,AC19,AC2,AC22,AC6,AC8,"&
"AD1,AD11,AD18,AD2,AD22,AE1,AE11,AE12,AE15,AE16,"&
"AE2,AE20,AE3,AF1,AF11,AF14,AF18,AF2,AF20,AF23,"&
"AF26,AF27,AF3,AF8,AG12,AG15,AG16,AG19,AG2,AG22,"&
"AG3,AG4,AG5,B1,B10,B11,B14,B15,B16,B2,B23,B3,B4,"&
"B5,B6,B7,B9,C1,C15,C18,C2,C24,C3,C8,D1,D10,D11,"&
"D13,D14,D15,D16,D17,D2,D23,D3,D8,E10,E12,E14,E16,"&
"E18,E2,E20,E22,E26,E8,F1,F23,F5,G1,G24,H1,H23,H5,"&
"J10,J12,J14,J16,J18,J26,K11,K13,K15,K17,K19,K23,"&
"K5,K9,L10,L12,L14,L16,L18,L2,M11,M13,M15,M17,M19,"&
"M23,M27,M5,M9,N10,N12,N14,N16,N18,P1,P11,P13,P15,"&
"P17,P19,P23,P27,P5,P9,R10,R12,R14,R16,R18,R24,T11,"&
"T13,T15,T17,T19,T23,T27,T5,T9,U10,U12,U14,U16,U18,"&
"U2,U24,V11,V13,V15,V17,V19,V23,V27,V5,V9,W10,W12,"&
"W14,W16,W18,Y1,Y23,Y5),"&
"SGR_Vdda_11 : (D12,D18,E11,E15),"&
"SGR_Vddd_11 : (J13,J15,K12,K14,K16),"&
"SGR_Vddr_18 : (C12,A18),"&
"SGR_Vddt_11 : (B13,B17,B8,E13,E17,E9)";
attribute PORT_GROUPING of TMS320TCI6487_88 : entity is
"Differential_Voltage ( " &
"(DDRREFCLKP, DDRREFCLKN), " &
"(FSYNCCLKP, FSYNCCLKN), " &
"(FRAMEBURSTP, FRAMEBURSTN), " &
"(AIFTXP0, AIFTXN0), " &
"(AIFTXP1, AIFTXN1), " &
"(AIFTXP2, AIFTXN2), " &
"(AIFTXP3, AIFTXN3), " &
"(AIFTXP4, AIFTXN4), " &
"(AIFTXP5, AIFTXN5), " &
"(SGMIITXP, SGMIITXN), " &
"(RIOTXP0, RIOTXN0), " &
"(RIOTXP1, RIOTXN1), " &
"(RIOSGMIICLKP, RIOSGMIICLKN), " &
"(SYSCLKP, SYSCLKN), " &
"(RSV08, RSV09), " &
"(ALTCORECLKP, ALTCORECLKN), " &
"(RSV06, RSV07)) " ;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6,BOTH); -- 20 MHz, can stop TCLK in both 0 and 1 states
attribute TAP_SCAN_RESET of TRSTz : signal is true;
attribute COMPLIANCE_PATTERNS of TMS320TCI6487_88 : entity is "(PORz)(1)";
attribute INSTRUCTION_LENGTH of TMS320TCI6487_88 : entity is 6;
-- Opcode values are obtained from icepick_lib/icepick_wrap/pds/extract/rel_2_5/rtl/icepick_pkg.vhd
attribute INSTRUCTION_OPCODE of TMS320TCI6487_88 : entity is
"ROUTER (000010),"&
"IDCODE (000100),"&
"ICEPIDCODE (000101),"&
"CONPUB (000111),"&
"CHIPSPINID (001000),"&
"EXTEST_nPUPD (010111),"&
"EXTEST (011000),"& -- required, redundantly harmless to list here
"INTEST_PRIV (011001),"&
"RUNBIST_PRIV (011010),"&
"SAMPLE (011011),"& -- required, redundantly harmless to list here
"PRELOAD (011100),"&
"CLAMP_PRIV (011101),"&
"HIGHZ_PRIV (011110),"&
"CONPRIV (011111),"&
"EXTEST_PULSE (100100),"&
"EXTEST_TRAIN (100101),"&
"P1500_MD (110001),"&
"BYPASS (000000,111111)"; -- required, redundantly harmless to list here
-- examples of other allowed 1149.1-1993 instructions permitted
-- "PRIVATE1 (101010),"& -- example of private instruction, also list in _PRIVATE below
-- "USERCODE (xxxxxx),"& -- optional USERCODE sec 7.13 (dieid?) is not supported by this chip
attribute INSTRUCTION_CAPTURE of TMS320TCI6487_88 : entity is "000001";
attribute INSTRUCTION_PRIVATE of TMS320TCI6487_88 : entity is
"ROUTER, " &
"ICEPIDCODE, " &
"CONPUB, " &
"CHIPSPINID, " &
"EXTEST_nPUPD, " &
"INTEST_PRIV, " &
"RUNBIST_PRIV, " &
"CLAMP_PRIV, " &
"HIGHZ_PRIV, " &
"CONPRIV, " &
"EXTEST_PULSE, " &
"EXTEST_TRAIN, " &
"P1500_MD";
-- This is from faraday test_lib/test_pkg/vhdl/header.vhd
attribute IDCODE_REGISTER of TMS320TCI6487_88 : entity is
"0010" & -- variant
"0000000010010010" & -- device id
"00000010111" & -- mfg = Texas Instruments
"1"; -- must end with 1
attribute REGISTER_ACCESS of TMS320TCI6487_88 : entity is
"BOUNDARY (EXTEST), "& -- redundant, but harmless to list here per B.8.13.3 a
"BOUNDARY (SAMPLE), "& -- redundant, but harmless to list here per B.8.13.3 a
"BOUNDARY (PRELOAD), "& -- redundant, but harmless to list here per B.8.13.3 a
"DEVICE_ID (IDCODE), "& -- redundant, but harmless to list here per B.8.13.3 a
"GEN_REG32[32] (ICEPIDCODE), "&
"GEN_REG1[1] (ROUTER), "&
"GEN_REG8[8] (CONPUB), "&
"GEN_REG32[32] (CHIPSPINID), "&
"GEN_REG1[1] (EXTEST_nPUPD), "&
"GEN_REG1[1] (INTEST_PRIV), "&
"GEN_REG1[1] (RUNBIST_PRIV), "&
"GEN_REG1[1] (CLAMP_PRIV), "&
"GEN_REG1[1] (HIGHZ_PRIV), "&
"GEN_REG1[1] (CONPRIV), "&
"BOUNDARY (EXTEST_PULSE), "&
"BOUNDARY (EXTEST_TRAIN), "&
"GEN_REG1[1] (P1500_MD), "&
"BYPASS (BYPASS) "; -- redundant, but harmless to list here per B.8.13.3 a
attribute BOUNDARY_LENGTH of TMS320TCI6487_88 : entity is 333;
-- IEEE1149.1 suppliment, section B.8.14: "Cell 0 is closest to tdo."
attribute BOUNDARY_REGISTER of TMS320TCI6487_88 : entity is
-- num cell port function safe [ccell disval rslt]
" 332 (BC_7, RSV19 , bidir, X, 331, 1, Z ),"&
" 331 (BC_2, * , control, 1 ),"&
" 330 (BC_7, RSV20 , bidir, X, 329, 1, Z ),"&
" 329 (BC_2, * , control, 1 ),"&
" 328 (BC_1, RIOSGMIICLKP , input, X ),"&
" 327 (BC_1, RIORXN0 , input, X ),"&
" 326 (BC_1, RIORXN1 , input, X ),"&
" 325 (BC_1, RIORXP0 , input, X ),"&
" 324 (BC_4, * , internal, X ),"&
" 323 (BC_1, RIORXP1 , input, X ),"&
" 322 (BC_1, SGMIIRXN , input, X ),"&
" 321 (BC_1, SGMIIRXP , input, X ),"&
" 320 (BC_1, RIOTXP0 , output2, X ),"&
" 319 (BC_1, RIOTXP1 , output2, X ),"&
" 318 (BC_1, SGMIITXP , output2, X ),"&
" 317 (BC_7, MDIO , bidir, X, 316, 1, Z ),"&
" 316 (BC_2, * , control, 1 ),"&
" 315 (BC_7, MDCLK , bidir, X, 314, 1, Z ),"&
" 314 (BC_2, * , control, 1 ),"&
" 313 (BC_7, CLKR0 , bidir, X, 312, 1, Z ),"&
" 312 (BC_2, * , control, 1 ),"&
" 311 (BC_7, CLKX0 , bidir, X, 310, 1, Z ),"&
" 310 (BC_2, * , control, 1 ),"&
" 309 (BC_7, DX0 , bidir, X, 308, 1, Z ),"&
" 308 (BC_2, * , control, 1 ),"&
" 307 (BC_7, FSR0 , bidir, X, 306, 1, Z ),"&
" 306 (BC_2, * , control, 1 ),"&
" 305 (BC_7, FSX0 , bidir, X, 304, 1, Z ),"&
" 304 (BC_2, * , control, 1 ),"&
" 303 (BC_7, CLKR1 , bidir, X, 302, 1, Z ),"&
" 302 (BC_2, * , control, 1 ),"&
" 301 (BC_7, CLKX1 , bidir, X, 300, 1, Z ),"&
" 300 (BC_2, * , control, 1 ),"&
" 299 (BC_7, DX1 , bidir, X, 298, 1, Z ),"&
" 298 (BC_2, * , control, 1 ),"&
" 297 (BC_7, FSR1 , bidir, X, 296, 1, Z ),"&
" 296 (BC_2, * , control, 1 ),"&
" 295 (BC_7, FSX1 , bidir, X, 294, 1, Z ),"&
" 294 (BC_2, * , control, 1 ),"&
" 293 (BC_1, DR0 , input, X ),"&
" 292 (BC_1, DR1 , input, X ),"&
" 291 (BC_1, CLKS0 , input, X ),"&
" 290 (BC_1, CLKS1 , input, X ),"&
" 289 (BC_7, DDRODT , bidir, X, 288, 1, Z ),"&
" 288 (BC_2, * , control, 1 ),"&
" 287 (BC_7, DDRRASz , bidir, X, 286, 1, Z ),"&
" 286 (BC_2, * , control, 1 ),"&
" 285 (BC_7, DDRCEz , bidir, X, 284, 1, Z ),"&
" 284 (BC_2, * , control, 1 ),"&
" 283 (BC_7, DDRA04 , bidir, X, 282, 1, Z ),"&
" 282 (BC_2, * , control, 1 ),"&
" 281 (BC_7, DDRA02 , bidir, X, 280, 1, Z ),"&
" 280 (BC_2, * , control, 1 ),"&
" 279 (BC_7, DDRA00 , bidir, X, 278, 1, Z ),"&
" 278 (BC_2, * , control, 1 ),"&
" 277 (BC_7, DDRA08 , bidir, X, 276, 1, Z ),"&
" 276 (BC_2, * , control, 1 ),"&
" 275 (BC_7, DDRWEz , bidir, X, 274, 1, Z ),"&
" 274 (BC_2, * , control, 1 ),"&
" 273 (BC_7, DDRA01 , bidir, X, 272, 1, Z ),"&
" 272 (BC_2, * , control, 1 ),"&
" 271 (BC_7, DDRA06 , bidir, X, 270, 1, Z ),"&
" 270 (BC_2, * , control, 1 ),"&
" 269 (BC_7, DDRA10 , bidir, X, 268, 1, Z ),"&
" 268 (BC_2, * , control, 1 ),"&
" 267 (BC_7, DDRCASz , bidir, X, 266, 1, Z ),"&
" 266 (BC_2, * , control, 1 ),"&
" 265 (BC_7, DDRA13 , bidir, X, 264, 1, Z ),"&
" 264 (BC_2, * , control, 1 ),"&
" 263 (BC_7, DDRA11 , bidir, X, 262, 1, Z ),"&
" 262 (BC_2, * , control, 1 ),"&
" 261 (BC_7, DDRBA1 , bidir, X, 260, 1, Z ),"&
" 260 (BC_2, * , control, 1 ),"&
" 259 (BC_7, DDRA05 , bidir, X, 258, 1, Z ),"&
" 258 (BC_2, * , control, 1 ),"&
" 257 (BC_7, DDRA03 , bidir, X, 256, 1, Z ),"&
" 256 (BC_2, * , control, 1 ),"&
" 255 (BC_7, DDRA09 , bidir, X, 254, 1, Z ),"&
" 254 (BC_2, * , control, 1 ),"&
" 253 (BC_7, DDRBA0 , bidir, X, 252, 1, Z ),"&
" 252 (BC_2, * , control, 1 ),"&
" 251 (BC_7, DDRCKE , bidir, X, 250, 1, Z ),"&
" 250 (BC_2, * , control, 1 ),"&
" 249 (BC_7, DDRA12 , bidir, X, 248, 1, Z ),"&
" 248 (BC_2, * , control, 1 ),"&
" 247 (BC_7, DDRA07 , bidir, X, 246, 1, Z ),"&
" 246 (BC_2, * , control, 1 ),"&
" 245 (BC_7, DDRBA2 , bidir, X, 244, 1, Z ),"&
" 244 (BC_2, * , control, 1 ),"&
" 243 (BC_7, DDRD16 , bidir, X, 242, 1, Z ),"&
" 242 (BC_2, * , control, 1 ),"&
" 241 (BC_7, DDRD17 , bidir, X, 240, 1, Z ),"&
" 240 (BC_2, * , control, 1 ),"&
" 239 (BC_7, DDRD18 , bidir, X, 238, 1, Z ),"&
" 238 (BC_2, * , control, 1 ),"&
" 237 (BC_7, DDRD19 , bidir, X, 236, 1, Z ),"&
" 236 (BC_2, * , control, 1 ),"&
" 235 (BC_7, DDRD20 , bidir, X, 234, 1, Z ),"&
" 234 (BC_2, * , control, 1 ),"&
" 233 (BC_7, DDRD21 , bidir, X, 232, 1, Z ),"&
" 232 (BC_2, * , control, 1 ),"&
" 231 (BC_7, DDRD22 , bidir, X, 230, 1, Z ),"&
" 230 (BC_2, * , control, 1 ),"&
" 229 (BC_7, DDRD23 , bidir, X, 228, 1, Z ),"&
" 228 (BC_2, * , control, 1 ),"&
" 227 (BC_7, DDRD24 , bidir, X, 226, 1, Z ),"&
" 226 (BC_2, * , control, 1 ),"&
" 225 (BC_7, DDRD25 , bidir, X, 224, 1, Z ),"&
" 224 (BC_2, * , control, 1 ),"&
" 223 (BC_7, DDRD26 , bidir, X, 222, 1, Z ),"&
" 222 (BC_2, * , control, 1 ),"&
" 221 (BC_7, DDRD27 , bidir, X, 220, 1, Z ),"&
" 220 (BC_2, * , control, 1 ),"&
" 219 (BC_7, DDRD28 , bidir, X, 218, 1, Z ),"&
" 218 (BC_2, * , control, 1 ),"&
" 217 (BC_7, DDRD29 , bidir, X, 216, 1, Z ),"&
" 216 (BC_2, * , control, 1 ),"&
" 215 (BC_7, DDRD30 , bidir, X, 214, 1, Z ),"&
" 214 (BC_2, * , control, 1 ),"&
" 213 (BC_7, DDRD31 , bidir, X, 212, 1, Z ),"&
" 212 (BC_2, * , control, 1 ),"&
" 211 (BC_7, DDRD00 , bidir, X, 210, 1, Z ),"&
" 210 (BC_2, * , control, 1 ),"&
" 209 (BC_7, DDRD01 , bidir, X, 208, 1, Z ),"&
" 208 (BC_2, * , control, 1 ),"&
" 207 (BC_7, DDRD02 , bidir, X, 206, 1, Z ),"&
" 206 (BC_2, * , control, 1 ),"&
" 205 (BC_7, DDRD03 , bidir, X, 204, 1, Z ),"&
" 204 (BC_2, * , control, 1 ),"&
" 203 (BC_7, DDRD04 , bidir, X, 202, 1, Z ),"&
" 202 (BC_2, * , control, 1 ),"&
" 201 (BC_7, DDRD05 , bidir, X, 200, 1, Z ),"&
" 200 (BC_2, * , control, 1 ),"&
" 199 (BC_7, DDRD06 , bidir, X, 198, 1, Z ),"&
" 198 (BC_2, * , control, 1 ),"&
" 197 (BC_7, DDRD07 , bidir, X, 196, 1, Z ),"&
" 196 (BC_2, * , control, 1 ),"&
" 195 (BC_7, DDRD08 , bidir, X, 194, 1, Z ),"&
" 194 (BC_2, * , control, 1 ),"&
" 193 (BC_7, DDRD09 , bidir, X, 192, 1, Z ),"&
" 192 (BC_2, * , control, 1 ),"&
" 191 (BC_7, DDRD10 , bidir, X, 190, 1, Z ),"&
" 190 (BC_2, * , control, 1 ),"&
" 189 (BC_7, DDRD11 , bidir, X, 188, 1, Z ),"&
" 188 (BC_2, * , control, 1 ),"&
" 187 (BC_7, DDRD12 , bidir, X, 186, 1, Z ),"&
" 186 (BC_2, * , control, 1 ),"&
" 185 (BC_7, DDRD13 , bidir, X, 184, 1, Z ),"&
" 184 (BC_2, * , control, 1 ),"&
" 183 (BC_7, DDRD14 , bidir, X, 182, 1, Z ),"&
" 182 (BC_2, * , control, 1 ),"&
" 181 (BC_7, DDRD15 , bidir, X, 180, 1, Z ),"&
" 180 (BC_2, * , control, 1 ),"&
" 179 (BC_7, DDRDQM2 , bidir, X, 178, 1, Z ),"&
" 178 (BC_2, * , control, 1 ),"&
" 177 (BC_7, DDRDQM3 , bidir, X, 176, 1, Z ),"&
" 176 (BC_2, * , control, 1 ),"&
" 175 (BC_7, DDRDQM0 , bidir, X, 174, 1, Z ),"&
" 174 (BC_2, * , control, 1 ),"&
" 173 (BC_7, DDRDQM1 , bidir, X, 172, 1, Z ),"&
" 172 (BC_2, * , control, 1 ),"&
" 171 (BC_7, DDRDQS2P , bidir, X, 170, 1, Z ),"&
" 170 (BC_2, * , control, 1 ),"&
" 169 (BC_7, DDRDQS3P , bidir, X, 168, 1, Z ),"&
" 168 (BC_2, * , control, 1 ),"&
" 167 (BC_7, DDRDQS2N , bidir, X, 166, 1, Z ),"&
" 166 (BC_2, * , control, 1 ),"&
" 165 (BC_7, DDRDQS3N , bidir, X, 164, 1, Z ),"&
" 164 (BC_2, * , control, 1 ),"&
" 163 (BC_7, DDRDQS0P , bidir, X, 162, 1, Z ),"&
" 162 (BC_2, * , control, 1 ),"&
" 161 (BC_7, DDRDQS1P , bidir, X, 160, 1, Z ),"&
" 160 (BC_2, * , control, 1 ),"&
" 159 (BC_7, DDRDQS0N , bidir, X, 158, 1, Z ),"&
" 158 (BC_2, * , control, 1 ),"&
" 157 (BC_7, DDRDQS1N , bidir, X, 156, 1, Z ),"&
" 156 (BC_2, * , control, 1 ),"&
" 155 (BC_7, DDRRCVENIN1 , bidir, X, 154, 1, Z ),"&
" 154 (BC_2, * , control, 1 ),"&
" 153 (BC_7, DDRRCVENIN0 , bidir, X, 152, 1, Z ),"&
" 152 (BC_2, * , control, 1 ),"&
" 151 (BC_7, DDRRCVENOUT1 , bidir, X, 150, 1, Z ),"&
" 150 (BC_2, * , control, 1 ),"&
" 149 (BC_7, DDRRCVENOUT0 , bidir, X, 148, 1, Z ),"&
" 148 (BC_2, * , control, 1 ),"&
" 147 (BC_7, DDRCLKOUTP0 , bidir, X, 146, 1, Z ),"&
" 146 (BC_2, * , control, 1 ),"&
" 145 (BC_7, DDRCLKOUTN0 , bidir, X, 144, 1, Z ),"&
" 144 (BC_2, * , control, 1 ),"&
" 143 (BC_1, DDRREFCLKP , input, X ),"&
" 142 (BC_1, RSV08 , output2, X ),"&
" 141 (BC_7, DDRSLRATE , bidir, X, 140, 1, Z ),"&
" 140 (BC_2, * , control, 1 ),"&
" 139 (BC_7, RSV24 , bidir, X, 138, 1, Z ),"&
" 138 (BC_2, * , control, 1 ),"&
" 137 (BC_1, AIFRXN0 , input, X ),"&
" 136 (BC_1, AIFRXN1 , input, X ),"&
" 135 (BC_1, AIFRXN2 , input, X ),"&
" 134 (BC_1, AIFRXN3 , input, X ),"&
" 133 (BC_1, AIFRXN4 , input, X ),"&
" 132 (BC_1, AIFRXN5 , input, X ),"&
" 131 (BC_1, AIFRXP0 , input, X ),"&
" 130 (BC_1, AIFRXP1 , input, X ),"&
" 129 (BC_1, AIFRXP2 , input, X ),"&
" 128 (BC_1, AIFRXP3 , input, X ),"&
" 127 (BC_1, AIFRXP4 , input, X ),"&
" 126 (BC_1, AIFRXP5 , input, X ),"&
" 125 (BC_1, AIFTXP0 , output2, X ),"&
" 124 (BC_1, AIFTXP1 , output2, X ),"&
" 123 (BC_1, AIFTXP2 , output2, X ),"&
" 122 (BC_1, AIFTXP3 , output2, X ),"&
" 121 (BC_1, AIFTXP4 , output2, X ),"&
" 120 (BC_1, AIFTXP5 , output2, X ),"&
" 119 (BC_1, SYSCLKP , input, X ),"&
" 118 (BC_1, RSV06 , output2, X ),"&
" 117 (BC_1, FSYNCCLKP , input, X ),"&
" 116 (BC_1, FRAMEBURSTP , input, X ),"&
" 115 (BC_1, ALTCORECLKP , input, X ),"&
" 114 (BC_1, CORECLKSEL , input, X ),"&
" 113 (BC_7, ALTFSYNCCLK , bidir, X, 112, 1, Z ),"&
" 112 (BC_2, * , control, 1 ),"&
" 111 (BC_7, ALTFSYNCPULSE , bidir, X, 110, 1, Z ),"&
" 110 (BC_2, * , control, 1 ),"&
" 109 (BC_7, SYSCLKOUT , bidir, X, 108, 1, Z ),"&
" 108 (BC_2, * , control, 1 ),"&
" 107 (BC_1, XWRSTz , input, X ),"&
" 106 (BC_7, RESETSTATz , bidir, X, 105, 1, Z ),"&
" 105 (BC_2, * , control, 1 ),"&
" 104 (BC_7, RSV23 , bidir, X, 103, 1, Z ),"&
" 103 (BC_2, * , control, 1 ),"&
" 102 (BC_7, SMFRAMECLK , bidir, X, 101, 1, Z ),"&
" 101 (BC_2, * , control, 1 ),"&
" 100 (BC_7, TRT , bidir, X, 99, 1, Z ),"&
" 99 (BC_2, * , control, 1 ),"&
" 98 (BC_7, TRTCLK , bidir, X, 97, 1, Z ),"&
" 97 (BC_2, * , control, 1 ),"&
" 96 (BC_7, GP00 , bidir, X, 95, 1, Z ),"&
" 95 (BC_2, * , control, 1 ),"&
" 94 (BC_7, GP01 , bidir, X, 93, 1, Z ),"&
" 93 (BC_2, * , control, 1 ),"&
" 92 (BC_7, GP02 , bidir, X, 91, 1, Z ),"&
" 91 (BC_2, * , control, 1 ),"&
" 90 (BC_7, GP03 , bidir, X, 89, 1, Z ),"&
" 89 (BC_2, * , control, 1 ),"&
" 88 (BC_7, GP04 , bidir, X, 87, 1, Z ),"&
" 87 (BC_2, * , control, 1 ),"&
" 86 (BC_7, GP05 , bidir, X, 85, 1, Z ),"&
" 85 (BC_2, * , control, 1 ),"&
" 84 (BC_7, GP06 , bidir, X, 83, 1, Z ),"&
" 83 (BC_2, * , control, 1 ),"&
" 82 (BC_7, GP07 , bidir, X, 81, 1, Z ),"&
" 81 (BC_2, * , control, 1 ),"&
" 80 (BC_7, GP08 , bidir, X, 79, 1, Z ),"&
" 79 (BC_2, * , control, 1 ),"&
" 78 (BC_7, GP09 , bidir, X, 77, 1, Z ),"&
" 77 (BC_2, * , control, 1 ),"&
" 76 (BC_7, GP10 , bidir, X, 75, 1, Z ),"&
" 75 (BC_2, * , control, 1 ),"&
" 74 (BC_7, GP11 , bidir, X, 73, 1, Z ),"&
" 73 (BC_2, * , control, 1 ),"&
" 72 (BC_7, GP12 , bidir, X, 71, 1, Z ),"&
" 71 (BC_2, * , control, 1 ),"&
" 70 (BC_7, GP13 , bidir, X, 69, 1, Z ),"&
" 69 (BC_2, * , control, 1 ),"&
" 68 (BC_7, GP14 , bidir, X, 67, 1, Z ),"&
" 67 (BC_2, * , control, 1 ),"&
" 66 (BC_7, GP15 , bidir, X, 65, 1, Z ),"&
" 65 (BC_2, * , control, 1 ),"&
" 64 (BC_7, EMU00 , bidir, X, 63, 1, Z ),"&
" 63 (BC_2, * , control, 1 ),"&
" 62 (BC_7, EMU01 , bidir, X, 61, 1, Z ),"&
" 61 (BC_2, * , control, 1 ),"&
" 60 (BC_7, EMU02 , bidir, X, 59, 1, Z ),"&
" 59 (BC_2, * , control, 1 ),"&
" 58 (BC_7, EMU03 , bidir, X, 57, 1, Z ),"&
" 57 (BC_2, * , control, 1 ),"&
" 56 (BC_7, EMU04 , bidir, X, 55, 1, Z ),"&
" 55 (BC_2, * , control, 1 ),"&
" 54 (BC_7, EMU05 , bidir, X, 53, 1, Z ),"&
" 53 (BC_2, * , control, 1 ),"&
" 52 (BC_7, EMU06 , bidir, X, 51, 1, Z ),"&
" 51 (BC_2, * , control, 1 ),"&
" 50 (BC_7, EMU07 , bidir, X, 49, 1, Z ),"&
" 49 (BC_2, * , control, 1 ),"&
" 48 (BC_7, EMU08 , bidir, X, 47, 1, Z ),"&
" 47 (BC_2, * , control, 1 ),"&
" 46 (BC_7, EMU09 , bidir, X, 45, 1, Z ),"&
" 45 (BC_2, * , control, 1 ),"&
" 44 (BC_7, EMU10 , bidir, X, 43, 1, Z ),"&
" 43 (BC_2, * , control, 1 ),"&
" 42 (BC_7, EMU11 , bidir, X, 41, 1, Z ),"&
" 41 (BC_2, * , control, 1 ),"&
" 40 (BC_7, EMU12 , bidir, X, 39, 1, Z ),"&
" 39 (BC_2, * , control, 1 ),"&
" 38 (BC_7, EMU13 , bidir, X, 37, 1, Z ),"&
" 37 (BC_2, * , control, 1 ),"&
" 36 (BC_7, EMU14 , bidir, X, 35, 1, Z ),"&
" 35 (BC_2, * , control, 1 ),"&
" 34 (BC_7, EMU15 , bidir, X, 33, 1, Z ),"&
" 33 (BC_2, * , control, 1 ),"&
" 32 (BC_7, EMU16 , bidir, X, 31, 1, Z ),"&
" 31 (BC_2, * , control, 1 ),"&
" 30 (BC_7, EMU17 , bidir, X, 29, 1, Z ),"&
" 29 (BC_2, * , control, 1 ),"&
" 28 (BC_7, EMU18 , bidir, X, 27, 1, Z ),"&
" 27 (BC_2, * , control, 1 ),"&
" 26 (BC_7, RSV10 , bidir, X, 25, 1, Z ),"&
" 25 (BC_2, * , control, 1 ),"&
" 24 (BC_7, RSV11 , bidir, X, 23, 1, Z ),"&
" 23 (BC_2, * , control, 1 ),"&
" 22 (BC_7, RSV12 , bidir, X, 21, 1, Z ),"&
" 21 (BC_2, * , control, 1 ),"&
" 20 (BC_7, NMI0 , bidir, X, 19, 1, Z ),"&
" 19 (BC_2, * , control, 1 ),"&
" 18 (BC_7, NMI1 , bidir, X, 17, 1, Z ),"&
" 17 (BC_2, * , control, 1 ),"&
" 16 (BC_7, NMI2 , bidir, X, 15, 1, Z ),"&
" 15 (BC_2, * , control, 1 ),"&
" 14 (BC_1, HITEMPz , input, X ),"&
" 13 (BC_7, RSV13 , bidir, X, 12, 1, Z ),"&
" 12 (BC_2, * , control, 1 ),"&
" 11 (BC_7, RSV14 , bidir, X, 10, 1, Z ),"&
" 10 (BC_2, * , control, 1 ),"&
" 9 (BC_7, TIMO0 , bidir, X, 8, 1, Z ),"&
" 8 (BC_2, * , control, 1 ),"&
" 7 (BC_7, TIMO1 , bidir, X, 6, 1, Z ),"&
" 6 (BC_2, * , control, 1 ),"&
" 5 (BC_1, TIMI0 , input, X ),"&
" 4 (BC_1, TIMI1 , input, X ),"&
" 3 (BC_7, SDA , bidir, X, 2, 1, WEAK1 ),"&
" 2 (BC_2, * , control, 1 ),"&
" 1 (BC_7, SCL , bidir, X, 0, 1, WEAK1 ),"&
" 0 (BC_2, * , control, 1 ) ";
attribute DESIGN_WARNING of TMS320TCI6487_88 : entity is
"According to simulation, BSD JTAG TAP may not work correctly unless "&
" device has completed RESET sequence first. "&
"Forcing PORz low then release (no clock pulses required) would meet "&
" the requirement. "&
" "&
"In order to enter bscan mode correctly, TMS must be low at the "&
"rising edge of TRSTz and at least one cycle after TRSTz is high. ";
end TMS320TCI6487_88;