-- **********************************************************************
--
-- FILE : zl30158_v1.bsd
-- generated by Cz.P. as zl30158 on Tue Jan 18 13:13:46 EST 2011
-- using p.jtag.bsd rev 3.5 - 9 May, 2007
--
-- BSDL description for top level entity zl30158
-- Device : ZL30158 Synchronous Ethernet Clock Generator
-- Package : 100-pin BGA
--
-- Number of BSC cells: 57
--
-- **********************************************************************
-- Modification History:
-- Initial release: Tue Jan 18 13:13:46 EST 2011
-- **********************************************************************
--
-- IMPORTANT NOTICE
--
-- This information is for modeling purposes only, and is not guaranteed.
--
-- This information is provided "as is" without warranty of any kind.
-- It may contain technical inaccuracies or typographical errors.
--
-- ZARLINK and ZL30158 are trademarks of ZARLINK Semiconductor. ZARLINK
-- products, marketed under trademarks, are protected under numerous US
-- and foreign patents and pending applications, maskwork rights, and
-- copyrights.
--
-- ZARLINK reserves the right to make changes to any products and
-- services at any time without notice. ZARLINK assumes no
-- responsibility or liability arising out of the application or use of
-- any information, product, or service described herein except as
-- expressly agreed to in writing by ZARLINK Corporation. ZARLINK
-- customers are advised to obtain the latest version of device
-- specifications before relying on any published information and before
-- placing orders for products or services.
--
-- ======================================================================
-- This BSDL model has been validated for syntax and semantics compliance
-- to IEEE 1149.1 using ASSET/Agilent BSDL Validation Service.
-- ======================================================================
--
-- ********************************************************************
--
-- SPECIAL NOTES
--
-- 1. All instruction opcodes other than those defined in this file
-- should be considered PRIVATE.
--
-- ********************************************************************
entity zl30158 is
generic(PHYSICAL_PIN_MAP : string := "CABGA_PACKAGE");
port (
AT: linkage bit;
CS_B_ASEL0: in bit;
FILTER: linkage bit;
FILTER_REF: linkage bit;
GPIO: inout bit_vector (0 to 6);
HPDIFF0_N: linkage bit;
HPDIFF0_P: linkage bit;
HPDIFF1_N: linkage bit;
HPDIFF1_P: linkage bit;
HPDIFF2_N: linkage bit;
HPDIFF2_P: linkage bit;
HPDIFF3_N: linkage bit;
HPDIFF3_P: linkage bit;
HPOUTCLK0: linkage bit;
HPOUTCLK1: linkage bit;
OSCI: linkage bit;
OSCO: linkage bit;
PWR_B: in bit;
REF0_N: linkage bit;
REF0_P: in bit;
REF1_N: linkage bit;
REF1_P: in bit;
SCL_SCK: in bit;
SI_SDA: in bit;
SO_ASEL1: inout bit;
TCK: in bit;
TDI: in bit;
TDO: out bit;
TEST_EN: inout bit;
TMS: in bit;
TRST_B: in bit;
AVCORE: linkage bit_vector (1 to 2);
AVDD: linkage bit_vector (1 to 7);
AVSS: linkage bit_vector (1 to 9);
VCORE: linkage bit_vector (1 to 3);
VDD_IO: linkage bit;
VSS: linkage bit_vector (1 to 5)
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of zl30158 : entity is
"STD_1149_1_2001";
attribute PIN_MAP of zl30158 : entity is PHYSICAL_PIN_MAP;
constant CABGA_PACKAGE : PIN_MAP_STRING :=
"AT : C5 , " &
"CS_B_ASEL0 : E7 , " &
"FILTER : A5 , " &
"FILTER_REF : B5 , " &
"GPIO :(E6 , " & -- GPIO[0]
"F8 , " & -- GPIO[1]
"F7 , " & -- GPIO[2]
"F6 , " & -- GPIO[3]
"H1 , " & -- GPIO[4]
"E3 , " & -- GPIO[5]
"G1 ), " & -- GPIO[6]
"HPDIFF0_N : C1 , " &
"HPDIFF0_P : C2 , " &
"HPDIFF1_N : B1 , " &
"HPDIFF1_P : A1 , " &
"HPDIFF2_N : B2 , " &
"HPDIFF2_P : A2 , " &
"HPDIFF3_N : B3 , " &
"HPDIFF3_P : A3 , " &
"HPOUTCLK0 : E2 , " &
"HPOUTCLK1 : E1 , " &
"OSCI : B7 , " &
"OSCO : A7 , " &
"PWR_B : D8 , " &
"REF0_N : H5 , " &
"REF0_P : H4 , " &
"REF1_N : H7 , " &
"REF1_P : H6 , " &
"SCL_SCK : E8 , " &
"SI_SDA : H2 , " &
"SO_ASEL1 : G2 , " &
"TCK : H8 , " &
"TDI : G8 , " &
"TDO : H3 , " &
"TEST_EN : F3 , " &
"TMS : G7 , " &
"TRST_B : G3 , " &
"AVCORE :(C4, G4)," &
"AVDD :(B4, B6, B8, D2, D3, F2, G6)," &
"AVSS :(A4, A6, A8, C3, C6, C7, D1, F1, G5)," &
"VCORE :(E4, F4, F5)," &
"VDD_IO : D7 , " &
"VSS :(C8, D4, D5, D6, E5)";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6,BOTH);
attribute TAP_SCAN_RESET of TRST_B : signal is true;
--
-- NOTE: All instruction opcodes other than those defined in this file
-- should be considered PRIVATE.
--
attribute INSTRUCTION_LENGTH of zl30158 : entity is 6;
attribute INSTRUCTION_OPCODE of zl30158 : entity is
"bypass (111111)," &
"extest (000000)," &
"highz (000110)," &
"idcode (000101)," &
"preload (000100)," &
"sample (000001)" ;
attribute INSTRUCTION_CAPTURE of zl30158 : entity is "xxxx01";
attribute IDCODE_REGISTER of zl30158 : entity is
"0001" & -- version
"0111010111001110" & -- part number
"00010100101" & -- manufacturer id
"1";
attribute REGISTER_ACCESS of zl30158 : entity is
"boundary (extest, sample, preload)," &
"bypass (bypass, highz)," &
"device_id (idcode)" ;
attribute BOUNDARY_LENGTH of zl30158 : entity is 57;
attribute BOUNDARY_REGISTER of zl30158 : entity is
-- num cell port function safe ccel disval rslt
" 0 ( BC_0, *, internal, X) ," &
" 1 ( BC_0, *, internal, 1) ," &
" 2 ( BC_0, *, internal, X) ," &
" 3 ( BC_0, *, internal, 1) ," &
" 4 ( BC_0, *, internal, X) ," &
" 5 ( BC_0, *, internal, 1) ," &
" 6 ( BC_0, *, internal, X) ," &
" 7 ( BC_0, *, internal, 1) ," &
" 8 ( BC_0, *, internal, X) ," &
" 9 ( BC_0, *, internal, X) ," &
" 10 ( BC_0, *, internal, 1) ," &
" 11 ( BC_0, *, internal, X) ," &
" 12 ( BC_0, *, internal, X) ," &
" 13 ( BC_5, SI_SDA, input, X) ," &
" 14 ( BC_7, SO_ASEL1, bidir, X, 15, 1, Z) ," &
" 15 ( BC_2, *, control, 1) ," &
" 16 ( BC_7, GPIO(4), bidir, X, 17, 1, Z) ," &
" 17 ( BC_2, *, control, 1) ," &
" 18 ( BC_7, GPIO(6), bidir, X, 19, 1, Z) ," &
" 19 ( BC_2, *, control, 1) ," &
" 20 ( BC_0, *, internal, X) ," &
" 21 ( BC_0, *, internal, 1) ," &
" 22 ( BC_7, TEST_EN, bidir, X, 23, 1, Z) ," &
" 23 ( BC_2, *, control, 1) ," &
" 24 ( BC_7, GPIO(5), bidir, X, 25, 1, Z) ," &
" 25 ( BC_2, *, control, 1) ," &
" 26 ( BC_7, GPIO(0), bidir, X, 27, 1, Z) ," &
" 27 ( BC_2, *, control, 1) ," &
" 28 ( BC_0, *, internal, X) ," &
" 29 ( BC_4, PWR_B, input, X) ," &
" 30 ( BC_0, *, internal, X) ," &
" 31 ( BC_0, *, internal, 1) ," &
" 32 ( BC_0, *, internal, X) ," &
" 33 ( BC_0, *, internal, 1) ," &
" 34 ( BC_4, SCL_SCK, input, X) ," &
" 35 ( BC_7, GPIO(3), bidir, X, 36, 1, Z) ," &
" 36 ( BC_2, *, control, 1) ," &
" 37 ( BC_7, GPIO(1), bidir, X, 38, 1, Z) ," &
" 38 ( BC_2, *, control, 1) ," &
" 39 ( BC_5, CS_B_ASEL0, input, X) ," &
" 40 ( BC_7, GPIO(2), bidir, X, 41, 1, Z) ," &
" 41 ( BC_2, *, control, 1) ," &
" 42 ( BC_0, *, internal, X) ," &
" 43 ( BC_0, *, internal, 1) ," &
" 44 ( BC_0, *, internal, X) ," &
" 45 ( BC_0, *, internal, X) ," &
" 46 ( BC_0, *, internal, 1) ," &
" 47 ( BC_0, *, internal, X) ," &
" 48 ( BC_0, *, internal, 1) ," &
" 49 ( BC_0, *, internal, X) ," &
" 50 ( BC_0, *, internal, 1) ," &
" 51 ( BC_0, *, internal, X) ," &
" 52 ( BC_0, *, internal, 1) ," &
" 53 ( BC_0, *, internal, X) ," &
" 54 ( BC_0, *, internal, X) ," &
" 55 ( BC_5, REF1_P, input, X) ," &
" 56 ( BC_4, REF0_P, input, X) ";
end zl30158;
------------- end of BSDL description for the zl30158 ----------