--$ XILINX$RCSfile: xc5202_vq100.bsd,v $
--$ XILINX$Revision: 1.3 $
--
-- BSDL file for device XC5202, package VQ100
-- Xilinx, Inc. $State: FINAL $ $Date: 1997-11-12 21:35:44+00 $
-- Generated by createBSDL 2.6
--
-- For technical support, contact Xilinx as follows:
-- North America 1-800-255-7778 hotline@xilinx.com
-- United Kingdom (44) 1932 820821 ukhelp@xilinx.com
-- France (33) 1 3463 0100 frhelp@xilinx.com
-- Germany (49) 89 991 54930 dlhelp@xilinx.com
-- Japan (81) 3-3297-9163 jhotline@xilinx.com
--
-- BSDL verified to conform to 1149.1b-1994 syntax. This device has been
-- tested by the Intellitech 1149.1 Verification Lab using the Intellitech
-- Eclipse(TM) Scan Diagnostic Tool and the Intellitech RCT(TM). This
-- device has been verified to operate according to the BSDL provided,
-- and is compatible with the IEEE 1149.1 standard when the operating
-- instructions in the BSDL are followed.
-- PH: 603-868-7116 or email: scansupport@intellitech.com
--
-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect
-- the post-configuration JTAG behavior (if any), edit this file as described
-- below. Many of these changes are demonstrated by commented-out template
-- lines preceeding the lines they would replace:
--
-- 1. Enable USER instructions as appropriate (see below).
-- 2. For inputs using uncontrolled paths (e.g. PGCK), change
-- boundary cell function from 'input' to 'clock' or 'observe_only'.
-- 3. Set disable result of all pads as configured.
-- 4. Set safe state of boundary cells as necessary.
-- 5. Set safe state of INIT output to X, or as necessary (see below).
-- 6. Rename entity if necessary to avoid name collisions.
-- 7. Change INIT port direction from "in" to "inout" (see below).
-- 8. Change COMPLIANCE_PATTERNS to "(PROGRAM) (1)" (see below).
-- 9. Change INIT boundary cells from internal to controlr, output3,
-- and input, respectively (see below).
-- 10. Remove the design warning regarding keeping INIT low.
--
-- NOTE: Post-configuration JTAG is available only if the BSCAN symbol
-- is instantiated in the FPGA design.
-- NOTE: PULLUP symbols must be instantiated on the TMS and TDI pins
-- in the FPGA design to comply with IEEE Std. 1149.1-1993.
entity XC5202_VQ100 is
generic (PHYSICAL_PIN_MAP : string := "VQ100" );
port (
CCLK: linkage bit;
DONE: linkage bit;
GND: linkage bit_vector (1 to 8);
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the following line so
-- that INIT is of type inout.
-- INIT: inout bit;
INIT: in bit;
IO3: inout bit;
IO4: inout bit;
IO5: inout bit;
IO6: inout bit;
IO7: inout bit;
IO8: inout bit;
IO9: inout bit;
IO10: inout bit;
IO11: inout bit;
IO12: inout bit;
IO15: inout bit;
IO16: inout bit;
IO20: inout bit;
IO22: inout bit;
IO23: inout bit;
IO24: inout bit;
IO27: inout bit;
IO28: inout bit;
IO29: inout bit;
IO31: inout bit;
IO32: inout bit;
IO33: inout bit;
IO34: inout bit;
IO35: inout bit;
IO36: inout bit;
IO42: inout bit;
IO43: inout bit;
IO44: inout bit;
IO45: inout bit;
IO46: inout bit;
IO47: inout bit;
IO48: inout bit;
IO49: inout bit;
IO50: inout bit;
IO54: inout bit;
IO55: inout bit;
IO56: inout bit;
IO57: inout bit;
IO58: inout bit;
IO59: inout bit;
IO60: inout bit;
IO61: inout bit;
IO62: inout bit;
IO63: inout bit;
IO68: inout bit;
IO69: inout bit;
IO70: inout bit;
IO71: inout bit;
IO72: inout bit;
IO73: inout bit;
IO74: inout bit;
IO75: inout bit;
IO76: inout bit;
IO77: inout bit;
IO80: inout bit;
IO81: inout bit;
IO82: inout bit;
IO84: inout bit;
IO85: inout bit;
IO86: inout bit;
IO87: inout bit;
IO88: inout bit;
IO89: inout bit;
IO94: inout bit;
IO95: inout bit;
IO96: inout bit;
IO97: inout bit;
IO98: inout bit;
IO99: inout bit;
IO100: inout bit;
IO101: inout bit;
IO102: inout bit;
IO103: inout bit;
M0: inout bit;
M1: inout bit;
M2: inout bit;
PROGRAM: in bit;
TCK: in bit;
TDI: in bit;
TDO: out bit;
TMS: in bit;
VDD: linkage bit_vector (1 to 8)
); --end port list
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of XC5202_VQ100 : entity is
"STD_1149_1_1993";
attribute PIN_MAP of XC5202_VQ100 : entity is PHYSICAL_PIN_MAP;
constant VQ100: PIN_MAP_STRING:=
"CCLK:74," &
"DONE:50," &
"GND:(88,1,11,23,38,49,64,77)," &
"INIT:36," &
"IO3:90," &
"IO4:91," &
"IO5:92," &
"IO6:93," &
"IO7:94," &
"IO8:95," &
"IO9:96," &
"IO10:97," &
"IO11:98," &
"IO12:99," &
"IO15:2," &
"IO16:3," &
"IO20:7," &
"IO22:8," &
"IO23:9," &
"IO24:10," &
"IO27:13," &
"IO28:14," &
"IO29:15," &
"IO31:16," &
"IO32:17," &
"IO33:18," &
"IO34:19," &
"IO35:20," &
"IO36:21," &
"IO42:27," &
"IO43:28," &
"IO44:29," &
"IO45:30," &
"IO46:31," &
"IO47:32," &
"IO48:33," &
"IO49:34," &
"IO50:35," &
"IO54:39," &
"IO55:40," &
"IO56:41," &
"IO57:42," &
"IO58:43," &
"IO59:44," &
"IO60:45," &
"IO61:46," &
"IO62:47," &
"IO63:48," &
"IO68:53," &
"IO69:54," &
"IO70:55," &
"IO71:56," &
"IO72:57," &
"IO73:58," &
"IO74:59," &
"IO75:60," &
"IO76:61," &
"IO77:62," &
"IO80:65," &
"IO81:66," &
"IO82:67," &
"IO84:68," &
"IO85:69," &
"IO86:70," &
"IO87:71," &
"IO88:72," &
"IO89:73," &
"IO94:78," &
"IO95:79," &
"IO96:80," &
"IO97:81," &
"IO98:82," &
"IO99:83," &
"IO100:84," &
"IO101:85," &
"IO102:86," &
"IO103:87," &
"M0:24," &
"M1:22," &
"M2:26," &
"PROGRAM:52," &
"TCK:5," &
"TDI:4," &
"TDO:76," &
"TMS:6," &
"VDD:(89,100,12,25,37,51,63,75)";
--end pin map
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (2.0e6, LOW);
-- This is conservative. Real max is expected to be (~5MHz, BOTH).
attribute COMPLIANCE_PATTERNS of XC5202_VQ100 : entity is
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the corresponding line
-- below.
-- "(PROGRAM) (1)";
--
-- NOTE: If INIT has been high or floating since the later of power-on
-- and the last rising transition of PROGRAM, then the device may
-- be in configuration mode in which case some JTAG instructions
-- will not be available.
"(INIT,PROGRAM) (01)";
attribute INSTRUCTION_LENGTH of XC5202_VQ100 : entity is 3;
attribute INSTRUCTION_OPCODE of XC5202_VQ100 : entity is
"RESERVED (110)," &
"READBACK (100)," & -- Not available during configuration
"CONFIGURE (101)," & -- Not available during configuration
"USER2 (011)," & -- Not available until after configuration
"USER1 (010)," & -- Not available until after configuration
"SAMPLE (001)," & -- Internal capture not valid until after config
"EXTEST (000)," & -- Not available during configuration
"BYPASS (111)";
attribute INSTRUCTION_CAPTURE of XC5202_VQ100 : entity is "X01";
-- MSB of instruction capture is low during configuration.
-- If the device is configured, and a USER instruction is implemented
-- and not private to the FPGA designer, then it should be removed
-- from INSTRUCTION_PRIVATE, and the target register should be defined
-- in REGISTER_ACCESS.
attribute INSTRUCTION_PRIVATE of XC5202_VQ100 : entity is
"USER1," &
"USER2," &
"READBACK," &
"RESERVED," &
"CONFIGURE";
attribute REGISTER_ACCESS of XC5202_VQ100 : entity is
-- "<reg_name>[<length>] (USER1)," &
-- "<reg_name>[<length>] (USER2)," &
"BYPASS (BYPASS)," &
"BOUNDARY (SAMPLE,EXTEST)";
attribute BOUNDARY_LENGTH of XC5202_VQ100 : entity is 385;
attribute BOUNDARY_REGISTER of XC5202_VQ100 : entity is
-- cellnum (type, port, function, safe[, ccell, disval, disrslt])
" 0 (BC_1, *, internal, X)," &
" 1 (BC_1, *, internal, X)," &
" 2 (BC_1, *, internal, X)," &
" 3 (BC_1, *, internal, X)," &
" 4 (BC_1, *, internal, X)," &
" 5 (BC_1, *, internal, X)," &
" 6 (BC_1, *, internal, X)," &
" 7 (BC_1, *, internal, X)," &
" 8 (BC_1, *, internal, X)," &
" 9 (BC_1, *, controlr, 1)," &
" 10 (BC_1, IO94, output3, X, 9, 1, PULL1)," &
" 11 (BC_1, IO94, input, X)," &
" 12 (BC_1, *, internal, X)," &
" 13 (BC_1, *, internal, X)," &
" 14 (BC_1, *, internal, X)," &
" 15 (BC_1, *, controlr, 1)," &
" 16 (BC_1, IO95, output3, X, 15, 1, PULL1)," &
" 17 (BC_1, IO95, input, X)," &
" 18 (BC_1, *, controlr, 1)," &
" 19 (BC_1, IO96, output3, X, 18, 1, PULL1)," &
" 20 (BC_1, IO96, input, X)," &
" 21 (BC_1, *, controlr, 1)," &
" 22 (BC_1, IO97, output3, X, 21, 1, PULL1)," &
" 23 (BC_1, IO97, input, X)," &
" 24 (BC_1, *, internal, X)," &
" 25 (BC_1, *, internal, X)," &
" 26 (BC_1, *, internal, X)," &
" 27 (BC_1, *, controlr, 1)," &
" 28 (BC_1, IO98, output3, X, 27, 1, PULL1)," &
" 29 (BC_1, IO98, input, X)," &
" 30 (BC_1, *, controlr, 1)," &
" 31 (BC_1, IO99, output3, X, 30, 1, PULL1)," &
" 32 (BC_1, IO99, input, X)," &
" 33 (BC_1, *, controlr, 1)," &
" 34 (BC_1, IO100, output3, X, 33, 1, PULL1)," &
" 35 (BC_1, IO100, input, X)," &
" 36 (BC_1, *, internal, X)," &
" 37 (BC_1, *, internal, X)," &
" 38 (BC_1, *, internal, X)," &
" 39 (BC_1, *, controlr, 1)," &
" 40 (BC_1, IO101, output3, X, 39, 1, PULL1)," &
" 41 (BC_1, IO101, input, X)," &
" 42 (BC_1, *, controlr, 1)," &
" 43 (BC_1, IO102, output3, X, 42, 1, PULL1)," &
" 44 (BC_1, IO102, input, X)," &
" 45 (BC_1, *, controlr, 1)," &
" 46 (BC_1, IO103, output3, X, 45, 1, PULL1)," &
" 47 (BC_1, IO103, input, X)," &
" 48 (BC_1, *, internal, X)," &
" 49 (BC_1, *, internal, X)," &
" 50 (BC_1, *, internal, X)," &
" 51 (BC_1, *, controlr, 1)," &
" 52 (BC_1, IO3, output3, X, 51, 1, PULL1)," &
" 53 (BC_1, IO3, input, X)," &
" 54 (BC_1, *, controlr, 1)," &
" 55 (BC_1, IO4, output3, X, 54, 1, PULL1)," &
" 56 (BC_1, IO4, input, X)," &
" 57 (BC_1, *, controlr, 1)," &
" 58 (BC_1, IO5, output3, X, 57, 1, PULL1)," &
" 59 (BC_1, IO5, input, X)," &
" 60 (BC_1, *, internal, X)," &
" 61 (BC_1, *, internal, X)," &
" 62 (BC_1, *, internal, X)," &
" 63 (BC_1, *, controlr, 1)," &
" 64 (BC_1, IO6, output3, X, 63, 1, PULL1)," &
" 65 (BC_1, IO6, input, X)," &
" 66 (BC_1, *, controlr, 1)," &
" 67 (BC_1, IO7, output3, X, 66, 1, PULL1)," &
" 68 (BC_1, IO7, input, X)," &
" 69 (BC_1, *, controlr, 1)," &
" 70 (BC_1, IO8, output3, X, 69, 1, PULL1)," &
" 71 (BC_1, IO8, input, X)," &
" 72 (BC_1, *, internal, X)," &
" 73 (BC_1, *, internal, X)," &
" 74 (BC_1, *, internal, X)," &
" 75 (BC_1, *, internal, X)," &
" 76 (BC_1, *, internal, X)," &
" 77 (BC_1, *, internal, X)," &
" 78 (BC_1, *, controlr, 1)," &
" 79 (BC_1, IO9, output3, X, 78, 1, PULL1)," &
" 80 (BC_1, IO9, input, X)," &
" 81 (BC_1, *, controlr, 1)," &
" 82 (BC_1, IO10, output3, X, 81, 1, PULL1)," &
" 83 (BC_1, IO10, input, X)," &
" 84 (BC_1, *, internal, X)," &
" 85 (BC_1, *, internal, X)," &
" 86 (BC_1, *, internal, X)," &
" 87 (BC_1, *, internal, X)," &
" 88 (BC_1, *, internal, X)," &
" 89 (BC_1, *, internal, X)," &
" 90 (BC_1, *, controlr, 1)," &
" 91 (BC_1, IO11, output3, X, 90, 1, PULL1)," &
" 92 (BC_1, IO11, input, X)," &
" 93 (BC_1, *, controlr, 1)," &
" 94 (BC_1, IO12, output3, X, 93, 1, PULL1)," &
" 95 (BC_1, IO12, input, X)," &
" 96 (BC_1, *, internal, X)," &
" 97 (BC_1, *, internal, X)," &
" 98 (BC_1, *, internal, X)," &
" 99 (BC_1, *, internal, X)," &
" 100 (BC_1, *, internal, X)," &
" 101 (BC_1, *, internal, X)," &
" 102 (BC_1, *, controlr, 1)," &
" 103 (BC_1, IO15, output3, X, 102, 1, PULL1)," &
" 104 (BC_1, IO15, input, X)," &
" 105 (BC_1, *, controlr, 1)," &
" 106 (BC_1, IO16, output3, X, 105, 1, PULL1)," &
" 107 (BC_1, IO16, input, X)," &
" 108 (BC_1, *, internal, X)," &
" 109 (BC_1, *, internal, X)," &
" 110 (BC_1, *, internal, X)," &
" 111 (BC_1, *, internal, X)," &
" 112 (BC_1, *, internal, X)," &
" 113 (BC_1, *, internal, X)," &
" 114 (BC_1, *, internal, X)," &
" 115 (BC_1, *, internal, X)," &
" 116 (BC_1, *, internal, X)," &
" 117 (BC_1, *, internal, X)," &
" 118 (BC_1, *, internal, X)," &
" 119 (BC_1, *, internal, X)," &
" 120 (BC_1, *, internal, X)," &
" 121 (BC_1, *, internal, X)," &
" 122 (BC_1, *, internal, X)," &
" 123 (BC_1, *, controlr, 1)," &
" 124 (BC_1, IO20, output3, X, 123, 1, PULL1)," &
" 125 (BC_1, IO20, input, X)," &
" 126 (BC_1, *, internal, 1)," & -- IO21.T
" 127 (BC_1, *, internal, X)," & -- IO21.O
" 128 (BC_1, *, internal, X)," & -- IO21.I
" 129 (BC_1, *, controlr, 1)," &
" 130 (BC_1, IO22, output3, X, 129, 1, PULL1)," &
" 131 (BC_1, IO22, input, X)," &
" 132 (BC_1, *, internal, X)," &
" 133 (BC_1, *, internal, X)," &
" 134 (BC_1, *, internal, X)," &
" 135 (BC_1, *, controlr, 1)," &
" 136 (BC_1, IO23, output3, X, 135, 1, PULL1)," &
" 137 (BC_1, IO23, input, X)," &
" 138 (BC_1, *, controlr, 1)," &
" 139 (BC_1, IO24, output3, X, 138, 1, PULL1)," &
" 140 (BC_1, IO24, input, X)," &
" 141 (BC_1, *, controlr, 1)," &
" 142 (BC_1, IO27, output3, X, 141, 1, PULL1)," &
" 143 (BC_1, IO27, input, X)," &
" 144 (BC_1, *, internal, X)," &
" 145 (BC_1, *, internal, X)," &
" 146 (BC_1, *, internal, X)," &
" 147 (BC_1, *, controlr, 1)," &
" 148 (BC_1, IO28, output3, X, 147, 1, PULL1)," &
" 149 (BC_1, IO28, input, X)," &
" 150 (BC_1, *, controlr, 1)," &
" 151 (BC_1, IO29, output3, X, 150, 1, PULL1)," &
" 152 (BC_1, IO29, input, X)," &
" 153 (BC_1, *, internal, 1)," & -- IO30.T
" 154 (BC_1, *, internal, X)," & -- IO30.O
" 155 (BC_1, *, internal, X)," & -- IO30.I
" 156 (BC_1, *, internal, X)," &
" 157 (BC_1, *, internal, X)," &
" 158 (BC_1, *, internal, X)," &
" 159 (BC_1, *, controlr, 1)," &
" 160 (BC_1, IO31, output3, X, 159, 1, PULL1)," &
" 161 (BC_1, IO31, input, X)," &
" 162 (BC_1, *, controlr, 1)," &
" 163 (BC_1, IO32, output3, X, 162, 1, PULL1)," &
" 164 (BC_1, IO32, input, X)," &
" 165 (BC_1, *, controlr, 1)," &
" 166 (BC_1, IO33, output3, X, 165, 1, PULL1)," &
" 167 (BC_1, IO33, input, X)," &
" 168 (BC_1, *, internal, X)," &
" 169 (BC_1, *, internal, X)," &
" 170 (BC_1, *, internal, X)," &
" 171 (BC_1, *, controlr, 1)," &
" 172 (BC_1, IO34, output3, X, 171, 1, PULL1)," &
" 173 (BC_1, IO34, input, X)," &
" 174 (BC_1, *, controlr, 1)," &
" 175 (BC_1, IO35, output3, X, 174, 1, PULL1)," &
" 176 (BC_1, IO35, input, X)," &
" 177 (BC_1, *, controlr, 1)," &
" 178 (BC_1, IO36, output3, X, 177, 1, PULL1)," &
" 179 (BC_1, IO36, input, X)," &
" 180 (BC_1, *, internal, X)," &
" 181 (BC_1, *, internal, X)," &
" 182 (BC_1, *, internal, X)," &
" 183 (BC_1, *, internal, X)," &
" 184 (BC_1, *, internal, X)," &
" 185 (BC_1, *, internal, X)," &
" 186 (BC_1, *, controlr, 1)," &
" 187 (BC_1, M1, output3, X, 186, 1, PULL1)," &
" 188 (BC_1, M1, input, X)," &
" 189 (BC_1, *, controlr, 1)," &
" 190 (BC_1, M0, output3, X, 189, 1, PULL1)," &
" 191 (BC_1, M0, input, X)," &
" 192 (BC_1, *, controlr, 1)," &
" 193 (BC_1, M2, output3, X, 192, 1, PULL1)," &
" 194 (BC_1, M2, input, X)," &
" 195 (BC_1, *, controlr, 1)," &
" 196 (BC_1, IO42, output3, X, 195, 1, PULL1)," &
" 197 (BC_1, IO42, input, X)," &
" 198 (BC_1, *, internal, X)," &
" 199 (BC_1, *, internal, X)," &
" 200 (BC_1, *, internal, X)," &
" 201 (BC_1, *, internal, X)," &
" 202 (BC_1, *, internal, X)," &
" 203 (BC_1, *, internal, X)," &
" 204 (BC_1, *, controlr, 1)," &
" 205 (BC_1, IO43, output3, X, 204, 1, PULL1)," &
" 206 (BC_1, IO43, input, X)," &
" 207 (BC_1, *, controlr, 1)," &
" 208 (BC_1, IO44, output3, X, 207, 1, PULL1)," &
" 209 (BC_1, IO44, input, X)," &
" 210 (BC_1, *, controlr, 1)," &
" 211 (BC_1, IO45, output3, X, 210, 1, PULL1)," &
" 212 (BC_1, IO45, input, X)," &
" 213 (BC_1, *, internal, X)," &
" 214 (BC_1, *, internal, X)," &
" 215 (BC_1, *, internal, X)," &
" 216 (BC_1, *, controlr, 1)," &
" 217 (BC_1, IO46, output3, X, 216, 1, PULL1)," &
" 218 (BC_1, IO46, input, X)," &
" 219 (BC_1, *, controlr, 1)," &
" 220 (BC_1, IO47, output3, X, 219, 1, PULL1)," &
" 221 (BC_1, IO47, input, X)," &
" 222 (BC_1, *, controlr, 1)," &
" 223 (BC_1, IO48, output3, X, 222, 1, PULL1)," &
" 224 (BC_1, IO48, input, X)," &
" 225 (BC_1, *, internal, X)," &
" 226 (BC_1, *, internal, X)," &
" 227 (BC_1, *, internal, X)," &
" 228 (BC_1, *, controlr, 1)," &
" 229 (BC_1, IO49, output3, X, 228, 1, PULL1)," &
" 230 (BC_1, IO49, input, X)," &
" 231 (BC_1, *, controlr, 1)," &
" 232 (BC_1, IO50, output3, X, 231, 1, PULL1)," &
" 233 (BC_1, IO50, input, X)," &
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the following line.
-- Repeat for registers 234 through 236.
-- " 234 (BC_1, *, controlr, 1)," &
" 234 (BC_1, *, internal, 1)," &
-- " 235 (BC_1, INIT, output3, X, 234, 1, PULL1)," &
" 235 (BC_1, *, internal, 0)," &
-- " 236 (BC_1, INIT, input, X)," &
" 236 (BC_1, *, internal, X)," &
" 237 (BC_1, *, internal, X)," &
" 238 (BC_1, *, internal, X)," &
" 239 (BC_1, *, internal, X)," &
" 240 (BC_1, *, controlr, 1)," &
" 241 (BC_1, IO54, output3, X, 240, 1, PULL1)," &
" 242 (BC_1, IO54, input, X)," &
" 243 (BC_1, *, controlr, 1)," &
" 244 (BC_1, IO55, output3, X, 243, 1, PULL1)," &
" 245 (BC_1, IO55, input, X)," &
" 246 (BC_1, *, controlr, 1)," &
" 247 (BC_1, IO56, output3, X, 246, 1, PULL1)," &
" 248 (BC_1, IO56, input, X)," &
" 249 (BC_1, *, internal, X)," &
" 250 (BC_1, *, internal, X)," &
" 251 (BC_1, *, internal, X)," &
" 252 (BC_1, *, controlr, 1)," &
" 253 (BC_1, IO57, output3, X, 252, 1, PULL1)," &
" 254 (BC_1, IO57, input, X)," &
" 255 (BC_1, *, controlr, 1)," &
" 256 (BC_1, IO58, output3, X, 255, 1, PULL1)," &
" 257 (BC_1, IO58, input, X)," &
" 258 (BC_1, *, controlr, 1)," &
" 259 (BC_1, IO59, output3, X, 258, 1, PULL1)," &
" 260 (BC_1, IO59, input, X)," &
" 261 (BC_1, *, internal, X)," &
" 262 (BC_1, *, internal, X)," &
" 263 (BC_1, *, internal, X)," &
" 264 (BC_1, *, controlr, 1)," &
" 265 (BC_1, IO60, output3, X, 264, 1, PULL1)," &
" 266 (BC_1, IO60, input, X)," &
" 267 (BC_1, *, controlr, 1)," &
" 268 (BC_1, IO61, output3, X, 267, 1, PULL1)," &
" 269 (BC_1, IO61, input, X)," &
" 270 (BC_1, *, internal, X)," &
" 271 (BC_1, *, internal, X)," &
" 272 (BC_1, *, internal, X)," &
" 273 (BC_1, *, internal, X)," &
" 274 (BC_1, *, internal, X)," &
" 275 (BC_1, *, internal, X)," &
" 276 (BC_1, *, controlr, 1)," &
" 277 (BC_1, IO62, output3, X, 276, 1, PULL1)," &
" 278 (BC_1, IO62, input, X)," &
" 279 (BC_1, *, controlr, 1)," &
" 280 (BC_1, IO63, output3, X, 279, 1, PULL1)," &
" 281 (BC_1, IO63, input, X)," &
" 282 (BC_1, *, internal, X)," &
" 283 (BC_1, *, internal, X)," &
" 284 (BC_1, *, internal, X)," &
" 285 (BC_1, *, internal, X)," &
" 286 (BC_1, *, internal, X)," &
" 287 (BC_1, *, internal, X)," &
" 288 (BC_1, *, controlr, 1)," &
" 289 (BC_1, IO68, output3, X, 288, 1, PULL1)," &
" 290 (BC_1, IO68, input, X)," &
" 291 (BC_1, *, controlr, 1)," &
" 292 (BC_1, IO69, output3, X, 291, 1, PULL1)," &
" 293 (BC_1, IO69, input, X)," &
" 294 (BC_1, *, internal, X)," &
" 295 (BC_1, *, internal, X)," &
" 296 (BC_1, *, internal, X)," &
" 297 (BC_1, *, internal, X)," &
" 298 (BC_1, *, internal, X)," &
" 299 (BC_1, *, internal, X)," &
" 300 (BC_1, *, controlr, 1)," &
" 301 (BC_1, IO70, output3, X, 300, 1, PULL1)," &
" 302 (BC_1, IO70, input, X)," &
" 303 (BC_1, *, controlr, 1)," &
" 304 (BC_1, IO71, output3, X, 303, 1, PULL1)," &
" 305 (BC_1, IO71, input, X)," &
" 306 (BC_1, *, controlr, 1)," &
" 307 (BC_1, IO72, output3, X, 306, 1, PULL1)," &
" 308 (BC_1, IO72, input, X)," &
" 309 (BC_1, *, internal, X)," &
" 310 (BC_1, *, internal, X)," &
" 311 (BC_1, *, internal, X)," &
" 312 (BC_1, *, controlr, 1)," &
" 313 (BC_1, IO73, output3, X, 312, 1, PULL1)," &
" 314 (BC_1, IO73, input, X)," &
" 315 (BC_1, *, controlr, 1)," &
" 316 (BC_1, IO74, output3, X, 315, 1, PULL1)," &
" 317 (BC_1, IO74, input, X)," &
" 318 (BC_1, *, controlr, 1)," &
" 319 (BC_1, IO75, output3, X, 318, 1, PULL1)," &
" 320 (BC_1, IO75, input, X)," &
" 321 (BC_1, *, internal, X)," &
" 322 (BC_1, *, internal, X)," &
" 323 (BC_1, *, internal, X)," &
" 324 (BC_1, *, controlr, 1)," &
" 325 (BC_1, IO76, output3, X, 324, 1, PULL1)," &
" 326 (BC_1, IO76, input, X)," &
" 327 (BC_1, *, controlr, 1)," &
" 328 (BC_1, IO77, output3, X, 327, 1, PULL1)," &
" 329 (BC_1, IO77, input, X)," &
" 330 (BC_1, *, internal, X)," &
" 331 (BC_1, *, internal, X)," &
" 332 (BC_1, *, internal, X)," &
" 333 (BC_1, *, internal, X)," &
" 334 (BC_1, *, internal, X)," &
" 335 (BC_1, *, internal, X)," &
" 336 (BC_1, *, controlr, 1)," &
" 337 (BC_1, IO80, output3, X, 336, 1, PULL1)," &
" 338 (BC_1, IO80, input, X)," &
" 339 (BC_1, *, controlr, 1)," &
" 340 (BC_1, IO81, output3, X, 339, 1, PULL1)," &
" 341 (BC_1, IO81, input, X)," &
" 342 (BC_1, *, controlr, 1)," &
" 343 (BC_1, IO82, output3, X, 342, 1, PULL1)," &
" 344 (BC_1, IO82, input, X)," &
" 345 (BC_1, *, internal, X)," &
" 346 (BC_1, *, internal, X)," &
" 347 (BC_1, *, internal, X)," &
" 348 (BC_1, *, internal, 1)," & -- IO83.T
" 349 (BC_1, *, internal, X)," & -- IO83.O
" 350 (BC_1, *, internal, X)," & -- IO83.I
" 351 (BC_1, *, controlr, 1)," &
" 352 (BC_1, IO84, output3, X, 351, 1, PULL1)," &
" 353 (BC_1, IO84, input, X)," &
" 354 (BC_1, *, internal, X)," &
" 355 (BC_1, *, internal, X)," &
" 356 (BC_1, *, internal, X)," &
" 357 (BC_1, *, internal, X)," &
" 358 (BC_1, *, internal, X)," &
" 359 (BC_1, *, internal, X)," &
" 360 (BC_1, *, controlr, 1)," &
" 361 (BC_1, IO85, output3, X, 360, 1, PULL1)," &
" 362 (BC_1, IO85, input, X)," &
" 363 (BC_1, *, controlr, 1)," &
" 364 (BC_1, IO86, output3, X, 363, 1, PULL1)," &
" 365 (BC_1, IO86, input, X)," &
" 366 (BC_1, *, controlr, 1)," &
" 367 (BC_1, IO87, output3, X, 366, 1, PULL1)," &
" 368 (BC_1, IO87, input, X)," &
" 369 (BC_1, *, internal, X)," &
" 370 (BC_1, *, internal, X)," &
" 371 (BC_1, *, internal, X)," &
" 372 (BC_1, *, controlr, 1)," &
" 373 (BC_1, IO88, output3, X, 372, 1, PULL1)," &
" 374 (BC_1, IO88, input, X)," &
" 375 (BC_1, *, controlr, 1)," &
" 376 (BC_1, IO89, output3, X, 375, 1, PULL1)," &
" 377 (BC_1, IO89, input, X)," &
" 378 (BC_1, *, internal, X)," &
" 379 (BC_1, *, internal, X)," &
" 380 (BC_1, *, internal, X)," &
" 381 (BC_1, *, internal, X)," &
" 382 (BC_1, *, internal, X)," &
" 383 (BC_1, *, internal, X)," &
" 384 (BC_1, *, internal, X)";
--end boundary register
attribute DESIGN_WARNING of XC5202_VQ100 : entity is
"CCLK and DONE are not represented in BOUNDARY_REGISTER." &
"This BSDL file must be modified by the FPGA designer in order to" &
"reflect post-configuration behavior (if any)." &
"If INIT has been high or floating since power-on or the last" &
"rising edge of PROGRAM, then the device may be in" &
"configuration mode in which case this file is not valid." &
"Programmably inverted input paths are controlled with the" &
"wrong polarity." &
"The tristate control is not captured properly when GTS is activated." &
"Some pins have both controlled and uncontrolled input paths.";
end XC5202_VQ100;