BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: ZL81001_CSBGA_256

----------------------------------------------------------------------------------   
--
--   File Name		:	ZL81001_CSBGA_256
--
--   Company		: 	Microsemi Corporation
--   Documentation	:	ZL81001 datasheet
--   BSDL Revision	:	0.1 (preliminary)
--   Date			:	12/16/2020	
--
--   Device	      	:	ZL81001
--   Package	    :	256-pin CSBGA
-- 
--			IMPORTANT NOTICE
-- Microsemi Corporation customers are advised to obtain the latest version of 
-- device specifications before relying on any published information contained 
-- herein. Microsemi Corporation assumes no responsibility or liability arising 
-- out of the application of any information described herein.
--
--			IMPORTANT NOTICE ABOUT THE REVISION
--
-- Microsemi Corporation customers are advised to check the revision of the  
-- device they will be using.  All the codes for the device revisions are 
-- herein this BSDL file.
--
-- The characters "/", "(", ")" and "*" have been removed from signal names for 
-- compatibility with BSDL file format. 
--
-- --------------------------------------------------------------------------------
entity ZL81001_CSBGA_256 is
   
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "CSBGA_256");
   
-- This section declares all the ports in the design.
   port ( 
          A          : inout     bit_vector (0 to 8);
          AD         : inout     bit_vector (0 to 7);
          ALE        : inout     bit;
          AVDD_PLL1  : linkage   bit;
          AVDD_PLL2  : linkage   bit;
          AVDD_PLL3  : linkage   bit;
          AVDD_PLL4  : linkage   bit;
          AVSS_PLL1  : linkage   bit;
          AVSS_PLL2  : linkage   bit;
          AVSS_PLL3  : linkage   bit;
          AVSS_PLL4  : linkage   bit;
          CS         : inout     bit;
          DVDD       : linkage   bit;
          DVSS       : linkage   bit;
          GPIO1      : inout     bit;
          GPIO2      : inout     bit;
          GPIO3      : inout     bit;
          GPIO4      : inout     bit;
          HIZ        : inout     bit;
          IC1        : inout     bit;
          IC10       : inout     bit;
          IC11       : inout     bit;
          IC12       : inout     bit;
          IC13       : inout     bit;
          IC14       : inout     bit;
          IC1A       : linkage   bit;
          IC2        : inout     bit;
          IC2A       : linkage   bit;
          IC3        : inout     bit;
          IC4        : inout     bit;
          IC5NEG     : linkage   bit;
          IC5POS     : linkage   bit;
          IC6NEG     : linkage   bit;
          IC6POS     : linkage   bit;
          IC7        : inout     bit;
          IC8        : inout     bit;
          IC9        : inout     bit;
          IFSEL      : inout     bit_vector (0 to 2);
          INTREQ     : inout     bit;
          JTCLK      : in        bit;
          JTDI       : in        bit;
          JTDO       : out       bit;
          JTMS       : in        bit;
          JTRST_N    : in        bit;
          MASTSLV    : inout     bit;
          MCLK1      : inout     bit;
          MCLK2      : inout     bit;
          OC1        : linkage   bit;
          OC10       : linkage   bit;
          OC11       : linkage   bit;
          OC2        : linkage   bit;
          OC3        : linkage   bit;
          OC4        : linkage   bit;
          OC5        : linkage   bit;
          OC6NEG     : linkage   bit;
          OC6POS     : linkage   bit;
          OC7NEG     : linkage   bit;
          OC7POS     : linkage   bit;
          OC8NEG     : linkage   bit;
          OC8POS     : linkage   bit;
          OC9        : linkage   bit;
          RCLK1      : inout     bit;
          RCLK2      : inout     bit;
          RD         : inout     bit;
          RDY        : inout     bit;
          REFCLK     : inout     bit;
          RESREF     : linkage   bit;
          ROUT1      : inout     bit;
          ROUT2      : inout     bit;
          RRING1     : linkage   bit;
          RRING2     : linkage   bit;
          RSER1      : inout     bit;
          RSER2      : inout     bit;
          RST        : inout     bit;
          RTIP1      : linkage   bit;
          RTIP2      : linkage   bit;
          RVDD_P1    : linkage   bit;
          RVDD_P2    : linkage   bit;
          RVSS_P1    : linkage   bit;
          RVSS_P2    : linkage   bit;
          SONSDH     : inout     bit;
          SRCSW      : inout     bit;
          SRFAIL     : inout     bit;
          SYNC2K     : inout     bit;
          TCLK1      : inout     bit;
          TCLK2      : inout     bit;
          THZE1      : inout     bit;
          THZE2      : inout     bit;
          TIN1       : inout     bit;
          TIN2       : inout     bit;
          TM1        : inout     bit;
          TM2        : inout     bit;
          TOUT1      : inout     bit;
          TOUT2      : inout     bit;
          TRING1     : linkage   bit;
          TRING2     : linkage   bit;
          TSER1      : inout     bit;
          TSER2      : inout     bit;
          TST_RA1    : linkage   bit;
          TST_RA2    : linkage   bit;
          TST_RB1    : linkage   bit;
          TST_RB2    : linkage   bit;
          TST_RC1    : linkage   bit;
          TST_RC2    : linkage   bit;
          TST_TA1    : linkage   bit;
          TST_TA2    : linkage   bit;
          TST_TB1    : linkage   bit;
          TST_TB2    : linkage   bit;
          TST_TC1    : linkage   bit;
          TST_TC2    : linkage   bit;
          TTIP1      : linkage   bit;
          TTIP2      : linkage   bit;
          TVDD_P1    : linkage   bit;
          TVDD_P2    : linkage   bit;
          TVSS_P1    : linkage   bit;
          TVSS_P2    : linkage   bit;
          VDD        : linkage   bit_vector (0 to 23);
          VDDIO      : linkage   bit_vector (0 to 27);
          VDD_ICDIFF : linkage   bit;
          VDD_OC6    : linkage   bit;
          VDD_OC7    : linkage   bit;
          VSS        : linkage   bit_vector (0 to 55);
          VSS_ICDIFF : linkage   bit;
          VSS_OC6    : linkage   bit;
          VSS_OC7    : linkage   bit;
          WDT        : inout     bit;
          WR         : inout     bit
   );
   
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of ZL81001_CSBGA_256: entity is "STD_1149_1_1993";
attribute PIN_MAP of ZL81001_CSBGA_256: entity is PHYSICAL_PIN_MAP;
   
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
  
constant CSBGA_256: PIN_MAP_STRING := 
        "A          :(H16, H15, G16, H14, G15, F16, G14, F15, E16)," &
        "AD         :(E15, D16, C16, D15, C15, E14, D14, C14)," &
        "ALE        : K14," &
        "AVDD_PLL1  : D1," &
        "AVDD_PLL2  : E1," &
        "AVDD_PLL3  : F1," &
        "AVDD_PLL4  : G1," &
        "AVSS_PLL1  : D2," &
        "AVSS_PLL2  : E3," &
        "AVSS_PLL3  : G2," &
        "AVSS_PLL4  : G3," &
        "CS         : J16," &
        "DVDD       : H3," &
        "DVSS       : P8," &
        "GPIO1      : E2," &
        "GPIO2      : F3," &
        "GPIO3      : H2," &
        "GPIO4      : J1," &
        "HIZ        : R14," &
        "IC1        : A10," &
        "IC10       : B12," &
        "IC11       : A13," &
        "IC12       : C12," &
        "IC13       : B13," &
        "IC14       : A14," &
        "IC1A       : P6," &
        "IC2        : B10," &
        "IC2A       : P7," &
        "IC3        : C10," &
        "IC4        : A11," &
        "IC5NEG     : A5," &
        "IC5POS     : B5," &
        "IC6NEG     : A4," &
        "IC6POS     : B4," &
        "IC7        : B11," &
        "IC8        : C11," &
        "IC9        : A12," &
        "IFSEL      :(N1, N2, P1)," &
        "INTREQ     : A15," &
        "JTCLK      : R8," &
        "JTDI       : R9," &
        "JTDO       : P9," &
        "JTMS       : T9," &
        "JTRST_N    : T8," &
        "MASTSLV    : R11," &
        "MCLK1      : F2," &
        "MCLK2      : T10," &
        "OC1        : C6," &
        "OC10       : B9," &
        "OC11       : C9," &
        "OC2        : A7," &
        "OC3        : B7," &
        "OC4        : C7," &
        "OC5        : A8," &
        "OC6NEG     : A3," &
        "OC6POS     : B3," &
        "OC7NEG     : C1," &
        "OC7POS     : C2," &
        "OC8NEG     : B8," &
        "OC8POS     : C8," &
        "OC9        : A9," &
        "RCLK1      : K1," &
        "RCLK2      : R10," &
        "RD         : J14," &
        "RDY        : B15," &
        "REFCLK     : H1," &
        "RESREF     : T7," &
        "ROUT1      : K2," &
        "ROUT2      : P10," &
        "RRING1     : R5," &
        "RRING2     : L15," &
        "RSER1      : J3," &
        "RSER2      : T11," &
        "RST        : B6," &
        "RTIP1      : T5," &
        "RTIP2      : L16," &
        "RVDD_P1    : T4," &
        "RVDD_P2    : M15," &
        "RVSS_P1    : P5," &
        "RVSS_P2    : M14," &
        "SONSDH     : M3," &
        "SRCSW      : M2," &
        "SRFAIL     : J2," &
        "SYNC2K     : B14," &
        "TCLK1      : L2," &
        "TCLK2      : T12," &
        "THZE1      : K3," &
        "THZE2      : T14," &
        "TIN1       : L1," &
        "TIN2       : R12," &
        "TM1        : R13," &
        "TM2        : T15," &
        "TOUT1      : M1," &
        "TOUT2      : P11," &
        "TRING1     : R2," &
        "TRING2     : P15," &
        "TSER1      : L3," &
        "TSER2      : T13," &
        "TST_RA1    : R6," &
        "TST_RA2    : L14," &
        "TST_RB1    : T6," &
        "TST_RB2    : K16," &
        "TST_RC1    : R7," &
        "TST_RC2    : K15," &
        "TST_TA1    : P2," &
        "TST_TA2    : R15," &
        "TST_TB1    : N3," &
        "TST_TB2    : P13," &
        "TST_TC1    : P3," &
        "TST_TC2    : P14," &
        "TTIP1      : R3," &
        "TTIP2      : N15," &
        "TVDD_P1    : R4," &
        "TVDD_P2    : M16," &
        "TVSS_P1    : P4," &
        "TVSS_P2    : N14," &
        "VDD        :(D11, D6, D8, D9, E11, E6, F12, F13, F4, F5, H13, H4, J13, J4, L12, L13, L4, L5, M11, M6, N11, N6, N8, N9)," &
        "VDDIO      :(B1, B16, D10, D7, E10, E7, E8, E9, G12, G13, G4, G5, H12, H5, J12, J5, K12, K13, K4, K5, M10, M7, M8, M9, N10, N7, R1, R16)," &
        "VDD_ICDIFF : A6," &
        "VDD_OC6    : B2," &
        "VDD_OC7    : C3," &
        "VSS        :(A1, A16, D12, D13, D4, D5, E12, E13, E4, E5, F10, F11, F6, F7, F8, F9, G10, G11, G6, G7, G8, G9, H10, H11, H6, H7, H8, H9, J10, J11, J6, J7, J8, J9, K10, K11, K6, K7, K8, K9, L10, L11, L6, L7, L8, L9, M12, M13, M4, M5, N12, N13, N4, N5, T1, T16)," &
        "VSS_ICDIFF : C4," &
        "VSS_OC6    : A2," &
        "VSS_OC7    : D3," &
        "WDT        : C5," &
        "WR         : J15" ;
  
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
--        First Field : Maximum  TCK frequency.
--        Second Field: Allowable states TCK may be stopped in.

attribute TAP_SCAN_CLOCK of JTCLK    : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN    of JTDI     : signal is true;
attribute TAP_SCAN_MODE  of JTMS     : signal is true;
attribute TAP_SCAN_OUT   of JTDO     : signal is true;
attribute TAP_SCAN_RESET of JTRST_N  : signal is true;
   
-- Specifies the number of bits in the instruction register.
   
attribute INSTRUCTION_LENGTH of ZL81001_CSBGA_256: entity is 3;
   
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
   
attribute INSTRUCTION_OPCODE of ZL81001_CSBGA_256: entity is 
     "BYPASS (111)," &
     "EXTEST (000)," &
     "SAMPLE (010)," &
     "CLAMP  (011)," &
     "HIGHZ  (100)," &
     "USER1  (101)," &
     "USER2  (110)," &
     "IDCODE (001)";
   
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
   
attribute INSTRUCTION_CAPTURE of ZL81001_CSBGA_256: entity is "001";
   
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
   
attribute IDCODE_REGISTER of ZL81001_CSBGA_256: entity is 
     "0001" &                  -- 4-bit version number
     "1100000000011100" &      -- 16-bit part number
     "00010100001" &           -- 11-bit identity of the manufacturer
     "1";                      -- Required by IEEE Std 1149.1
   
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
   
attribute REGISTER_ACCESS of ZL81001_CSBGA_256: entity is 
        "BYPASS    (BYPASS, CLAMP, HIGHZ, USER1, USER2)," &
        "BOUNDARY  (EXTEST, SAMPLE)," &
        "DEVICE_ID (IDCODE)";
   
-- Specifies the length of the boundary scan register.
   
attribute BOUNDARY_LENGTH of ZL81001_CSBGA_256: entity is 162;
   
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
--      num     : Is the cell number.
--      cell    : Is the cell type as defined by the standard.
--      port    : Is the design port name. Control cells do not
--                have a port name.
--      function: Is the function of the cell as defined by the
--                standard. Is one of input, output2, output3,
--                bidir, control or controlr.
--      safe    : Specifies the value that the BSR cell should be
--                loaded with for safe operation when the software
--                might otherwise choose a random value.
--      ccell   : The control cell number. Specifies the control
--                cell that drives the output enable for this port.
--      disval  : Specifies the value that is loaded into the
--                control cell to disable the output enable for
--                the corresponding port.
--      rslt    : Resulting state. Shows the state of the driver
--                when it is disabled.
   
attribute BOUNDARY_REGISTER of ZL81001_CSBGA_256: entity is 
--    
--    num   cell   port     function      safe  [ccell  disval  rslt]
--    
  "161   (BC_1,  *,           controlr,     0),                        " &
  "160   (BC_0,  GPIO1,       bidir,        X,   161 ,     0,     Z),  " &
  "159   (BC_1,  *,           controlr,     0),                        " &
  "158   (BC_0,  GPIO2,       bidir,        X,   159 ,     0,     Z),  " &
  "157   (BC_1,  *,           controlr,     0),                        " &
  "156   (BC_0,  MCLK1,       bidir,        X,   157 ,     0,     Z),  " &
  "155   (BC_1,  *,           controlr,     0),                        " &
  "154   (BC_0,  REFCLK,      bidir,        X,   155 ,     0,     Z),  " &
  "153   (BC_1,  *,           controlr,     0),                        " &
  "152   (BC_0,  GPIO3,       bidir,        X,   153 ,     0,     Z),  " &
  "151   (BC_1,  *,           controlr,     0),                        " &
  "150   (BC_0,  GPIO4,       bidir,        X,   151 ,     0,     Z),  " &
  "149   (BC_1,  *,           controlr,     0),                        " &
  "148   (BC_0,  SRFAIL,      bidir,        X,   149 ,     0,     Z),  " &
  "147   (BC_1,  *,           controlr,     0),                        " &
  "146   (BC_0,  RSER1,       bidir,        X,   147 ,     0,     Z),  " &
  "145   (BC_1,  *,           controlr,     0),                        " &
  "144   (BC_0,  RCLK1,       bidir,        X,   145 ,     0,     Z),  " &
  "143   (BC_1,  *,           controlr,     0),                        " &
  "142   (BC_0,  ROUT1,       bidir,        X,   143 ,     0,     Z),  " &
  "141   (BC_1,  *,           controlr,     0),                        " &
  "140   (BC_0,  TIN1,        bidir,        X,   141 ,     0,     Z),  " &
  "139   (BC_1,  *,           controlr,     0),                        " &
  "138   (BC_0,  TSER1,       bidir,        X,   139 ,     0,     Z),  " &
  "137   (BC_1,  *,           controlr,     0),                        " &
  "136   (BC_0,  THZE1,       bidir,        X,   137 ,     0,     Z),  " &
  "135   (BC_1,  *,           controlr,     0),                        " &
  "134   (BC_0,  TCLK1,       bidir,        X,   135 ,     0,     Z),  " &
  "133   (BC_1,  *,           controlr,     0),                        " &
  "132   (BC_0,  TOUT1,       bidir,        X,   133 ,     0,     Z),  " &
  "131   (BC_1,  *,           controlr,     0),                        " &
  "130   (BC_0,  SRCSW,       bidir,        X,   131 ,     0,     Z),  " &
  "129   (BC_1,  *,           controlr,     0),                        " &
  "128   (BC_0,  SONSDH,      bidir,        X,   129 ,     0,     Z),  " &
  "127   (BC_1,  *,           controlr,     0),                        " &
  "126   (BC_0,  IFSEL(0),    bidir,        X,   127 ,     0,     Z),  " &
  "125   (BC_1,  *,           controlr,     0),                        " &
  "124   (BC_0,  IFSEL(1),    bidir,        X,   125 ,     0,     Z),  " &
  "123   (BC_1,  *,           controlr,     0),                        " &
  "122   (BC_0,  IFSEL(2),    bidir,        X,   123 ,     0,     Z),  " &
  "121   (BC_1,  *,           controlr,     0),                        " &
  "120   (BC_0,  MCLK2,       bidir,        X,   121 ,     0,     Z),  " &
  "119   (BC_1,  *,           controlr,     0),                        " &
  "118   (BC_0,  RCLK2,       bidir,        X,   119 ,     0,     Z),  " &
  "117   (BC_1,  *,           controlr,     0),                        " &
  "116   (BC_0,  ROUT2,       bidir,        X,   117 ,     0,     Z),  " &
  "115   (BC_1,  *,           controlr,     0),                        " &
  "114   (BC_0,  RSER2,       bidir,        X,   115 ,     0,     Z),  " &
  "113   (BC_1,  *,           controlr,     0),                        " &
  "112   (BC_0,  MASTSLV,     bidir,        X,   113 ,     0,     Z),  " &
  "111   (BC_1,  *,           controlr,     0),                        " &
  "110   (BC_0,  TCLK2,       bidir,        X,   111 ,     0,     Z),  " &
  "109   (BC_1,  *,           controlr,     0),                        " &
  "108   (BC_0,  TOUT2,       bidir,        X,   109 ,     0,     Z),  " &
  "107   (BC_1,  *,           controlr,     0),                        " &
  "106   (BC_0,  TIN2,        bidir,        X,   107 ,     0,     Z),  " &
  "105   (BC_1,  *,           controlr,     0),                        " &
  "104   (BC_0,  TSER2,       bidir,        X,   105 ,     0,     Z),  " &
  "103   (BC_1,  *,           controlr,     0),                        " &
  "102   (BC_0,  THZE2,       bidir,        X,   103 ,     0,     Z),  " &
  "101   (BC_1,  *,           controlr,     0),                        " &
  "100   (BC_0,  TM1,         bidir,        X,   101 ,     0,     Z),  " &
  "99    (BC_1,  *,           controlr,     0),                        " &
  "98    (BC_0,  TM2,         bidir,        X,   99  ,     0,     Z),  " &
  "97    (BC_1,  *,           controlr,     0),                        " &
  "96    (BC_0,  HIZ,         bidir,        X,   97  ,     0,     Z),  " &
  "95    (BC_1,  *,           controlr,     0),                        " &
  "94    (BC_0,  ALE,         bidir,        X,   95  ,     0,     Z),  " &
  "93    (BC_1,  *,           controlr,     0),                        " &
  "92    (BC_0,  CS,          bidir,        X,   93  ,     0,     Z),  " &
  "91    (BC_1,  *,           controlr,     0),                        " &
  "90    (BC_0,  WR,          bidir,        X,   91  ,     0,     Z),  " &
  "89    (BC_1,  *,           controlr,     0),                        " &
  "88    (BC_0,  RD,          bidir,        X,   89  ,     0,     Z),  " &
  "87    (BC_1,  *,           controlr,     0),                        " &
  "86    (BC_0,  A(0),        bidir,        X,   87  ,     0,     Z),  " &
  "85    (BC_1,  *,           controlr,     0),                        " &
  "84    (BC_0,  A(1),        bidir,        X,   85  ,     0,     Z),  " &
  "83    (BC_1,  *,           controlr,     0),                        " &
  "82    (BC_0,  A(2),        bidir,        X,   83  ,     0,     Z),  " &
  "81    (BC_1,  *,           controlr,     0),                        " &
  "80    (BC_0,  A(3),        bidir,        X,   81  ,     0,     Z),  " &
  "79    (BC_1,  *,           controlr,     0),                        " &
  "78    (BC_0,  A(4),        bidir,        X,   79  ,     0,     Z),  " &
  "77    (BC_1,  *,           controlr,     0),                        " &
  "76    (BC_0,  A(5),        bidir,        X,   77  ,     0,     Z),  " &
  "75    (BC_1,  *,           controlr,     0),                        " &
  "74    (BC_0,  A(6),        bidir,        X,   75  ,     0,     Z),  " &
  "73    (BC_1,  *,           controlr,     0),                        " &
  "72    (BC_0,  A(7),        bidir,        X,   73  ,     0,     Z),  " &
  "71    (BC_1,  *,           controlr,     0),                        " &
  "70    (BC_0,  A(8),        bidir,        X,   71  ,     0,     Z),  " &
  "69    (BC_1,  *,           controlr,     0),                        " &
  "68    (BC_0,  AD(0),       bidir,        X,   69  ,     0,     Z),  " &
  "67    (BC_1,  *,           controlr,     0),                        " &
  "66    (BC_0,  AD(1),       bidir,        X,   67  ,     0,     Z),  " &
  "65    (BC_1,  *,           controlr,     0),                        " &
  "64    (BC_0,  AD(2),       bidir,        X,   65  ,     0,     Z),  " &
  "63    (BC_1,  *,           controlr,     0),                        " &
  "62    (BC_0,  AD(3),       bidir,        X,   63  ,     0,     Z),  " &
  "61    (BC_1,  *,           controlr,     0),                        " &
  "60    (BC_0,  AD(4),       bidir,        X,   61  ,     0,     Z),  " &
  "59    (BC_1,  *,           controlr,     0),                        " &
  "58    (BC_0,  AD(5),       bidir,        X,   59  ,     0,     Z),  " &
  "57    (BC_1,  *,           controlr,     0),                        " &
  "56    (BC_0,  AD(6),       bidir,        X,   57  ,     0,     Z),  " &
  "55    (BC_1,  *,           controlr,     0),                        " &
  "54    (BC_0,  AD(7),       bidir,        X,   55  ,     0,     Z),  " &
  "53    (BC_1,  *,           controlr,     0),                        " &
  "52    (BC_0,  RDY,         bidir,        X,   53  ,     0,     Z),  " &
  "51    (BC_1,  *,           controlr,     0),                        " &
  "50    (BC_0,  INTREQ,      bidir,        X,   51  ,     0,     Z),  " &
  "49    (BC_1,  *,           controlr,     0),                        " &
  "48    (BC_0,  SYNC2K,      bidir,        X,   49  ,     0,     Z),  " &
  "47    (BC_1,  *,           controlr,     0),                        " &
  "46    (BC_0,  IC14,        bidir,        X,   47  ,     0,     Z),  " &
  "45    (BC_1,  *,           controlr,     0),                        " &
  "44    (BC_0,  IC13,        bidir,        X,   45  ,     0,     Z),  " &
  "43    (BC_1,  *,           controlr,     0),                        " &
  "42    (BC_0,  IC12,        bidir,        X,   43  ,     0,     Z),  " &
  "41    (BC_1,  *,           controlr,     0),                        " &
  "40    (BC_0,  IC11,        bidir,        X,   41  ,     0,     Z),  " &
  "39    (BC_1,  *,           controlr,     0),                        " &
  "38    (BC_0,  IC10,        bidir,        X,   39  ,     0,     Z),  " &
  "37    (BC_1,  *,           controlr,     0),                        " &
  "36    (BC_0,  IC9,         bidir,        X,   37  ,     0,     Z),  " &
  "35    (BC_1,  *,           controlr,     0),                        " &
  "34    (BC_0,  IC8,         bidir,        X,   35  ,     0,     Z),  " &
  "33    (BC_1,  *,           controlr,     0),                        " &
  "32    (BC_0,  IC7,         bidir,        X,   33  ,     0,     Z),  " &
  "31    (BC_1,  *,           controlr,     0),                        " &
  "30    (BC_0,  IC4,         bidir,        X,   31  ,     0,     Z),  " &
  "29    (BC_1,  *,           controlr,     0),                        " &
  "28    (BC_0,  IC3,         bidir,        X,   29  ,     0,     Z),  " &
  "27    (BC_1,  *,           controlr,     0),                        " &
  "26    (BC_0,  IC2,         bidir,        X,   27  ,     0,     Z),  " &
  "25    (BC_1,  *,           controlr,     0),                        " &
  "24    (BC_0,  IC1,         bidir,        X,   25  ,     0,     Z),  " &
  "23    (BC_0,  *,           internal,     X),                        " &
  "22    (BC_0,  *,           internal,     X),                        " &
  "21    (BC_0,  *,           internal,     X),                        " &
  "20    (BC_0,  *,           internal,     X),                        " &
  "19    (BC_0,  *,           internal,     X),                        " &
  "18    (BC_0,  *,           internal,     X),                        " &
  "17    (BC_0,  *,           internal,     X),                        " &
  "16    (BC_0,  *,           internal,     X),                        " &
  "15    (BC_0,  *,           internal,     X),                        " &
  "14    (BC_0,  *,           internal,     X),                        " &
  "13    (BC_0,  *,           internal,     X),                        " &
  "12    (BC_0,  *,           internal,     X),                        " &
  "11    (BC_0,  *,           internal,     X),                        " &
  "10    (BC_0,  *,           internal,     X),                        " &
  "9     (BC_0,  *,           internal,     X),                        " &
  "8     (BC_0,  *,           internal,     X),                        " &
  "7     (BC_0,  *,           internal,     X),                        " &
  "6     (BC_0,  *,           internal,     X),                        " &
  "5     (BC_0,  *,           internal,     X),                        " &
  "4     (BC_0,  *,           internal,     X),                        " &
  "3     (BC_0,  *,           controlr,     0),                        " &
  "2     (BC_0,  RST,         bidir,        X,   3   ,     0,     Z),  " &
  "1     (BC_0,  *,           controlr,     0),                        " &
  "0     (BC_0,  WDT,         bidir,        X,   1   ,     0,     Z)   " ;

end ZL81001_CSBGA_256;