-- Copyright (C) 1998-2005 Altera Corporation
-- File Name : 740L68.BSD
-- Device : EPX740L68
-- Package : 68 Pin J-lead Chip Carrier (PLCC)
-- Created by : Altera Corporation
-- BSDL revision : 1.33
-- BSDL Status : Final
-- Revision : 1.0, 03/21/94
-- History : 1.31, 8/15/98
-- Updated info from Intel to Altera
-- 1.32, 10/18/99
-- Updated to 1994 spec
-- : 1.33, 8/23/02
-- Changed file status to Final
-- Verification : Software syntax checked on:
-- ASSET Tool Box ver. 2.3d
-- Genrad BSDL syntax checker ver. 4.01, a component
-- of Scan Pathfinder(tm) and BasicSCAN(tm)
-- HP 3070 BSDL Compiler
-- JTAG Technologies PLDPROG ver. 2.7
-- Documentation : FLASHlogic Family Datasheet
-- Note: This device is obsolete
-- AN39 - JTAG Boundary Scan for Altera Devices
-- AB51 - Overview of In-Circuit Recoguration and
-- Programming for the FLASHlogic EPX780 and EPX740
--
--
-- IMPORTANT NOTICE
--
-- Altera and EPX740 are trademarks of Altera Corporation.
-- Altera products, marketed under trademarks are protected
-- under numerous US and foreign patents and pending
-- applications, maskwork rights, and copyrights. Altera
-- warrants performance of its semiconductor products to
-- current specifications in accordance with Altera's standard
-- warranty, but reserves the right to make changes to any
-- products and services at any time without notice. Altera
-- assumes no responsibility or liability arising out of the
-- application or use of any information, product, or service
-- described herein except as expressly agreed to in writing
-- by Altera Corporation. Altera customers are advised to
-- obtain the latest version of device specifications before
-- relying on any published information and before placing
-- orders for products or services.
entity EPX740L68 is
generic (PHYSICAL_PIN_MAP : string := "PLCC68");
port (
CLK1 : in bit;
CLK2 : in bit;
INP : in bit_vector(0 to 9); -- inputs
IO : inout bit_vector(0 to 39); -- I/O pins
TCK, TMS, TDI : in bit; -- Scan Port inputs
TDO : out bit; -- Scan Port output
VCC : linkage bit ; -- VCC
VCCO : linkage bit_vector(0 to 3); -- VCC
VSS : linkage bit_vector(1 to 6); -- GND pins
VPP : linkage bit -- VPP pin
); -- end of ports
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of EPX740L68 : entity is "STD_1149_1_1993";
attribute PIN_MAP of EPX740L68 : entity is PHYSICAL_PIN_MAP;
constant PLCC68 : PIN_MAP_STRING := -- Define Pin Out of QFP
-- I/O pins
"IO:(22, 23, 24, 25, 26, 27, 28, 29, 30, 31," &
"14, 13, 12, 11, 10, 9, 8, 7, 6, 5," &
"48, 47, 46, 45, 44, 43, 42, 41, 40, 39," &
"56, 57, 58, 59, 60, 61, 62, 63, 64, 65), " &
-- Dedicated Clocks
"CLK1:19, CLK2:53," &
-- Power pins
"VSS:(1, 21, 34, 54, 55, 68)," & -- GND
"VCC:35, VPP:20," &
"VCCO:(18,17,51,52), " &
-- TAP controller pins
"TCK:66, TMS:67, TDI:33, TDO:32," &
-- Dedicated Inputs
"INP:(16,15,4,3,2,50,49,38,37,36)";
attribute Tap_Scan_In of TDI : signal is true;
attribute Tap_Scan_Mode of TMS : signal is true;
attribute Tap_Scan_Out of TDO : signal is true;
attribute Tap_Scan_Clock of TCK : signal is (8.0e6, BOTH);
attribute Instruction_Length of EPX740L68: entity is 5;
attribute Instruction_Opcode of EPX740L68: entity is
"BYPASS (11111)," &
"EXTEST (00000)," &
"SAMPLE (00001)," &
"IDCODE (00010)," &
"LDVECT (00101)," &
"FREAD (00110)," &
"SWRITE (01111)," &
"SREAD (10000)," &
"FPGM (10101)," &
"UESCODE (10110)," &
"RADLOAD (11000)," &
"ISCAN (11110)," &
"TRIBYP (11101)," & -- Boundary Hi-Z
"PRIVATE (00011,00100,00111,01000,01001,01010,01011,01100,01101,"&
"01110,10001,10010,10011,10100,"&
"10111,11001,11010,11011,11100)";
attribute Instruction_Capture of EPX740L68: entity is "00001";
-- there is no Instruction_Disable attribute for EPX740L68
attribute Instruction_Private of EPX740L68: entity is "private";
attribute Idcode_Register of EPX740L68: entity is
"0000" & --version
"0000011000100010" & --part number
"00000001001" & --manufacturers identity, 9h for Intel
"1"; --required by the standard
attribute Register_Access of EPX740L68: entity is
"BYPASS (BYPASS, TRIBYP)," & -- 1149.1 bypass
-- High-Z Bypass
"BOUNDARY (EXTEST, SAMPLE)," & -- 1149.1 extest & sample
"EPROM_VECTOR[43] (LDVECT)," & -- semi-private eprom prog.
"ROW_VECTOR[606] (FREAD, SWRITE, SREAD)," &
-- semi-private eprom read
-- semi-private sram write
-- semi-private sram read
"VERIFY[1](FPGM)," & -- semi-private eprom verify
"UES_CODE[300] (UESCODE)," & -- semi-private user code
"ADDR[6] (RADLOAD)," & -- semi-private address load
"REGISTER_SCAN[40] (ISCAN)"; -- semi-private all mcells
--{*******************************************************************}
-- ISCAN CHAIN-The ISCAN chain scans out the device macrocell registers
-- in the order given below. It goes from Macrocell 9 to 0 in each CFB,
-- and from CFB 0 to CFB 3. See the appropriate application notes and
-- datasheet restrictions on how to use this instruction.
-- TDI -> IO9,IO8,IO7,IO6,IO5,IO4,IO3,IO2,IO1,IO0, IO19,...IO30 -> TDO
--{*******************************************************************}
attribute Boundary_Length of EPX740L68: entity is 132;
attribute Boundary_Register of EPX740L68: entity is
--num cell port function safe ccell dsval rslt
" 0 (BC_1, *, CONTROLR, 0)," & -- IO09.OE
" 1 (BC_1, IO(9), output3, X, 0, 0, Z)," & -- IO09.OUT
" 2 (BC_1, IO(9), input, X)," & -- IO09.IN
" 3 (BC_1, *, CONTROLR, 0)," & -- IO08
" 4 (BC_1, IO(8), output3, X, 3, 0, Z)," &
" 5 (BC_1, IO(8), input, X)," &
" 6 (BC_1, *, CONTROLR, 0)," & -- IO07
" 7 (BC_1, IO(7), output3, X, 6, 0, Z)," &
" 8 (BC_1, IO(7), input, X)," &
" 9 (BC_1, *, CONTROLR, 0)," & -- IO06
" 10 (BC_1, IO(6), output3, X, 9, 0, Z)," &
" 11 (BC_1, IO(6), input, X)," &
" 12 (BC_1, *, CONTROLR, 0)," & -- IO05
" 13 (BC_1, IO(5), output3, X, 12, 0, Z)," &
" 14 (BC_1, IO(5), input, X)," &
" 15 (BC_1, *, CONTROLR, 0)," & -- IO04
" 16 (BC_1, IO(4), output3, X, 15, 0, Z)," &
" 17 (BC_1, IO(4), input, X)," &
" 18 (BC_1, *, CONTROLR, 0)," & -- IO03
" 19 (BC_1, IO(3), output3, X, 18, 0, Z)," &
" 20 (BC_1, IO(3), input, X)," &
" 21 (BC_1, *, CONTROLR, 0)," & -- IO02
" 22 (BC_1, IO(2), output3, X, 21, 0, Z)," &
" 23 (BC_1, IO(2), input, X)," &
" 24 (BC_1, *, CONTROLR, 0)," & -- IO01
" 25 (BC_1, IO(1), output3, X, 24, 0, Z)," &
" 26 (BC_1, IO(1), input, X)," &
" 27 (BC_1, *, CONTROLR, 0)," & -- IO00
" 28 (BC_1, IO(0), output3, X, 27, 0, Z)," &
" 29 (BC_1, IO(0), input, X)," &
" 30 (BC_4, CLK1, INPUT, X)," & -- CLK1
" 31 (BC_4, INP(0), INPUT, X)," & -- IN0
" 32 (BC_4, INP(1), INPUT, X)," & -- IN1
" 33 (BC_1, *, CONTROLR, 0)," & -- IO10
" 34 (BC_1, IO(10), output3, X, 33, 0, Z)," &
" 35 (BC_1, IO(10), input, X)," &
" 36 (BC_1, *, CONTROLR, 0)," & -- IO11
" 37 (BC_1, IO(11), output3, X, 36, 0, Z)," &
" 38 (BC_1, IO(11), input, X)," &
" 39 (BC_1, *, CONTROLR, 0)," & -- IO12
" 40 (BC_1, IO(12), output3, X, 39, 0, Z)," &
" 41 (BC_1, IO(12), input, X)," &
" 42 (BC_1, *, CONTROLR, 0)," & -- IO13
" 43 (BC_1, IO(13), output3, X, 42, 0, Z)," &
" 44 (BC_1, IO(13), input, X)," &
" 45 (BC_1, *, CONTROLR, 0)," & -- IO14
" 46 (BC_1, IO(14), output3, X, 45, 0, Z)," &
" 47 (BC_1, IO(14), input, X)," &
" 48 (BC_1, *, CONTROLR, 0)," & -- IO15
" 49 (BC_1, IO(15), output3, X, 48, 0, Z)," &
" 50 (BC_1, IO(15), input, X)," &
" 51 (BC_1, *, CONTROLR, 0)," & -- IO16
" 52 (BC_1, IO(16), output3, X, 51, 0, Z)," &
" 53 (BC_1, IO(16), input, X)," &
" 54 (BC_1, *, CONTROLR, 0)," & -- IO17
" 55 (BC_1, IO(17), output3, X, 54, 0, Z)," &
" 56 (BC_1, IO(17), input, X)," &
" 57 (BC_1, *, CONTROLR, 0)," & -- IO18
" 58 (BC_1, IO(18), output3, X, 57, 0, Z)," &
" 59 (BC_1, IO(18), input, X)," &
" 60 (BC_1, *, CONTROLR, 0)," & -- IO19
" 61 (BC_1, IO(19), output3, X, 60, 0, Z)," &
" 62 (BC_1, IO(19), input, X)," &
" 63 (BC_4, INP(2), INPUT, X)," & -- IN2
" 64 (BC_4, INP(3), INPUT, X)," & -- IN3
" 65 (BC_4, INP(4), INPUT, X)," & -- IN4
" 66 (BC_1, *, CONTROLR, 0)," & -- IO39
" 67 (BC_1, IO(39), output3, X, 66, 0, Z)," &
" 68 (BC_1, IO(39), input, X)," &
" 69 (BC_1, *, CONTROLR, 0)," & -- IO38
" 70 (BC_1, IO(38), output3, X, 69, 0, Z)," &
" 71 (BC_1, IO(38), input, X)," &
" 72 (BC_1, *, CONTROLR, 0)," & -- IO37
" 73 (BC_1, IO(37), output3, X, 72, 0, Z)," &
" 74 (BC_1, IO(37), input, X)," &
" 75 (BC_1, *, CONTROLR, 0)," & -- IO36
" 76 (BC_1, IO(36), output3, X, 75, 0, Z)," &
" 77 (BC_1, IO(36), input, X)," &
" 78 (BC_1, *, CONTROLR, 0)," & -- IO35
" 79 (BC_1, IO(35), output3, X, 78, 0, Z)," &
" 80 (BC_1, IO(35), input, X)," &
" 81 (BC_1, *, CONTROLR, 0)," & -- IO34
" 82 (BC_1, IO(34), output3, X, 81, 0, Z)," &
" 83 (BC_1, IO(34), input, X)," &
" 84 (BC_1, *, CONTROLR, 0)," & -- IO33
" 85 (BC_1, IO(33), output3, X, 84, 0, Z)," &
" 86 (BC_1, IO(33), input, X)," &
" 87 (BC_1, *, CONTROLR, 0)," & -- IO32
" 88 (BC_1, IO(32), output3, X, 87, 0, Z)," &
" 89 (BC_1, IO(32), input, X)," &
" 90 (BC_1, *, CONTROLR, 0)," & -- IO31
" 91 (BC_1, IO(31), output3, X, 90, 0, Z)," &
" 92 (BC_1, IO(31), input, X)," &
" 93 (BC_1, *, CONTROLR, 0)," & -- IO30
" 94 (BC_1, IO(30), output3, X, 93, 0, Z)," &
" 95 (BC_1, IO(30), input, X)," &
" 96 (BC_4, CLK2, INPUT, X)," & -- CLK2
" 97 (BC_4, INP(5), INPUT, X)," & -- IN5
" 98 (BC_4, INP(6), INPUT, X)," & -- IN6
" 99 (BC_1, *, CONTROLR, 0)," & -- IO20
"100 (BC_1, IO(20), output3, X, 99, 0, Z)," &
"101 (BC_1, IO(20), input, X)," &
"102 (BC_1, *, CONTROLR, 0)," & -- IO21
"103 (BC_1, IO(21), output3, X, 102, 0, Z)," &
"104 (BC_1, IO(21), input, X)," &
"105 (BC_1, *, CONTROLR, 0)," & -- IO22
"106 (BC_1, IO(22), output3, X, 105, 0, Z)," &
"107 (BC_1, IO(22), input, X)," &
"108 (BC_1, *, CONTROLR, 0)," & -- IO23
"109 (BC_1, IO(23), output3, X, 108, 0, Z)," &
"110 (BC_1, IO(23), input, X)," &
"111 (BC_1, *, CONTROLR, 0)," & -- IO24
"112 (BC_1, IO(24), output3, X, 111, 0, Z)," &
"113 (BC_1, IO(24), input, X)," &
"114 (BC_1, *, CONTROLR, 0)," & -- IO25
"115 (BC_1, IO(25), output3, X, 114, 0, Z)," &
"116 (BC_1, IO(25), input, X)," &
"117 (BC_1, *, CONTROLR, 0)," & -- IO26
"118 (BC_1, IO(26), output3, X, 117, 0, Z)," &
"119 (BC_1, IO(26), input, X)," &
"120 (BC_1, *, CONTROLR, 0)," & -- IO27
"121 (BC_1, IO(27), output3, X, 120, 0, Z)," &
"122 (BC_1, IO(27), input, X)," &
"123 (BC_1, *, CONTROLR, 0)," & -- IO28
"124 (BC_1, IO(28), output3, X, 123, 0, Z)," &
"125 (BC_1, IO(28), input, X)," &
"126 (BC_1, *, CONTROLR, 0)," & -- IO29
"127 (BC_1, IO(29), output3, X, 126, 0, Z)," &
"128 (BC_1, IO(29), input, X)," &
"129 (BC_4, INP(7), INPUT, X)," & -- IN7
"130 (BC_4, INP(8), INPUT, X)," & -- IN8
"131 (BC_4, INP(9), INPUT, X)" ; -- IN9
end EPX740L68;
