-- Generated by boundaryScanGenerate 2015.3 Mon Aug 24 21:10:32 GMT 2015 on 01/19/17 14:33:05
-- BSDL Version 2001
entity asic_top is
generic (PHYSICAL_PIN_MAP : string := "DEFAULT_PACKAGE_NAME");
port (
-- Port List
OSCI : linkage bit;
OSCO : linkage bit;
OSCVDD12 : linkage bit;
OSCVSS : linkage bit;
VDD33 : linkage bit;
VDDCR : linkage bit_vector(1 to 3);
REG_EN : linkage bit;
FXLOSEN : linkage bit;
FXSDA_FXSENA : linkage bit;
FXSDB_FXSENB : linkage bit;
NRST : in bit;
AD2_SIO2 : inout bit;
AD1_SIO1 : inout bit;
VDDIO : linkage bit_vector(1 to 5);
AD14_GP8_TXD3 : inout bit;
AD13_GP7_TXD2 : inout bit;
AD0_WD_STATE : inout bit;
SYNC_LATCH1 : inout bit;
AD9_LATCH_IN : inout bit;
AD12_GP6_TXD1 : inout bit;
AD11_GP5_TXD0 : inout bit;
AD10_GP4_TXEN : inout bit;
A1_ALELO_OE_EXT : inout bit;
A3_DIGIO11_GP11 : inout bit;
A4_DIGIO12_GP12 : inout bit;
CS_DIGIO13_GP13 : inout bit;
A2_ALEHI_DIGIO10 : inout bit;
WR_EN_DIGIO14 : inout bit;
RD_WR_DIGIO15 : inout bit;
AD15_GP9_RXER : inout bit;
SYNC_LATCH0 : inout bit;
AD3_SIO3 : inout bit;
AD6_GP0_RXCLK : inout bit;
AD7_MDC : inout bit;
AD8_MDIO : inout bit;
TESTMODE : in bit;
I2CSDA_EESDA_TMS : in bit;
I2CSC_EESCL_TCK : in bit;
IRQ : inout bit;
GP2_LED2_E2P_SZ : inout bit;
LED_GP_TDI_GT_1 : in bit;
LED_GP_TD0_GT_0 : out bit;
AD4_GP3_LNK : inout bit;
AD5_OUT_VALID : inout bit;
VDD33TXRX1 : linkage bit;
TXNA : linkage bit;
TXPA : linkage bit;
RXNA : linkage bit;
RXPA : linkage bit;
VDD12TX1 : linkage bit;
RBIAS : linkage bit;
VDD33BIAS : linkage bit;
VDD12TX2 : linkage bit;
RXPB : linkage bit;
RXNB : linkage bit;
TXPB : linkage bit;
TXNB : linkage bit;
VDD33TXRX2 : linkage bit);
use STD_1149_1_2001.all;
use LVS_BSCAN_CELLS.all;
attribute COMPONENT_CONFORMANCE of asic_top: entity is "STD_1149_1_2001";
--Pin mappings
attribute PIN_MAP of asic_top: entity is PHYSICAL_PIN_MAP;
constant DEFAULT_PACKAGE_NAME: PIN_MAP_STRING :=
"OSCI : 1 , " &
"OSCO : 2 , " &
"OSCVDD12 : 3 , " &
"OSCVSS : 4 , " &
"VDD33 : 5 , " &
"VDDCR : (6,24,38) , " &
"REG_EN : 7 , " &
"FXLOSEN : 8 , " &
"FXSDA_FXSENA : 9 , " &
"FXSDB_FXSENB : 10 , " &
"NRST : 11 , " &
"AD2_SIO2 : 12 , " &
"AD1_SIO1 : 13 , " &
"VDDIO : (14,20,32,37,47), " &
"AD14_GP8_TXD3 : 15 , " &
"AD13_GP7_TXD2 : 16 , " &
"AD0_WD_STATE : 17 , " &
"SYNC_LATCH1 : 18 , " &
"AD9_LATCH_IN : 19 , " &
"AD12_GP6_TXD1 : 21 , " &
"AD11_GP5_TXD0 : 22 , " &
"AD10_GP4_TXEN : 23 , " &
"A1_ALELO_OE_EXT : 25 , " &
"A3_DIGIO11_GP11 : 26 , " &
"A4_DIGIO12_GP12 : 27 , " &
"CS_DIGIO13_GP13 : 28 , " &
"A2_ALEHI_DIGIO10 : 29 , " &
"WR_EN_DIGIO14 : 30 , " &
"RD_WR_DIGIO15 : 31 , " &
"AD15_GP9_RXER : 33 , " &
"SYNC_LATCH0 : 34 , " &
"AD3_SIO3 : 35 , " &
"AD6_GP0_RXCLK : 36 , " &
"AD7_MDC : 39 , " &
"AD8_MDIO : 40 , " &
"TESTMODE : 41 , " &
"I2CSDA_EESDA_TMS : 42 , " &
"I2CSC_EESCL_TCK : 43 , " &
"IRQ : 44 , " &
"GP2_LED2_E2P_SZ : 45 , " &
"LED_GP_TDI_GT_1 : 46 , " &
"LED_GP_TD0_GT_0 : 48 , " &
"AD4_GP3_LNK : 49 , " &
"AD5_OUT_VALID : 50 , " &
"VDD33TXRX1 : 51 , " &
"TXNA : 52 , " &
"TXPA : 53 , " &
"RXNA : 54 , " &
"RXPA : 55 , " &
"VDD12TX1 : 56 , " &
"RBIAS : 57 , " &
"VDD33BIAS : 58 , " &
"VDD12TX2 : 59 , " &
"RXPB : 60 , " &
"RXNB : 61 , " &
"TXPB : 62 , " &
"TXNB : 63 , " &
"VDD33TXRX2 : 64 ";
attribute TAP_SCAN_RESET of NRST : signal is true;
attribute TAP_SCAN_IN of LED_GP_TDI_GT_1 : signal is true;
attribute TAP_SCAN_MODE of I2CSDA_EESDA_TMS : signal is true;
attribute TAP_SCAN_OUT of LED_GP_TD0_GT_0 : signal is true;
attribute TAP_SCAN_CLOCK of I2CSC_EESCL_TCK : signal is (1.0000000000000000000e+08, BOTH);
attribute INSTRUCTION_LENGTH of asic_top: entity is 35;
attribute INSTRUCTION_OPCODE of asic_top: entity is
"IDCODE (11111111111111111111111111111111110)," &
"BYPASS (11111111111111111111111111111111111)," &
"EXTEST (11111111111111111111111111111101000)," &
"SAMPLE (11111111111111111111111111111111000)," &
"PRELOAD (11111111111111111111111111111111000)," &
"HIGHZ (11111111111111111111111111111001111)," &
"CLAMP (11111111111111111111111111111101111) " ;
attribute INSTRUCTION_CAPTURE of asic_top: entity is "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01";
attribute IDCODE_REGISTER of asic_top: entity is
"0010" & -- version
"0000000100000001" & -- part number
"01000100010" & -- manufacturer's identity
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of asic_top: entity is
"DEVICE_ID ( IDCODE ), " &
"BOUNDARY ( SAMPLE, PRELOAD, EXTEST )," &
"BYPASS ( HIGHZ, CLAMP, BYPASS ) " ;
--Boundary scan definition
attribute BOUNDARY_LENGTH of asic_top: entity is 90;
attribute BOUNDARY_REGISTER of asic_top: entity is
-- num cell port function safe [ccell disval rslt]
" 89 (BC_4 , TESTMODE , observe_only , X ) ,"&
" 88 (BC_0 , * , internal , X ) ,"&
" 87 (BC_0 , * , internal , X ) ,"&
" 86 (BC_0 , * , internal , X ) ,"&
" 85 (BC_0 , * , internal , 1 ) ,"&
" 84 (BC_0 , * , internal , X ) ,"&
" 83 (BC_0 , * , internal , 1 ) ,"&
" 82 (BC_0 , * , internal , X ) ,"&
" 81 (BC_2 , * , control , 1 ) ,"&
" 80 (LV_BC_7 , AD2_SIO2 , bidir , X , 81 , 1 , Z ),"&
" 79 (BC_2 , * , control , 1 ) ,"&
" 78 (LV_BC_7 , AD1_SIO1 , bidir , X , 79 , 1 , Z ),"&
" 77 (BC_0 , * , internal , 1 ) ,"&
" 76 (BC_0 , * , internal , X ) ,"&
" 75 (BC_0 , * , internal , 1 ) ,"&
" 74 (BC_0 , * , internal , X ) ,"&
" 73 (BC_2 , * , control , 1 ) ,"&
" 72 (LV_BC_7 , AD14_GP8_TXD3 , bidir , X , 73 , 1 , Z ),"&
" 71 (BC_2 , * , control , 1 ) ,"&
" 70 (LV_BC_7 , AD13_GP7_TXD2 , bidir , X , 71 , 1 , Z ),"&
" 69 (BC_2 , * , control , 1 ) ,"&
" 68 (LV_BC_7 , AD0_WD_STATE , bidir , X , 69 , 1 , Z ),"&
" 67 (BC_2 , * , control , 1 ) ,"&
" 66 (LV_BC_7 , SYNC_LATCH1 , bidir , X , 67 , 1 , Z ),"&
" 65 (BC_0 , * , internal , 1 ) ,"&
" 64 (BC_0 , * , internal , X ) ,"&
" 63 (BC_0 , * , internal , 1 ) ,"&
" 62 (BC_0 , * , internal , X ) ,"&
" 61 (BC_0 , * , internal , 1 ) ,"&
" 60 (BC_0 , * , internal , X ) ,"&
" 59 (BC_2 , * , control , 1 ) ,"&
" 58 (LV_BC_7 , AD9_LATCH_IN , bidir , X , 59 , 1 , Z ),"&
" 57 (BC_2 , * , control , 1 ) ,"&
" 56 (LV_BC_7 , AD12_GP6_TXD1 , bidir , X , 57 , 1 , Z ),"&
" 55 (BC_2 , * , control , 1 ) ,"&
" 54 (LV_BC_7 , AD11_GP5_TXD0 , bidir , X , 55 , 1 , Z ),"&
" 53 (BC_2 , * , control , 1 ) ,"&
" 52 (LV_BC_7 , AD10_GP4_TXEN , bidir , X , 53 , 1 , Z ),"&
" 51 (BC_2 , * , control , 1 ) ,"&
" 50 (LV_BC_7 , A1_ALELO_OE_EXT , bidir , X , 51 , 1 , Z ),"&
" 49 (BC_2 , * , control , 1 ) ,"&
" 48 (LV_BC_7 , A3_DIGIO11_GP11 , bidir , X , 49 , 1 , Z ),"&
" 47 (BC_2 , * , control , 1 ) ,"&
" 46 (LV_BC_7 , A4_DIGIO12_GP12 , bidir , X , 47 , 1 , Z ),"&
" 45 (BC_2 , * , control , 1 ) ,"&
" 44 (LV_BC_7 , CS_DIGIO13_GP13 , bidir , X , 45 , 1 , Z ),"&
" 43 (BC_2 , * , control , 1 ) ,"&
" 42 (LV_BC_7 , A2_ALEHI_DIGIO10 , bidir , X , 43 , 1 , Z ),"&
" 41 (BC_2 , * , control , 1 ) ,"&
" 40 (LV_BC_7 , WR_EN_DIGIO14 , bidir , X , 41 , 1 , Z ),"&
" 39 (BC_2 , * , control , 1 ) ,"&
" 38 (LV_BC_7 , RD_WR_DIGIO15 , bidir , X , 39 , 1 , Z ),"&
" 37 (BC_0 , * , internal , 1 ) ,"&
" 36 (BC_0 , * , internal , X ) ,"&
" 35 (BC_2 , * , control , 1 ) ,"&
" 34 (LV_BC_7 , AD15_GP9_RXER , bidir , X , 35 , 1 , Z ),"&
" 33 (BC_0 , * , internal , 1 ) ,"&
" 32 (BC_0 , * , internal , X ) ,"&
" 31 (BC_2 , * , control , 1 ) ,"&
" 30 (LV_BC_7 , SYNC_LATCH0 , bidir , X , 31 , 1 , Z ),"&
" 29 (BC_0 , * , internal , 1 ) ,"&
" 28 (BC_0 , * , internal , X ) ,"&
" 27 (BC_0 , * , internal , 1 ) ,"&
" 26 (BC_0 , * , internal , X ) ,"&
" 25 (BC_0 , * , internal , 1 ) ,"&
" 24 (BC_0 , * , internal , X ) ,"&
" 23 (BC_0 , * , internal , 1 ) ,"&
" 22 (BC_0 , * , internal , X ) ,"&
" 21 (BC_2 , * , control , 1 ) ,"&
" 20 (LV_BC_7 , AD3_SIO3 , bidir , X , 21 , 1 , Z ),"&
" 19 (BC_2 , * , control , 1 ) ,"&
" 18 (LV_BC_7 , AD6_GP0_RXCLK , bidir , X , 19 , 1 , Z ),"&
" 17 (BC_2 , * , control , 1 ) ,"&
" 16 (LV_BC_7 , AD7_MDC , bidir , X , 17 , 1 , Z ),"&
" 15 (BC_2 , * , control , 1 ) ,"&
" 14 (LV_BC_7 , AD8_MDIO , bidir , X , 15 , 1 , Z ),"&
" 13 (BC_2 , * , control , 1 ) ,"&
" 12 (LV_BC_7 , IRQ , bidir , X , 13 , 1 , Z ),"&
" 11 (BC_2 , * , control , 1 ) ,"&
" 10 (LV_BC_7 , GP2_LED2_E2P_SZ , bidir , X , 11 , 1 , Z ),"&
" 9 (BC_2 , * , control , 1 ) ,"&
" 8 (LV_BC_7 , AD4_GP3_LNK , bidir , X , 9 , 1 , Z ),"&
" 7 (BC_2 , * , control , 1 ) ,"&
" 6 (LV_BC_7 , AD5_OUT_VALID , bidir , X , 7 , 1 , Z ),"&
" 5 (BC_0 , * , internal , 1 ) ,"&
" 4 (BC_0 , * , internal , X ) ,"&
" 3 (BC_0 , * , internal , 1 ) ,"&
" 2 (BC_0 , * , internal , X ) ,"&
" 1 (BC_0 , * , internal , 1 ) ,"&
" 0 (BC_0 , * , internal , X ) ";
end asic_top;