--*****************************************************************
--
-- Device: M4A3-128/64 100 pin caBGA
-- File Name: M4A128NL.BSM
-- Written by: Phil Vu 04/06/00
--
-- ****************************************************************
-- ****************************************************************
-- * Copywrite 1997, Advanced Micro Devices *
-- * All rights reserved. No part of this program or publication*
-- * may be reproduced, transmitted, transcribed, stored in a *
-- * retrieval system, or translated into any language or *
-- * computer language, in any form or by any means without this *
-- * notice appearing within. *
-- ****************************************************************
-- * Advanced Micro Devices makes no warranty for the use of this*
-- * product and assumes no responsibility for any errors which *
-- * may appear within. Neither does it make a committment to *
-- * update this information. *
-- ****************************************************************
-- * This is the template BSDL file for the M5LV_128 to be used *
-- * for the purpose of verifying the parts compliance with the *
-- * IEEE standard 1149.1-1990. The BSDL languange is not at *
-- * this time a standard and IEEE holds no opinion on it or its *
-- * use. It has been submitted as a proposed addition to the *
-- * standard and should be voted on by the working committee *
-- * this year. *
-- ****************************************************************
--
-- This file has been verified by:
-- Teradyne VICTORY v 2.10
-- - Syntax Check using BSA
-- - Test vector generation using BSA
--
-- Hewlett-Packard Boundary-Scan Software
-- - Syntax Check
--
-- Genrad Boundary-Scan Software
-- - Syntax Check
-- - Physical Verification
--
-- Entity format: Mabcdddeeefggg
-- a = family (1, 2, 4, 5)
-- b = A for "A" type parts
-- c = Vcc level: 5, 3, 2, or 1 for 5.0, 3.3, 2.5, or 1.8 VDC
-- ddd = number of macrocells, such as 064
-- eee = number of I/O pins, such as 032
-- f = package: L, P, T, or B for PLCC, PQFP, TQFP, or BGA
-- ggg = number of pins, such as 044
entity M4A3128064B100 is
generic(PHYSICAL_PIN_MAP : string := "caBGA_100pin");
port (
DED_IN : in bit_vector(0 to 5); -- Clocks/Inputs
IO_A : inout bit_vector(0 to 7); -- I/O pins
IO_B : inout bit_vector(0 to 7); -- I/O pins
IO_C : inout bit_vector(0 to 7); -- I/O pins
IO_D : inout bit_vector(0 to 7); -- I/O pins
IO_E : inout bit_vector(0 to 7); -- I/O pins
IO_F : inout bit_vector(0 to 7); -- I/O pins
IO_G : inout bit_vector(0 to 7); -- I/O pins
IO_H : inout bit_vector(0 to 7); -- I/O pins
TCK, TMS, TDI, TRST: in bit; -- JTAG inputs
TDO : out bit; -- JTAG outputs
ENABLE : linkage bit; -- Program Enable pin
VCC : linkage bit_vector(0 to 5);
GND : linkage bit_vector(0 to 17)
);
use STD_1149_1_1990.all; -- get JTAG definitions and attributes
attribute PIN_MAP of M4A3128064B100 : entity is PHYSICAL_PIN_MAP;
constant caBGA_100pin : PIN_MAP_STRING :=
"DED_IN:(D2, F1, J4, G9, E10, B7), " & -- Dedicated Clk/Inp Pins
"IO_A: (B5, A4, C5, D6, A3, D5, B4, A2), " & -- I/O A0-7
"IO_B: (E3, D1, D3, D4, C1, C2, C3, B1), " & -- I/O B0-7
"IO_C: (E5, F2, G1, F3, E4, H1, F4, G2), " & -- I/O C0-7
"IO_D: (H5, K4, H4, G4, K3, J3, H3, K2), " & -- I/O D0-7
"IO_E: (J6, K7, H6, G5, K8, G6, J7, K9), " & -- I/O E0-7
"IO_F: (F8, G10, G8, G7, H10, H9, H8, J10), " & -- I/O F0-7
"IO_G: (F6, E9,D10, E8, F7,C10, E7, D9), " & -- I/O G0-7
"IO_H: (C6, A7, C7, D7, A8, B8, C8, A9), " & -- I/O H0-7
"ENABLE: J9, " &
"TDI:B2, TMS:J1, TCK:H2, TRST:B10, TDO:C9, " & -- JTAG
"VCC:( E2,E6,B6,J5,F5,F9), " & -- POWER
"GND:( A1,A5,A6,A10,B3,B9,C4,D8, " & -- GROUND PINS
"E1,F10,G3,H7,J2,J8,K1,K5, " &
"K6,K10)"; -- END OF PIN DEFINITION
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRST : signal is true;
attribute TAP_SCAN_CLOCK of TCK: signal is (20.0e6, BOTH);
-- Instruction register definitions
attribute INSTRUCTION_LENGTH of M4A3128064B100 : entity is 6;
attribute INSTRUCTION_OPCODE of M4A3128064B100 : entity is
"BYPASS (111111)," &
"EXTEST (000000)," &
"SAMPLE (000010)," &
"IDCODE (000001)," &
"USERCODE (010000)," &
"HIGHZ (010001)," &
"PRIV003 (000011)," &
"PRIV004 (000100)," &
"PRIV005 (000101)," &
"PRIV006 (000110)," &
"PRIV007 (000111)," &
"PRIV008 (001000)," &
"PRIV009 (001001)," &
"PRIV00F (001111)," &
"PRIVATE (110011,110100,110000,110010,100101,101110," &
"100111,101101,001101,001110,001010,001011,001100)";
attribute INSTRUCTION_CAPTURE of M4A3128064B100 : entity is "000001";
attribute INSTRUCTION_DISABLE of M4A3128064B100 : entity is "HIGHZ";
attribute INSTRUCTION_PRIVATE of M4A3128064B100 : entity is "PRIVATE";
attribute IDCODE_REGISTER of M4A3128064B100 : entity is
"0001" & -- version number
"0111010101101110" & -- part identification
"00010101011" & -- company code
"1"; -- mandatory 1
attribute USERCODE_REGISTER of M4A3128064B100 : entity is
"11111111111111111111111111111111";
attribute REGISTER_ACCESS of M4A3128064B100 : entity is
"BYPASS (BYPASS, HIGHZ, PRIV005, PRIV006, PRIV008, PRIV009)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"ROWREG[80](PRIV003)," &
"COLREG[792](PRIV004, PRIV007)," &
"PRIVR00F[5](PRIV00F)";
-- **************************************************************
-- * BOUNDARY SCAN CELL REGISTER DESCRIPTION
-- * THE FIRST CELL (0) IS THE CELL CLOSEST TO TDO
-- **************************************************************
attribute BOUNDARY_CELLS of M4A3128064B100 : entity is "BC_1";
attribute BOUNDARY_LENGTH of M4A3128064B100 : entity is 198;
attribute BOUNDARY_REGISTER of M4A3128064B100 : entity is
-- 1. The order of the I/O cell is OE - OUTPUT - INPUT
-- 2. The output is disabled when a 0 is shifted into the
-- OE cell.
-- 3. The pictoral representation of the Boundary scan
-- register is found in AMD document no. 93-009-6105-JT-01.
--
--
--------------------------- A0-A7 ---------------------------------
" 197 (BC_1, IO_A(0), INPUT, X)," &
" 196 (BC_1, IO_A(0), OUTPUT3, X, 195, 0, Z)," &
" 195 (BC_1, *, CONTROL, 0)," &
" 194 (BC_1, IO_A(1), INPUT, X)," &
" 193 (BC_1, IO_A(1), OUTPUT3, X, 192, 0, Z)," &
" 192 (BC_1, *, CONTROL, 0)," &
" 191 (BC_1, IO_A(2), INPUT, X)," &
" 190 (BC_1, IO_A(2), OUTPUT3, X, 189, 0, Z)," &
" 189 (BC_1, *, CONTROL, 0)," &
" 188 (BC_1, IO_A(3), INPUT, X)," &
" 187 (BC_1, IO_A(3), OUTPUT3, X, 186, 0, Z)," &
" 186 (BC_1, *, CONTROL, 0)," &
" 185 (BC_1, IO_A(4), INPUT, X)," &
" 184 (BC_1, IO_A(4), OUTPUT3, X, 183, 0, Z)," &
" 183 (BC_1, *, CONTROL, 0)," &
" 182 (BC_1, IO_A(5), INPUT, X)," &
" 181 (BC_1, IO_A(5), OUTPUT3, X, 180, 0, Z)," &
" 180 (BC_1, *, CONTROL, 0)," &
" 179 (BC_1, IO_A(6), INPUT, X)," &
" 178 (BC_1, IO_A(6), OUTPUT3, X, 177, 0, Z)," &
" 177 (BC_1, *, CONTROL, 0)," &
" 176 (BC_1, IO_A(7), INPUT, X)," &
" 175 (BC_1, IO_A(7), OUTPUT3, X, 174, 0, Z)," &
" 174 (BC_1, *, CONTROL, 0)," &
--------------------------- B7-B0 ---------------------------------
" 173 (BC_1, IO_B(7), INPUT, X)," &
" 172 (BC_1, IO_B(7), OUTPUT3, X, 171, 0, Z)," &
" 171 (BC_1, *, CONTROL, 0)," &
" 170 (BC_1, IO_B(6), INPUT, X)," &
" 169 (BC_1, IO_B(6), OUTPUT3, X, 168, 0, Z)," &
" 168 (BC_1, *, CONTROL, 0)," &
" 167 (BC_1, IO_B(5), INPUT, X)," &
" 166 (BC_1, IO_B(5), OUTPUT3, X, 165, 0, Z)," &
" 165 (BC_1, *, CONTROL, 0)," &
" 164 (BC_1, IO_B(4), INPUT, X)," &
" 163 (BC_1, IO_B(4), OUTPUT3, X, 162, 0, Z)," &
" 162 (BC_1, *, CONTROL, 0)," &
" 161 (BC_1, IO_B(3), INPUT, X)," &
" 160 (BC_1, IO_B(3), OUTPUT3, X, 159, 0, Z)," &
" 159 (BC_1, *, CONTROL, 0)," &
" 158 (BC_1, IO_B(2), INPUT, X)," &
" 157 (BC_1, IO_B(2), OUTPUT3, X, 156, 0, Z)," &
" 156 (BC_1, *, CONTROL, 0)," &
" 155 (BC_1, IO_B(1), INPUT, X)," &
" 154 (BC_1, IO_B(1), OUTPUT3, X, 153, 0, Z)," &
" 153 (BC_1, *, CONTROL, 0)," &
" 152 (BC_1, IO_B(0), INPUT, X)," &
" 151 (BC_1, IO_B(0), OUTPUT3, X, 150, 0, Z)," &
" 150 (BC_1, *, CONTROL, 0)," &
--------------------------- IN0 & IN1 -----------------------------
" 149 (BC_1, DED_IN(0), INPUT, X)," &
" 148 (BC_1, DED_IN(1), INPUT, X)," &
--------------------------- C0-C7 ---------------------------------
" 147 (BC_1, IO_C(0), INPUT, X)," &
" 146 (BC_1, IO_C(0), OUTPUT3, X, 145, 0, Z)," &
" 145 (BC_1, *, CONTROL, 0)," &
" 144 (BC_1, IO_C(1), INPUT, X)," &
" 143 (BC_1, IO_C(1), OUTPUT3, X, 142, 0, Z)," &
" 142 (BC_1, *, CONTROL, 0)," &
" 141 (BC_1, IO_C(2), INPUT, X)," &
" 140 (BC_1, IO_C(2), OUTPUT3, X, 139, 0, Z)," &
" 139 (BC_1, *, CONTROL, 0)," &
" 138 (BC_1, IO_C(3), INPUT, X)," &
" 137 (BC_1, IO_C(3), OUTPUT3, X, 136, 0, Z)," &
" 136 (BC_1, *, CONTROL, 0)," &
" 135 (BC_1, IO_C(4), INPUT, X)," &
" 134 (BC_1, IO_C(4), OUTPUT3, X, 133, 0, Z)," &
" 133 (BC_1, *, CONTROL, 0)," &
" 132 (BC_1, IO_C(5), INPUT, X)," &
" 131 (BC_1, IO_C(5), OUTPUT3, X, 130, 0, Z)," &
" 130 (BC_1, *, CONTROL, 0)," &
" 129 (BC_1, IO_C(6), INPUT, X)," &
" 128 (BC_1, IO_C(6), OUTPUT3, X, 127, 0, Z)," &
" 127 (BC_1, *, CONTROL, 0)," &
" 126 (BC_1, IO_C(7), INPUT, X)," &
" 125 (BC_1, IO_C(7), OUTPUT3, X, 124, 0, Z)," &
" 124 (BC_1, *, CONTROL, 0)," &
--------------------------- D7-D0 ---------------------------------
" 123 (BC_1, IO_D(7), INPUT, X)," &
" 122 (BC_1, IO_D(7), OUTPUT3, X, 121, 0, Z)," &
" 121 (BC_1, *, CONTROL, 0)," &
" 120 (BC_1, IO_D(6), INPUT, X)," &
" 119 (BC_1, IO_D(6), OUTPUT3, X, 118, 0, Z)," &
" 118 (BC_1, *, CONTROL, 0)," &
" 117 (BC_1, IO_D(5), INPUT, X)," &
" 116 (BC_1, IO_D(5), OUTPUT3, X, 115, 0, Z)," &
" 115 (BC_1, *, CONTROL, 0)," &
" 114 (BC_1, IO_D(4), INPUT, X)," &
" 113 (BC_1, IO_D(4), OUTPUT3, X, 112, 0, Z)," &
" 112 (BC_1, *, CONTROL, 0)," &
" 111 (BC_1, IO_D(3), INPUT, X)," &
" 110 (BC_1, IO_D(3), OUTPUT3, X, 109, 0, Z)," &
" 109 (BC_1, *, CONTROL, 0)," &
" 108 (BC_1, IO_D(2), INPUT, X)," &
" 107 (BC_1, IO_D(2), OUTPUT3, X, 106, 0, Z)," &
" 106 (BC_1, *, CONTROL, 0)," &
" 105 (BC_1, IO_D(1), INPUT, X)," &
" 104 (BC_1, IO_D(1), OUTPUT3, X, 103, 0, Z)," &
" 103 (BC_1, *, CONTROL, 0)," &
" 102 (BC_1, IO_D(0), INPUT, X)," &
" 101 (BC_1, IO_D(0), OUTPUT3, X, 100, 0, Z)," &
" 100 (BC_1, *, CONTROL, 0)," &
--------------------------- IN2 ---------------------------------
" 99 (BC_1, DED_IN(2), INPUT, X)," &
--------------------------- E0-E7 ---------------------------------
" 98 (BC_1, IO_E(0), INPUT, X)," &
" 97 (BC_1, IO_E(0), OUTPUT3, X, 96, 0, Z)," &
" 96 (BC_1, *, CONTROL, 0)," &
" 95 (BC_1, IO_E(1), INPUT, X)," &
" 94 (BC_1, IO_E(1), OUTPUT3, X, 93, 0, Z)," &
" 93 (BC_1, *, CONTROL, 0)," &
" 92 (BC_1, IO_E(2), INPUT, X)," &
" 91 (BC_1, IO_E(2), OUTPUT3, X, 90, 0, Z)," &
" 90 (BC_1, *, CONTROL, 0)," &
" 89 (BC_1, IO_E(3), INPUT, X)," &
" 88 (BC_1, IO_E(3), OUTPUT3, X, 87, 0, Z)," &
" 87 (BC_1, *, CONTROL, 0)," &
" 86 (BC_1, IO_E(4), INPUT, X)," &
" 85 (BC_1, IO_E(4), OUTPUT3, X, 84, 0, Z)," &
" 84 (BC_1, *, CONTROL, 0)," &
" 83 (BC_1, IO_E(5), INPUT, X)," &
" 82 (BC_1, IO_E(5), OUTPUT3, X, 81, 0, Z)," &
" 81 (BC_1, *, CONTROL, 0)," &
" 80 (BC_1, IO_E(6), INPUT, X)," &
" 79 (BC_1, IO_E(6), OUTPUT3, X, 78, 0, Z)," &
" 78 (BC_1, *, CONTROL, 0)," &
" 77 (BC_1, IO_E(7), INPUT, X)," &
" 76 (BC_1, IO_E(7), OUTPUT3, X, 75, 0, Z)," &
" 75 (BC_1, *, CONTROL, 0)," &
--------------------------- F7-F0 ---------------------------------
" 74 (BC_1, IO_F(7), INPUT, X)," &
" 73 (BC_1, IO_F(7), OUTPUT3, X, 72, 0, Z)," &
" 72 (BC_1, *, CONTROL, 0)," &
" 71 (BC_1, IO_F(6), INPUT, X)," &
" 70 (BC_1, IO_F(6), OUTPUT3, X, 69, 0, Z)," &
" 69 (BC_1, *, CONTROL, 0)," &
" 68 (BC_1, IO_F(5), INPUT, X)," &
" 67 (BC_1, IO_F(5), OUTPUT3, X, 66, 0, Z)," &
" 66 (BC_1, *, CONTROL, 0)," &
" 65 (BC_1, IO_F(4), INPUT, X)," &
" 64 (BC_1, IO_F(4), OUTPUT3, X, 63, 0, Z)," &
" 63 (BC_1, *, CONTROL, 0)," &
" 62 (BC_1, IO_F(3), INPUT, X)," &
" 61 (BC_1, IO_F(3), OUTPUT3, X, 60, 0, Z)," &
" 60 (BC_1, *, CONTROL, 0)," &
" 59 (BC_1, IO_F(2), INPUT, X)," &
" 58 (BC_1, IO_F(2), OUTPUT3, X, 57, 0, Z)," &
" 57 (BC_1, *, CONTROL, 0)," &
" 56 (BC_1, IO_F(1), INPUT, X)," &
" 55 (BC_1, IO_F(1), OUTPUT3, X, 54, 0, Z)," &
" 54 (BC_1, *, CONTROL, 0)," &
" 53 (BC_1, IO_F(0), INPUT, X)," &
" 52 (BC_1, IO_F(0), OUTPUT3, X, 51, 0, Z)," &
" 51 (BC_1, *, CONTROL, 0)," &
--------------------------- IN3 & IN4 -----------------------------
" 50 (BC_1, DED_IN(3), INPUT, X)," &
" 49 (BC_1, DED_IN(4), INPUT, X)," &
--------------------------- G0-G7 ---------------------------------
" 48 (BC_1, IO_G(0), INPUT, X)," &
" 47 (BC_1, IO_G(0), OUTPUT3, X, 46, 0, Z)," &
" 46 (BC_1, *, CONTROL, 0)," &
" 45 (BC_1, IO_G(1), INPUT, X)," &
" 44 (BC_1, IO_G(1), OUTPUT3, X, 43, 0, Z)," &
" 43 (BC_1, *, CONTROL, 0)," &
" 42 (BC_1, IO_G(2), INPUT, X)," &
" 41 (BC_1, IO_G(2), OUTPUT3, X, 40, 0, Z)," &
" 40 (BC_1, *, CONTROL, 0)," &
" 39 (BC_1, IO_G(3), INPUT, X)," &
" 38 (BC_1, IO_G(3), OUTPUT3, X, 37, 0, Z)," &
" 37 (BC_1, *, CONTROL, 0)," &
" 36 (BC_1, IO_G(4), INPUT, X)," &
" 35 (BC_1, IO_G(4), OUTPUT3, X, 34, 0, Z)," &
" 34 (BC_1, *, CONTROL, 0)," &
" 33 (BC_1, IO_G(5), INPUT, X)," &
" 32 (BC_1, IO_G(5), OUTPUT3, X, 31, 0, Z)," &
" 31 (BC_1, *, CONTROL, 0)," &
" 30 (BC_1, IO_G(6), INPUT, X)," &
" 29 (BC_1, IO_G(6), OUTPUT3, X, 28, 0, Z)," &
" 28 (BC_1, *, CONTROL, 0)," &
" 27 (BC_1, IO_G(7), INPUT, X)," &
" 26 (BC_1, IO_G(7), OUTPUT3, X, 25, 0, Z)," &
" 25 (BC_1, *, CONTROL, 0)," &
--------------------------- H7-H0 ---------------------------------
" 24 (BC_1, IO_H(7), INPUT, X)," &
" 23 (BC_1, IO_H(7), OUTPUT3, X, 22, 0, Z)," &
" 22 (BC_1, *, CONTROL, 0)," &
" 21 (BC_1, IO_H(6), INPUT, X)," &
" 20 (BC_1, IO_H(6), OUTPUT3, X, 19, 0, Z)," &
" 19 (BC_1, *, CONTROL, 0)," &
" 18 (BC_1, IO_H(5), INPUT, X)," &
" 17 (BC_1, IO_H(5), OUTPUT3, X, 16, 0, Z)," &
" 16 (BC_1, *, CONTROL, 0)," &
" 15 (BC_1, IO_H(4), INPUT, X)," &
" 14 (BC_1, IO_H(4), OUTPUT3, X, 13, 0, Z)," &
" 13 (BC_1, *, CONTROL, 0)," &
" 12 (BC_1, IO_H(3), INPUT, X)," &
" 11 (BC_1, IO_H(3), OUTPUT3, X, 10, 0, Z)," &
" 10 (BC_1, *, CONTROL, 0)," &
" 9 (BC_1, IO_H(2), INPUT, X)," &
" 8 (BC_1, IO_H(2), OUTPUT3, X, 7, 0, Z)," &
" 7 (BC_1, *, CONTROL, 0)," &
" 6 (BC_1, IO_H(1), INPUT, X)," &
" 5 (BC_1, IO_H(1), OUTPUT3, X, 4, 0, Z)," &
" 4 (BC_1, *, CONTROL, 0)," &
" 3 (BC_1, IO_H(0), INPUT, X)," &
" 2 (BC_1, IO_H(0), OUTPUT3, X, 1, 0, Z)," &
" 1 (BC_1, *, CONTROL, 0)," &
--------------------------- IN5 -----------------------------------
" 0 (BC_1, DED_IN(5), INPUT, X)";
end M4A3128064B100;