-- **********************************************************************
--
-- FILE : zl30145ggg.bsd
-- generated by Cz.P. as zl30145 on Fri Nov 28 10:15:41 EST 2008
-- using p.jtag.bsd rev 3.5 - 9 May, 2007
--
-- BSDL description for top level entity zl30145
-- Device : ZL30145 10G SyncE SONET Rate Cnversion PLL
-- Package : 64-pin CABGA
--
-- Number of BSC cells: 160
--
-- **********************************************************************
-- Modification History:
-- Initial release: Fri Nov 28 10:15:41 EST 2008
-- **********************************************************************
--
-- IMPORTANT NOTICE
--
-- This information is for modeling purposes only, and is not guaranteed.
--
-- This information is provided "as is" without warranty of any kind.
-- It may contain technical inaccuracies or typographical errors.
--
-- ZARLINK and ZL30145 are trademarks of ZARLINK Semiconductor. ZARLINK
-- products, marketed under trademarks, are protected under numerous US
-- and foreign patents and pending applications, maskwork rights, and
-- copyrights.
--
-- ZARLINK reserves the right to make changes to any products and
-- services at any time without notice. ZARLINK assumes no
-- responsibility or liability arising out of the application or use of
-- any information, product, or service described herein except as
-- expressly agreed to in writing by ZARLINK Corporation. ZARLINK
-- customers are advised to obtain the latest version of device
-- specifications before relying on any published information and before
-- placing orders for products or services.
--
-- ======================================================================
-- This BSDL model has been validated for syntax and semantics compliance
-- to IEEE 1149.1 using ASSET/Agilent BSDL Validation Service.
-- ======================================================================
--
-- ********************************************************************
--
-- SPECIAL NOTES
--
-- 1. All instruction opcodes other than those defined in this file
-- should be considered PRIVATE.
--
-- ********************************************************************
entity zl30145 is
generic(PHYSICAL_PIN_MAP : string := "CABGA30145_PACKAGE");
port (
APLL_CLK: out bit;
APLL_FILTER: linkage bit;
CS_B_ASEL0: in bit;
DIFF_EN: in bit;
DIFF_N: linkage bit;
DIFF_P: linkage bit;
FILTER_REF0: linkage bit;
FILTER_REF1: linkage bit;
HOLD: out bit;
I2C_EN: in bit;
IC_GND1: linkage bit;
IC_GND2: linkage bit;
IC_OPEN: linkage bit_vector (1 to 3);
INT_B: out bit;
LOCK: out bit;
NC: linkage bit_vector (1 to 7);
OSCI: linkage bit;
OSCO: linkage bit;
REF: in bit;
RST_B: in bit;
SCK_SCL: inout bit;
SI_SDA: inout bit;
SO: out bit;
TCK: in bit;
TDI: in bit;
TDO: out bit;
TMS: in bit;
TRST_B: in bit;
AVCORE: linkage bit_vector (1 to 3);
AVDD: linkage bit_vector (1 to 2);
AVSS: linkage bit_vector (1 to 4);
VCORE: linkage bit_vector (1 to 2);
VDD: linkage bit_vector (1 to 7);
VSS: linkage bit_vector (1 to 10)
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of zl30145 : entity is
"STD_1149_1_2001";
attribute PIN_MAP of zl30145 : entity is PHYSICAL_PIN_MAP;
constant CABGA30145_PACKAGE : PIN_MAP_STRING :=
"APLL_CLK : D8 , " &
"APLL_FILTER : A5 , " &
"CS_B_ASEL0 : C2 , " &
"DIFF_EN : B3 , " &
"DIFF_N : B8 , " &
"DIFF_P : A7 , " &
"FILTER_REF0 : B5 , " &
"FILTER_REF1 : C5 , " &
"HOLD : H1 , " &
"I2C_EN : H2 , " &
"IC_GND1 : H6 , " &
"IC_GND2 : B2 , " &
"IC_OPEN :(F5 , " & -- IC_OPEN[1]
"A1 , " & -- IC_OPEN[2]
"A4 ), " & -- IC_OPEN[3]
"INT_B : E2 , " &
"LOCK : E1 , " &
"NC :(A2 , " & -- NC[1]
"A3 , " & -- NC[2]
"B4 , " & -- NC[3]
"D7 , " & -- NC[4]
"G7 , " & -- NC[5]
"G8 , " & -- NC[6]
"H7 ), " & -- NC[7]
"OSCI : H4 , " &
"OSCO : H5 , " &
"REF : B1 , " &
"RST_B : G5 , " &
"SCK_SCL : C1 , " &
"SI_SDA : D2 , " &
"SO : D1 , " &
"TCK : H3 , " &
"TDI : G2 , " &
"TDO : G4 , " &
"TMS : F2 , " &
"TRST_B : G3 , " &
"AVCORE :(C7, B6, F1)," &
"AVDD :(B7, C4)," &
"AVSS :(A8, C6, G1, A6)," &
"VCORE :(F3, E6)," &
"VDD :(H8, F6, F8, E8, C8, C3, G6)," &
"VSS :(D3, D4, D5, E3, E4, E5, F4, E7, D6, F7)";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6,BOTH);
attribute TAP_SCAN_RESET of TRST_B : signal is true;
--
-- NOTE: All instruction opcodes other than those defined in this file
-- should be considered PRIVATE.
--
attribute INSTRUCTION_LENGTH of zl30145 : entity is 4;
attribute INSTRUCTION_OPCODE of zl30145 : entity is
"bypass (1111)," &
"extest (0000)," &
"idcode (0010)," &
"preload (0001)," &
"sample (0001)";
attribute INSTRUCTION_CAPTURE of zl30145 : entity is "xx01";
attribute IDCODE_REGISTER of zl30145 : entity is
"0001" & -- version
"0111010111000001" & -- part number
"00010100101" & -- manufacturer id
"1";
attribute REGISTER_ACCESS of zl30145 : entity is
"boundary (extest, sample, preload)," &
"bypass (bypass)," &
"device_id (idcode)" ;
attribute BOUNDARY_LENGTH of zl30145 : entity is 160;
attribute BOUNDARY_REGISTER of zl30145 : entity is
-- num cell port function safe ccel disval rslt
" 0 ( BC_0, *, internal, X) ," &
" 1 ( BC_0, *, internal, X) ," &
" 2 ( BC_0, *, internal, X) ," &
" 3 ( BC_0, *, internal, X) ," &
" 4 ( BC_0, *, internal, X) ," &
" 5 ( BC_0, *, internal, X) ," &
" 6 ( BC_0, *, internal, X) ," &
" 7 ( BC_0, *, internal, X) ," &
" 8 ( BC_0, *, internal, X) ," &
" 9 ( BC_0, *, internal, X) ," &
" 10 ( BC_0, *, internal, 1) ," &
" 11 ( BC_0, *, internal, X) ," &
" 12 ( BC_0, *, internal, X) ," &
" 13 ( BC_0, *, internal, X) ," &
" 14 ( BC_0, *, internal, X) ," &
" 15 ( BC_0, *, internal, 1) ," &
" 16 ( BC_0, *, internal, X) ," &
" 17 ( BC_0, *, internal, 1) ," &
" 18 ( BC_0, *, internal, X) ," &
" 19 ( BC_0, *, internal, X) ," &
" 20 ( BC_0, *, internal, X) ," &
" 21 ( BC_0, *, internal, X) ," &
" 22 ( BC_0, *, internal, X) ," &
" 23 ( BC_0, *, internal, X) ," &
" 24 ( BC_0, *, internal, X) ," &
" 25 ( BC_0, *, internal, X) ," &
" 26 ( BC_0, *, internal, X) ," &
" 27 ( BC_0, *, internal, X) ," &
" 28 ( BC_0, *, internal, X) ," &
" 29 ( BC_0, *, internal, X) ," &
" 30 ( BC_4, RST_B, input, X) ," &
" 31 ( BC_0, *, internal, X) ," &
" 32 ( BC_0, *, internal, X) ," &
" 33 ( BC_0, *, internal, 1) ," &
" 34 ( BC_0, *, internal, X) ," &
" 35 ( BC_0, *, internal, 1) ," &
" 36 ( BC_0, *, internal, X) ," &
" 37 ( BC_0, *, internal, 1) ," &
" 38 ( BC_0, *, internal, X) ," &
" 39 ( BC_0, *, internal, 1) ," &
" 40 ( BC_0, *, internal, X) ," &
" 41 ( BC_0, *, internal, 1) ," &
" 42 ( BC_0, *, internal, X) ," &
" 43 ( BC_0, *, internal, 1) ," &
" 44 ( BC_0, *, internal, X) ," &
" 45 ( BC_0, *, internal, 1) ," &
" 46 ( BC_0, *, internal, X) ," &
" 47 ( BC_0, *, internal, X) ," &
" 48 ( BC_0, *, internal, X) ," &
" 49 ( BC_0, *, internal, X) ," &
" 50 ( BC_0, *, internal, X) ," &
" 51 ( BC_0, *, internal, X) ," &
" 52 ( BC_0, *, internal, X) ," &
" 53 ( BC_0, *, internal, 1) ," &
" 54 ( BC_0, *, internal, X) ," &
" 55 ( BC_0, *, internal, 1) ," &
" 56 ( BC_0, *, internal, X) ," &
" 57 ( BC_0, *, internal, 1) ," &
" 58 ( BC_0, *, internal, X) ," &
" 59 ( BC_2, *, control, 1) ," &
" 60 ( BC_1, APLL_CLK, output3, X, 59, 1, Z) ," &
" 61 ( BC_0, *, internal, 1) ," &
" 62 ( BC_0, *, internal, X) ," &
" 63 ( BC_0, *, internal, 1) ," &
" 64 ( BC_0, *, internal, X) ," &
" 65 ( BC_0, *, internal, X) ," &
" 66 ( BC_0, *, internal, 1) ," &
" 67 ( BC_0, *, internal, X) ," &
" 68 ( BC_0, *, internal, 1) ," &
" 69 ( BC_0, *, internal, X) ," &
" 70 ( BC_0, *, internal, X) ," &
" 71 ( BC_0, *, internal, X) ," &
" 72 ( BC_0, *, internal, X) ," &
" 73 ( BC_0, *, internal, X) ," &
" 74 ( BC_0, *, internal, X) ," &
" 75 ( BC_0, *, internal, X) ," &
" 76 ( BC_0, *, internal, X) ," &
" 77 ( BC_0, *, internal, X) ," &
" 78 ( BC_0, *, internal, X) ," &
" 79 ( BC_0, *, internal, X) ," &
" 80 ( BC_0, *, internal, X) ," &
" 81 ( BC_0, *, internal, X) ," &
" 82 ( BC_0, *, internal, X) ," &
" 83 ( BC_0, *, internal, X) ," &
" 84 ( BC_0, *, internal, X) ," &
" 85 ( BC_0, *, internal, X) ," &
" 86 ( BC_0, *, internal, X) ," &
" 87 ( BC_0, *, internal, X) ," &
" 88 ( BC_4, REF, input, X) ," &
" 89 ( BC_0, *, internal, 1) ," &
" 90 ( BC_0, *, internal, X) ," &
" 91 ( BC_0, *, internal, 1) ," &
" 92 ( BC_0, *, internal, X) ," &
" 93 ( BC_0, *, internal, 1) ," &
" 94 ( BC_0, *, internal, X) ," &
" 95 ( BC_0, *, internal, 1) ," &
" 96 ( BC_0, *, internal, X) ," &
" 97 ( BC_0, *, internal, 1) ," &
" 98 ( BC_0, *, internal, X) ," &
" 99 ( BC_0, *, internal, X) ," &
" 100 ( BC_0, *, internal, X) ," &
" 101 ( BC_4, DIFF_EN, input, X) ," &
" 102 ( BC_0, *, internal, X) ," &
" 103 ( BC_0, *, internal, X) ," &
" 104 ( BC_0, *, internal, 1) ," &
" 105 ( BC_0, *, internal, X) ," &
" 106 ( BC_0, *, internal, X) ," &
" 107 ( BC_0, *, internal, X) ," &
" 108 ( BC_0, *, internal, X) ," &
" 109 ( BC_0, *, internal, X) ," &
" 110 ( BC_0, *, internal, X) ," &
" 111 ( BC_0, *, internal, X) ," &
" 112 ( BC_0, *, internal, X) ," &
" 113 ( BC_0, *, internal, X) ," &
" 114 ( BC_0, *, internal, X) ," &
" 115 ( BC_0, *, internal, X) ," &
" 116 ( BC_0, *, internal, 1) ," &
" 117 ( BC_0, *, internal, X) ," &
" 118 ( BC_0, *, internal, X) ," &
" 119 ( BC_0, *, internal, X) ," &
" 120 ( BC_0, *, internal, X) ," &
" 121 ( BC_0, *, internal, 1) ," &
" 122 ( BC_0, *, internal, X) ," &
" 123 ( BC_0, *, internal, 1) ," &
" 124 ( BC_0, *, internal, X) ," &
" 125 ( BC_0, *, internal, X) ," &
" 126 ( BC_0, *, internal, X) ," &
" 127 ( BC_0, *, internal, X) ," &
" 128 ( BC_0, *, internal, X) ," &
" 129 ( BC_0, *, internal, X) ," &
" 130 ( BC_0, *, internal, X) ," &
" 131 ( BC_0, *, internal, X) ," &
" 132 ( BC_0, *, internal, X) ," &
" 133 ( BC_0, *, internal, X) ," &
" 134 ( BC_0, *, internal, X) ," &
" 135 ( BC_2, *, control, 1) ," &
" 136 ( BC_7, SCK_SCL, bidir, X, 135, 1, Z) ," &
" 137 ( BC_4, CS_B_ASEL0, input, X) ," &
" 138 ( BC_0, *, internal, X) ," &
" 139 ( BC_0, *, internal, X) ," &
" 140 ( BC_2, *, control, 1) ," &
" 141 ( BC_7, SI_SDA, bidir, X, 140, 1, Z) ," &
" 142 ( BC_2, *, control, 1) ," &
" 143 ( BC_1, SO, output3, X, 142, 1, Z) ," &
" 144 ( BC_0, *, internal, 1) ," &
" 145 ( BC_0, *, internal, X) ," &
" 146 ( BC_2, *, control, 1) ," &
" 147 ( BC_1, INT_B, output3, X, 146, 1, Z) ," &
" 148 ( BC_0, *, internal, X) ," &
" 149 ( BC_2, *, control, 1) ," &
" 150 ( BC_1, LOCK, output3, X, 149, 1, Z) ," &
" 151 ( BC_2, *, control, 1) ," &
" 152 ( BC_1, HOLD, output3, X, 151, 1, Z) ," &
" 153 ( BC_0, *, internal, X) ," &
" 154 ( BC_0, *, internal, X) ," &
" 155 ( BC_0, *, internal, X) ," &
" 156 ( BC_0, *, internal, X) ," &
" 157 ( BC_4, I2C_EN, input, X) ," &
" 158 ( BC_0, *, internal, X) ," &
" 159 ( BC_0, *, internal, X) ";
end zl30145;
------------- end of BSDL description for the zl30145 ----------