-- Part: IDT72V73250 (32Mbs, 8k x 8k, 3.3v)
-- Ver: 0.0 Fri Sep 14 11:53:18 EDT 2001
entity IDT72V73250 is
-- Generic parameter
generic (PHYSICAL_PIN_MAP: string := "DA144");
-- Logical port description
port (
A : in bit_vector(0 to 14);
CLK : in bit;
CSX : in bit;
D : inout bit_vector(0 to 15);
DSX : in bit;
DTAX : buffer bit;
FE : in bit;
FOI : in bit;
ODEX : in bit;
RESETX: in bit;
RWX : in bit;
RX : in bit_vector(0 to 15);
TCK : in bit;
TDI : in bit;
TDO : out bit;
TMS : in bit;
TRSTX : in bit;
TX : out bit_vector(0 to 15);
VCC : linkage bit_vector(0 to 15);
GND : linkage bit_vector(0 to 15);
DNC : linkage bit_vector(0 to 34)
);
-- Standard
use STD_1149_1_1994.all;
-- Component conformance
attribute COMPONENT_CONFORMANCE of IDT72V73250: entity is "STD_1149_1_1993";
-- Device package pin mappings
attribute PIN_MAP of IDT72V73250: entity is PHYSICAL_PIN_MAP;
-- Pin-port map for package DA144
constant DA144: PIN_MAP_STRING :=
"A : (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29), " &
"CLK : 2, " &
"CSX : 12, " &
"D : (56, 55, 54, 53, 50, 49, 48, 47, 44, 43, 42, 41, 38, 37, 36, 35), " &
"DSX : 11, " &
"DTAX : 32, " &
"FE : 4, " &
"FOI : 3, " &
"ODEX : 143, " &
"RESETX: 144, " &
"RWX : 13, " &
"RX : (142, 141, 140, 139, 138, 137, 136, 135, " &
" 100, 99, 98, 97, 96, 95, 94, 93), " &
"TCK : 9, " &
"TDI : 7, " &
"TDO : 8, " &
"TMS : 6, " &
"TRSTX : 10, " &
"TX : (132, 131, 130, 129, 126, 125, 124, 123, " &
" 90, 89, 88, 87, 84, 83, 82, 81)," &
"VCC : (110, 116, 122, 128, 134, 14, 33, 39, " &
" 45, 51, 57, 67, 73, 79, 85, 91), " &
"GND : (109, 115, 121, 127, 133, 1, 34, 40, " &
" 46, 52, 58, 68, 74, 80, 86, 92), " &
"DNC : (5, 30, 31, " &
" 108, 107, 106, 105, 104, 103, 102, 101, " &
" 66, 65, 64, 63, 62, 61, 60, 59, " &
" 120, 119, 118, 117, 114, 113, 112, 111, " &
" 78, 77, 76, 75, 72, 71, 70, 69) ";
-- Scan port identification
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRSTX : signal is true;
-- Instruction register description
attribute INSTRUCTION_LENGTH of IDT72V73250: entity is 4;
attribute INSTRUCTION_OPCODE of IDT72V73250: entity is
"SAMPLE (0001)," &
"EXTEST (0000)," &
"IDCODE (0010)," &
"HIGHZ (0100)," &
"CLAMP (0011)," &
"BYPASS (1111)," &
"PRIVATE (0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110)";
attribute INSTRUCTION_CAPTURE of IDT72V73250: entity is "0101";
attribute INSTRUCTION_PRIVATE of IDT72V73250: entity is "PRIVATE";
-- Optional register description
attribute IDCODE_REGISTER of IDT72V73250: entity is
"0000" & -- version
"0000010000110111" & -- part number
"00000110011" & -- manufacturer's identity
"1"; -- required by 1149.1
-- Register access description
attribute REGISTER_ACCESS of IDT72V73250: entity is
"BYPASS (BYPASS, HIGHZ, CLAMP), " &
"BOUNDARY (SAMPLE, EXTEST), " &
"DEVICE_ID (IDCODE)";
-- Boundary-Scan register description
attribute BOUNDARY_LENGTH of IDT72V73250: entity is 120;
attribute BOUNDARY_REGISTER of IDT72V73250: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"119 (BC_4, RX(0), input, X), " &
"118 (BC_4, RX(1), input, X), " &
"117 (BC_4, RX(2), input, X), " &
"116 (BC_4, RX(3), input, X), " &
"115 (BC_4, RX(4), input, X), " &
"114 (BC_4, RX(5), input, X), " &
"113 (BC_4, RX(6), input, X), " &
"112 (BC_4, RX(7), input, X), " &
"111 (BC_1, *, control, 0), " &
"110 (BC_1, TX(0), output3, X, 111, 0, Z)," &
"109 (BC_1, *, control, 0), " &
"108 (BC_1, TX(1), output3, X, 109, 0, Z)," &
"107 (BC_1, *, control, 0), " &
"106 (BC_1, TX(2), output3, X, 107, 0, Z)," &
"105 (BC_1, *, control, 0), " &
"104 (BC_1, TX(3), output3, X, 105, 0, Z)," &
"103 (BC_1, *, control, 0), " &
"102 (BC_1, TX(4), output3, X, 103, 0, Z)," &
"101 (BC_1, *, control, 0), " &
"100 (BC_1, TX(5), output3, X, 101, 0, Z)," &
" 99 (BC_1, *, control, 0), " &
" 98 (BC_1, TX(6), output3, X, 99, 0, Z), " &
" 97 (BC_1, *, control, 0), " &
" 96 (BC_1, TX(7), output3, X, 97, 0, Z)," &
" 95 (BC_4, RX(8), input, X), " &
" 94 (BC_4, RX(9), input, X), " &
" 93 (BC_4, RX(10), input, X), " &
" 92 (BC_4, RX(11), input, X), " &
" 91 (BC_4, RX(12), input, X), " &
" 90 (BC_4, RX(13), input, X), " &
" 89 (BC_4, RX(14), input, X), " &
" 88 (BC_4, RX(15), input, X), " &
" 87 (BC_1, *, control, 0), " &
" 86 (BC_1, TX(8), output3, X, 87, 0, Z), " &
" 85 (BC_1, *, control, 0), " &
" 84 (BC_1, TX(9), output3, X, 85, 0, Z), " &
" 83 (BC_1, *, control, 0), " &
" 82 (BC_1, TX(10), output3, X, 83, 0, Z), " &
" 81 (BC_1, *, control, 0), " &
" 80 (BC_1, TX(11), output3, X, 81, 0, Z), " &
" 79 (BC_1, *, control, 0), " &
" 78 (BC_1, TX(12), output3, X, 79, 0, Z), " &
" 77 (BC_1, *, control, 0), " &
" 76 (BC_1, TX(13), output3, X, 77, 0, Z), " &
" 75 (BC_1, *, control, 0), " &
" 74 (BC_1, TX(14), output3, X, 75, 0, Z), " &
" 73 (BC_1, *, control, 0), " &
" 72 (BC_1, TX(15), output3, X, 73, 0, Z)," &
" 71 (BC_1, *, control, 0), " &
" 70 (BC_1, D(0), output3, X, 71, 0, Z)," &
" 69 (BC_4, D(0), input, X), " &
" 68 (BC_1, *, control, 0), " &
" 67 (BC_1, D(1), output3, X, 68, 0, Z), " &
" 66 (BC_4, D(1), input, X), " &
" 65 (BC_1, *, control, 0), " &
" 64 (BC_1, D(2), output3, X, 65, 0, Z), " &
" 63 (BC_4, D(2), input, X), " &
" 62 (BC_1, *, control, 0), " &
" 61 (BC_1, D(3), output3, X, 62, 0, Z), " &
" 60 (BC_4, D(3), input, X), " &
" 59 (BC_1, *, control, 0), " &
" 58 (BC_1, D(4), output3, X, 59, 0, Z), " &
" 57 (BC_4, D(4), input, X), " &
" 56 (BC_1, *, control, 0), " &
" 55 (BC_1, D(5), output3, X, 56, 0, Z), " &
" 54 (BC_4, D(5), input, X), " &
" 53 (BC_1, *, control, 0), " &
" 52 (BC_1, D(6), output3, X, 53, 0, Z), " &
" 51 (BC_4, D(6), input, X), " &
" 50 (BC_1, *, control, 0), " &
" 49 (BC_1, D(7), output3, X, 50, 0, Z), " &
" 48 (BC_4, D(7), input, X), " &
" 47 (BC_1, *, control, 0), " &
" 46 (BC_1, D(8), output3, X, 47, 0, Z), " &
" 45 (BC_4, D(8), input, X), " &
" 44 (BC_1, *, control, 0), " &
" 43 (BC_1, D(9), output3, X, 44, 0, Z), " &
" 42 (BC_4, D(9), input, X), " &
" 41 (BC_1, *, control, 0), " &
" 40 (BC_1, D(10), output3, X, 41, 0, Z), " &
" 39 (BC_4, D(10), input, X), " &
" 38 (BC_1, *, control, 0), " &
" 37 (BC_1, D(11), output3, X, 38, 0, Z), " &
" 36 (BC_4, D(11), input, X), " &
" 35 (BC_1, *, control, 0), " &
" 34 (BC_1, D(12), output3, X, 35, 0, Z), " &
" 33 (BC_4, D(12), input, X), " &
" 32 (BC_1, *, control, 0), " &
" 31 (BC_1, D(13), output3, X, 32, 0, Z), " &
" 30 (BC_4, D(13), input, X), " &
" 29 (BC_1, *, control, 0), " &
" 28 (BC_1, D(14), output3, X, 29, 0, Z), " &
" 27 (BC_4, D(14), input, X), " &
" 26 (BC_1, *, control, 0), " &
" 25 (BC_1, D(15), output3, X, 26, 0, Z), " &
" 24 (BC_4, D(15), input, X), " &
" 23 (BC_1, DTAX, output2, X), " &
" 22 (BC_4, A(14), input, X), " &
" 21 (BC_4, A(13), input, X), " &
" 20 (BC_4, A(12), input, X), " &
" 19 (BC_4, A(11), input, X), " &
" 18 (BC_4, A(10), input, X), " &
" 17 (BC_4, A(9), input, X), " &
" 16 (BC_4, A(8), input, X), " &
" 15 (BC_4, A(7), input, X), " &
" 14 (BC_4, A(6), input, X), " &
" 13 (BC_4, A(5), input, X), " &
" 12 (BC_4, A(4), input, X), " &
" 11 (BC_4, A(3), input, X), " &
" 10 (BC_4, A(2), input, X), " &
" 9 (BC_4, A(1), input, X), " &
" 8 (BC_4, A(0), input, X), " &
" 7 (BC_4, RWX, input, X), " &
" 6 (BC_4, CSX, input, X), " &
" 5 (BC_4, DSX, input, X), " &
" 4 (BC_4, FE, input, X), " &
" 3 (BC_4, FOI, input, X), " &
" 2 (BC_4, CLK, clock, X), " &
" 1 (BC_4, RESETX, input, X), " &
" 0 (BC_4, ODEX, input, X) ";
end IDT72V73250;