----------------------------------------------------------------------
-- TI TMS320VC5421 16-Bit 144-pin Fixed-Point DSP's --
-- with Boundary Scan --
----------------------------------------------------------------------
-- Supported Devices: TMS320VC5421 144-pin Revision 1.0 and higher --
----------------------------------------------------------------------
-- --
-- This file contains the boundary scan description --
-- of CPU B of the 5421 only. --
-- --
----------------------------------------------------------------------
-- Created by : Texas Instruments Incorporated --
-- Documentation : TMS320VC54x Users Guide --
-- BSDL Revision : 1.0 - Original --
-- 1.1 - <changes made to cpu A BSDL file only> --
-- 1.2 - Reverse chain order --
-- --
-- BSDL status : Preliminary --
-- Date created : 01/25/2000 --
-- Last updated : 07/24/2000 --
----------------------------------------------------------------------
-- --
-- IMPORTANT NOTICE
-- Texas Instruments Incorporated (TI) reserves the right to make
-- changes to its products or to discontinue any semiconductor
-- product or service without notice, and advises its customers to
-- obtain the latest version of the relevant information to
-- verify, before placing orders, that the information being
-- relied on is current.
-- TI warrants performance of its semiconductor products and
-- related software to the specifications applicable at the time
-- of sale in accordance with TI's standard warranty. Testing and
-- other quality control techniques are utilized to the extent TI
-- deems necessary to support this warranty. Specific testing of
-- all parameters of each device is not necessarily performed,
-- except those mandated by government requirements.
--
-- Certain applications using semiconductor devices may involve
-- potential risks of death, personal injury, or severe property
-- or environmental damage ("Critical Applications").
-- TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
-- AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN
-- LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
-- CRITICAL APPLICATIONS.
-- Inclusion of TI products in such applications is understood
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-- applications should be directed to TI through a local SC sales
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-- In order to minimize risks associated with the customer's
-- applications, adequate design and operating safeguards should
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-- customer to minimize inherent or procedural hazards.
-- TI assumes no liability for applications assistance, customer
-- product design, software performance, or infringement of
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-- represent that any license, either express or implied, is
-- granted under any patent right, copyright, mask work right, or
-- other intellectual property right of TI covering or relating
-- to any combination, machine, or process in which such
-- semiconductor products or services might be or are used.
-- Copyright (c) 2000, Texas Instruments Incorporated
-------------------------------------------------------------------
entity TMS320VC5421_cpu_B is
generic (PHYSICAL_PIN_MAP : string := "GGU");
port
(B_BCLKR0 : inout bit;
B_BCLKR1 : inout bit;
B_BCLKR2 : inout bit;
B_BCLKX0 : inout bit;
B_BCLKX1 : inout bit;
B_BCLKX2 : inout bit;
B_BDR0 : in bit;
B_BDR1 : in bit;
B_BDR2 : in bit;
B_BDX0 : out bit;
B_BDX1 : out bit;
B_BDX2 : out bit;
B_BFSR0 : inout bit;
B_BFSR1 : inout bit;
B_BFSR2 : inout bit;
B_BFSX0 : inout bit;
B_BFSX1 : inout bit;
B_BFSX2 : inout bit;
B_INT0 : in bit;
B_INT1 : in bit;
B_NMI : in bit;
B_XF : out bit;
B_RS : in bit;
B_CLKOUT : out bit;
B_GPIO0 : inout bit;
B_GPIO1 : inout bit;
B_GPIO2 : inout bit;
B_GPIO3 : inout bit;
EMU0 : in bit;
EMU1 : in bit;
CVDD : linkage bit_vector(1 to 4);
DVDD : linkage bit_vector(1 to 3);
VSS : linkage bit_vector(1 to 9);
TMS : in bit;
TCK : in bit;
TDI : in bit;
TDO : out bit;
TRST : in bit);
use STD_1149_1_1994.all; -- Get standard attributes and definitions
use TI_BIDIR.all; -- Get C54X BIDIR cell attributes
----------------------------------------------------------------------
-- This package type TI_BIDIR must be available to your toolset. --
-- In most cases this text should be placed in a separate file --
-- named 'TI_BIDIR' that can be referenced via the previous --
-- 'use TI_BIDIR.all' statement. --
--
-- package TI_BIDIR is
-- use STD_1149_1_1990.all;
-- constant BC_BIDIR : CELL_INFO;
-- end TI_BIDIR;
--
-- package body TI_BIDIR is
-- constant BC_BIDIR : CELL_INFO :=
-- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PI),
-- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
-- (BIDIR_IN, INTEST, PI), (BIDIR_OUT, INTEST, PI));
-- end TI_BIDIR;
----------------------------------------------------------------------
-- attribute BOUNDARY_CELLS of TMS320VC5421_cpu_B : entity is
-- "BC_1, BC_2, BC_BIDIR";
attribute COMPONENT_CONFORMANCE of TMS320VC5421_cpu_B: entity is "STD_1149_1_1993";
attribute PIN_MAP of TMS320VC5421_cpu_B: entity is PHYSICAL_PIN_MAP;
constant GGU : PIN_MAP_STRING :=
" B_BCLKX2 : A08, " &
" B_BDX2 : B08, " &
" B_BFSX2 : C08, " &
" B_BDR2 : C09, " &
" B_BCLKR2 : D08, " &
" B_BFSR2 : D09, " &
" B_INT0 : D11, " &
" B_INT1 : D12, " &
" B_NMI : D13, " &
" B_BFSR1 : F10, " &
" B_GPIO3 : E10, " &
" B_GPIO2 : E11, " &
" B_GPIO1 : E12, " &
" B_GPIO0 : E13, " &
" B_BDR1 : F11, " &
" B_BCLKR1 : G10, " &
" B_BFSX1 : G11, " &
" B_BDX1 : G12, " &
" B_BCLKX1 : H13, " &
" TCK : J04, " &
" B_CLKOUT : J10, " &
" B_XF : J11, " &
" B_RS : J12, " &
" TMS : K01, " &
" TDI : K02, " &
" TRST : K03, " &
" B_BDR0 : K08, " &
" EMU1 : L01, " &
" B_BDX0 : L07, " &
" B_BCLKR0 : L08, " &
" B_BFSR0 : L09, " &
" EMU0 : M01, " &
" TDO : M02, " &
" B_BFSX0 : M08, " &
" B_BCLKX0 : N07, " &
" VSS: (H02,H11,L13,M05,M09,M12,N01,N03,N08), "&
" CVDD:(H01,H12,N05,N09), "&
" DVDD:(K07,L02,L12)" ;
-- *********************************************************
constant PGE : PIN_MAP_STRING :=
" B_BCLKX2 :124, " &
" B_BDX2 :123, " &
" B_BFSX2 :122, " &
" B_BDR2 :118, " &
" B_BCLKR2 :121, " &
" B_BFSR2 :117, " &
" B_INT0 :103, " &
" B_INT1 :102, " &
" B_NMI :101, " &
" B_BFSR1 :96, " &
" B_GPIO3 :100, " &
" B_GPIO2 :99, " &
" B_GPIO1 :98, " &
" B_GPIO0 :97, " &
" B_BDR1 :95, " &
" B_BCLKR1 :92, " &
" B_BFSX1 :91, " &
" B_BDX1 :89, " &
" B_BCLKX1 :88, " &
" TCK :28, " &
" B_CLKOUT :81, " &
" B_XF :82, " &
" B_RS :83, " &
" TMS :29, " &
" TDI :30, " &
" TRST :31, " &
" B_BDR0 :60, " &
" EMU1 :32, " &
" B_BDX0 :55, " &
" B_BCLKR0 :59, " &
" B_BFSR0 :63, " &
" EMU0 :35, " &
" TDO :36, " &
" B_BFSX0 :58, " &
" B_BCLKX0 :54, " &
" VSS: (76,86,90,93,106,119,125,134,144), "&
" CVDD:(87,94,120,133), "&
" DVDD:(75,112,130)";
-- *********************************************************
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRST : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (25.00e6, BOTH);
attribute COMPLIANCE_PATTERNS of TMS320VC5421_cpu_B: entity is "(EMU1,EMU0)(11)";
attribute INSTRUCTION_LENGTH of TMS320VC5421_cpu_B: entity is 8;
attribute INSTRUCTION_OPCODE of TMS320VC5421_cpu_B : entity is
"EXTEST (00000000), " &
"BYPASS (11111111), " &
"HIGHZ (00000110), " &
"SAMPLE (00000010) " ;
attribute INSTRUCTION_CAPTURE of TMS320VC5421_cpu_B : entity is "XXXXXX01";
attribute REGISTER_ACCESS of TMS320VC5421_cpu_B : entity is
"BOUNDARY (EXTEST, SAMPLE)," &
"BYPASS (BYPASS, HIGHZ) " ;
attribute BOUNDARY_LENGTH of TMS320VC5421_cpu_B : entity is 48;
attribute BOUNDARY_REGISTER of TMS320VC5421_cpu_B : entity is
----------------------------------------------------------------
-- CELL CELL PIN CELL CNTRL
-- # NAME ,NAME ,TYPE , ,CELL
----------------------------------------------------------------
"0 (BC_1 ,B_BDX2 ,OUTPUT3 ,X ,5 ,1 ,Z), " &
"1 (BC_BIDIR ,B_BFSX2 ,BIDIR ,X ,6 ,1 ,Z), " &
"2 (BC_BIDIR ,B_BFSR2 ,BIDIR ,X ,7 ,1 ,Z), " &
"3 (BC_BIDIR ,B_BCLKX2 ,BIDIR ,X ,8 ,1 ,Z), " &
"4 (BC_BIDIR ,B_BCLKR2 ,BIDIR ,X ,9 ,1 ,Z), " &
"5 (BC_1 ,* ,CONTROL ,1 ), " &
"6 (BC_1 ,* ,CONTROL ,1 ), " &
"7 (BC_1 ,* ,CONTROL ,1 ), " &
"8 (BC_1 ,* ,CONTROL ,1 ), " &
"9 (BC_1 ,* ,CONTROL ,1 ), " &
"10 (BC_2 ,B_BDR2 ,INPUT ,X ), " &
"11 (BC_1 ,B_BDX1 ,OUTPUT3 ,X ,16 ,1 ,Z), " &
"12 (BC_BIDIR ,B_BFSX1 ,BIDIR ,X ,17 ,1 ,Z), " &
"13 (BC_BIDIR ,B_BFSR1 ,BIDIR ,X ,18 ,1 ,Z), " &
"14 (BC_BIDIR ,B_BCLKX1 ,BIDIR ,X ,19 ,1 ,Z), " &
"15 (BC_BIDIR ,B_BCLKR1 ,BIDIR ,X ,20 ,1 ,Z), " &
"16 (BC_1 ,* ,CONTROL ,1 ), " &
"17 (BC_1 ,* ,CONTROL ,1 ), " &
"18 (BC_1 ,* ,CONTROL ,1 ), " &
"19 (BC_1 ,* ,CONTROL ,1 ), " &
"20 (BC_1 ,* ,CONTROL ,1 ), " &
"21 (BC_2 ,B_BDR1 ,INPUT ,X ), " &
"22 (BC_1 ,B_BDX0 ,OUTPUT3 ,X ,27 ,1 ,Z), " &
"23 (BC_BIDIR ,B_BFSX0 ,BIDIR ,X ,28 ,1 ,Z), " &
"24 (BC_BIDIR ,B_BFSR0 ,BIDIR ,X ,29 ,1 ,Z), " &
"25 (BC_BIDIR ,B_BCLKX0 ,BIDIR ,X ,30 ,1 ,Z), " &
"26 (BC_BIDIR ,B_BCLKR0 ,BIDIR ,X ,31 ,1 ,Z), " &
"27 (BC_1 ,* ,CONTROL ,1 ), " &
"28 (BC_1 ,* ,CONTROL ,1 ), " &
"29 (BC_1 ,* ,CONTROL ,1 ), " &
"30 (BC_1 ,* ,CONTROL ,1 ), " &
"31 (BC_1 ,* ,CONTROL ,1 ), " &
"32 (BC_2 ,B_BDR0 ,INPUT ,X ), " &
"33 (BC_1 ,B_XF ,OUTPUT3 ,X ,43 ,1 ,Z), " &
"34 (BC_1 ,B_CLKOUT ,OUTPUT3 ,X ,43 ,1 ,Z), " &
"35 (BC_BIDIR ,B_GPIO0 ,BIDIR ,X ,39 ,1 ,Z), " &
"36 (BC_BIDIR ,B_GPIO1 ,BIDIR ,X ,40 ,1 ,Z), " &
"37 (BC_BIDIR ,B_GPIO2 ,BIDIR ,X ,41 ,1 ,Z), " &
"38 (BC_BIDIR ,B_GPIO3 ,BIDIR ,X ,42 ,1 ,Z), " &
"39 (BC_1 ,* ,CONTROL ,1 ), " &
"40 (BC_1 ,* ,CONTROL ,1 ), " &
"41 (BC_1 ,* ,CONTROL ,1 ), " &
"42 (BC_1 ,* ,CONTROL ,1 ), " &
"43 (BC_1 ,* ,CONTROL ,1 ), " &
"44 (BC_2 ,B_INT1 ,INPUT ,X ), " &
"45 (BC_2 ,B_INT0 ,INPUT ,X ), " &
"46 (BC_2 ,B_NMI ,INPUT ,X ), " &
"47 (BC_2 ,B_RS ,INPUT ,X ) " ;
end TMS320VC5421_cpu_B;