-- ***************************************************************
-- Company: Integrated Device Technology, Inc.
--
-- Tundra Document number:
--
-- Title: BSDL file of Tsi568
-- Generated by : Andi Sugandi
--
-- Release status: formal issue
-- Security level: client use
-- BSDL Version 2001
-- Group ownership: DFT Revision Date:
-- Released by :
-- Revision History:
-- Dec 17, 2004: initial release
-- Apr 12, 2005: changed JTAG ID revision fr 0000 to 0001 for vA1
-- Sep 08, 2005: changed JTAG ID revision fr 0001 to 0010 for vA2
-- Aug 26, 2009: updated with IDT formatting
--
--
-- Agilent BSDL Syntax Checker -> passed Sep 08, 2005
-- Note: Serdes pins are not on boundary scan chain.
--
--
-- ***************************************************************
-- Generated by boundaryScanGenerate 4.1-Build20031130.014 on 09/23/04 18:31:34
-- BSDL Version 2001
entity Tsi568 is
generic (PHYSICAL_PIN_MAP : string := "BGA_675_27");
port (
-- Port List
SP0_TA_P : linkage bit;
SP0_TA_N : linkage bit;
SP0_RA_P : linkage bit;
SP0_RA_N : linkage bit;
SP0_TB_P : linkage bit;
SP0_TB_N : linkage bit;
SP0_RB_P : linkage bit;
SP0_RB_N : linkage bit;
SP0_TC_P : linkage bit;
SP0_TC_N : linkage bit;
SP0_RC_P : linkage bit;
SP0_RC_N : linkage bit;
SP0_TD_P : linkage bit;
SP0_TD_N : linkage bit;
SP0_RD_P : linkage bit;
SP0_RD_N : linkage bit;
SP0_RREF : linkage bit;
SP0_AVDD : linkage bit;
SP0_VTT : linkage bit;
SP2_TA_P : linkage bit;
SP2_TA_N : linkage bit;
SP2_RA_P : linkage bit;
SP2_RA_N : linkage bit;
SP2_TB_P : linkage bit;
SP2_TB_N : linkage bit;
SP2_RB_P : linkage bit;
SP2_RB_N : linkage bit;
SP2_TC_P : linkage bit;
SP2_TC_N : linkage bit;
SP2_RC_P : linkage bit;
SP2_RC_N : linkage bit;
SP2_TD_P : linkage bit;
SP2_TD_N : linkage bit;
SP2_RD_P : linkage bit;
SP2_RD_N : linkage bit;
SP2_RREF : linkage bit;
SP2_AVDD : linkage bit;
SP2_VTT : linkage bit;
SP4_TA_P : linkage bit;
SP4_TA_N : linkage bit;
SP4_RA_P : linkage bit;
SP4_RA_N : linkage bit;
SP4_TB_P : linkage bit;
SP4_TB_N : linkage bit;
SP4_RB_P : linkage bit;
SP4_RB_N : linkage bit;
SP4_TC_P : linkage bit;
SP4_TC_N : linkage bit;
SP4_RC_P : linkage bit;
SP4_RC_N : linkage bit;
SP4_TD_P : linkage bit;
SP4_TD_N : linkage bit;
SP4_RD_P : linkage bit;
SP4_RD_N : linkage bit;
SP4_RREF : linkage bit;
SP4_AVDD : linkage bit;
SP4_VTT : linkage bit;
SP6_TA_P : linkage bit;
SP6_TA_N : linkage bit;
SP6_RA_P : linkage bit;
SP6_RA_N : linkage bit;
SP6_TB_P : linkage bit;
SP6_TB_N : linkage bit;
SP6_RB_P : linkage bit;
SP6_RB_N : linkage bit;
SP6_TC_P : linkage bit;
SP6_TC_N : linkage bit;
SP6_RC_P : linkage bit;
SP6_RC_N : linkage bit;
SP6_TD_P : linkage bit;
SP6_TD_N : linkage bit;
SP6_RD_P : linkage bit;
SP6_RD_N : linkage bit;
SP6_RREF : linkage bit;
SP6_AVDD : linkage bit;
SP6_VTT : linkage bit;
SP8_TA_P : linkage bit;
SP8_TA_N : linkage bit;
SP8_RA_P : linkage bit;
SP8_RA_N : linkage bit;
SP8_TB_P : linkage bit;
SP8_TB_N : linkage bit;
SP8_RB_P : linkage bit;
SP8_RB_N : linkage bit;
SP8_TC_P : linkage bit;
SP8_TC_N : linkage bit;
SP8_RC_P : linkage bit;
SP8_RC_N : linkage bit;
SP8_TD_P : linkage bit;
SP8_TD_N : linkage bit;
SP8_RD_P : linkage bit;
SP8_RD_N : linkage bit;
SP8_RREF : linkage bit;
SP8_AVDD : linkage bit;
SP8_VTT : linkage bit;
SP10_TA_P : linkage bit;
SP10_TA_N : linkage bit;
SP10_RA_P : linkage bit;
SP10_RA_N : linkage bit;
SP10_TB_P : linkage bit;
SP10_TB_N : linkage bit;
SP10_RB_P : linkage bit;
SP10_RB_N : linkage bit;
SP10_TC_P : linkage bit;
SP10_TC_N : linkage bit;
SP10_RC_P : linkage bit;
SP10_RC_N : linkage bit;
SP10_TD_P : linkage bit;
SP10_TD_N : linkage bit;
SP10_RD_P : linkage bit;
SP10_RD_N : linkage bit;
SP10_RREF : linkage bit;
SP10_AVDD : linkage bit;
SP10_VTT : linkage bit;
SP12_TA_P : linkage bit;
SP12_TA_N : linkage bit;
SP12_RA_P : linkage bit;
SP12_RA_N : linkage bit;
SP12_TB_P : linkage bit;
SP12_TB_N : linkage bit;
SP12_RB_P : linkage bit;
SP12_RB_N : linkage bit;
SP12_TC_P : linkage bit;
SP12_TC_N : linkage bit;
SP12_RC_P : linkage bit;
SP12_RC_N : linkage bit;
SP12_TD_P : linkage bit;
SP12_TD_N : linkage bit;
SP12_RD_P : linkage bit;
SP12_RD_N : linkage bit;
SP12_RREF : linkage bit;
SP12_AVDD : linkage bit;
SP12_VTT : linkage bit;
SP14_TA_P : linkage bit;
SP14_TA_N : linkage bit;
SP14_RA_P : linkage bit;
SP14_RA_N : linkage bit;
SP14_TB_P : linkage bit;
SP14_TB_N : linkage bit;
SP14_RB_P : linkage bit;
SP14_RB_N : linkage bit;
SP14_TC_P : linkage bit;
SP14_TC_N : linkage bit;
SP14_RC_P : linkage bit;
SP14_RC_N : linkage bit;
SP14_TD_P : linkage bit;
SP14_TD_N : linkage bit;
SP14_RD_P : linkage bit;
SP14_RD_N : linkage bit;
SP14_RREF : linkage bit;
SP14_AVDD : linkage bit;
SP14_VTT : linkage bit;
P_CLK : in bit;
S_CLK_1_P : linkage bit;
S_CLK_1_N : linkage bit;
S_CLK_2_P : linkage bit;
S_CLK_2_N : linkage bit;
I2C_SCLK : inout bit;
I2C_SD : inout bit;
I2C_DISABLE : inout bit;
HARD_RST_B : linkage bit;
INT_B : inout bit;
SW_RST_B : inout bit;
TCK : in bit;
TMS : in bit;
TDI : in bit;
TDO : out bit;
TRST_B : in bit;
DI : in bit;
DO : out bit;
SP_IO_SPEED : inout bit_vector( 1 downto 0 );
SP0_PWRDN : inout bit;
SP1_PWRDN : inout bit;
SP2_PWRDN : inout bit;
SP3_PWRDN : inout bit;
SP4_PWRDN : inout bit;
SP5_PWRDN : inout bit;
SP6_PWRDN : inout bit;
SP7_PWRDN : inout bit;
SP8_PWRDN : inout bit;
SP9_PWRDN : inout bit;
SP10_PWRDN : inout bit;
SP11_PWRDN : inout bit;
SP12_PWRDN : inout bit;
SP13_PWRDN : inout bit;
SP14_PWRDN : inout bit;
SP15_PWRDN : inout bit;
SP0_MODESEL : inout bit;
SP2_MODESEL : inout bit;
SP4_MODESEL : inout bit;
SP6_MODESEL : inout bit;
SP8_MODESEL : inout bit;
SP10_MODESEL : inout bit;
SP12_MODESEL : inout bit;
SP14_MODESEL : inout bit;
DEV_ID_SEL : linkage bit;
SP_RX_SWAP : inout bit;
SP_TX_SWAP : inout bit;
VDD_IO : linkage bit_vector( 11 downto 0 );
VSS_IO : linkage bit_vector( 12 downto 0 );
VSS : linkage bit_vector( 90 downto 0 );
VDD : linkage bit_vector( 49 downto 0 );
SP_VDD : linkage bit_vector( 25 downto 0 );
SPY_CLK_0 : linkage bit;
SPY_CLK_1 : linkage bit);
use STD_1149_1_2001.all;
use LVS_BSCAN_CELLS.all;
attribute COMPONENT_CONFORMANCE of Tsi568: entity is "STD_1149_1_2001";
--Pin mappings
attribute PIN_MAP of Tsi568: entity is PHYSICAL_PIN_MAP;
constant DEFAULT_PACKAGE_NAME: PIN_MAP_STRING :=
"SP0_TA_P : c2 , " &
"SP0_TA_N : c1 , " &
"SP0_RA_P : c4 , " &
"SP0_RA_N : c5 , " &
"SP0_TB_P : e1 , " &
"SP0_TB_N : e2 , " &
"SP0_RB_P : e5 , " &
"SP0_RB_N : e4 , " &
"SP0_TC_P : g2 , " &
"SP0_TC_N : g1 , " &
"SP0_RC_P : g4 , " &
"SP0_RC_N : g5 , " &
"SP0_TD_P : j1 , " &
"SP0_TD_N : j2 , " &
"SP0_RD_P : j5 , " &
"SP0_RD_N : j4 , " &
"SP0_RREF : f4 , " &
"SP0_AVDD : f5 , " &
"SP0_VTT : h5 , " &
"SP2_TA_P : ae6 , " &
"SP2_TA_N : af6 , " &
"SP2_RA_P : ac6 , " &
"SP2_RA_N : ab6 , " &
"SP2_TB_P : af8 , " &
"SP2_TB_N : ae8 , " &
"SP2_RB_P : ab8 , " &
"SP2_RB_N : ac8 , " &
"SP2_TC_P : ae10 , " &
"SP2_TC_N : af10 , " &
"SP2_RC_P : ac10 , " &
"SP2_RC_N : ab10 , " &
"SP2_TD_P : af12 , " &
"SP2_TD_N : ae12 , " &
"SP2_RD_P : ab12 , " &
"SP2_RD_N : ac12 , " &
"SP2_RREF : ac9 , " &
"SP2_AVDD : ab9 , " &
"SP2_VTT : ab11 , " &
"SP4_TA_P : aa25 , " &
"SP4_TA_N : aa26 , " &
"SP4_RA_P : aa23 , " &
"SP4_RA_N : aa22 , " &
"SP4_TB_P : w26 , " &
"SP4_TB_N : w25 , " &
"SP4_RB_P : w22 , " &
"SP4_RB_N : w23 , " &
"SP4_TC_P : u25 , " &
"SP4_TC_N : u26 , " &
"SP4_RC_P : u23 , " &
"SP4_RC_N : u22 , " &
"SP4_TD_P : r26 , " &
"SP4_TD_N : r25 , " &
"SP4_RD_P : r22 , " &
"SP4_RD_N : r23 , " &
"SP4_RREF : v23 , " &
"SP4_AVDD : v22 , " &
"SP4_VTT : t22 , " &
"SP6_TA_P : b21 , " &
"SP6_TA_N : a21 , " &
"SP6_RA_P : d21 , " &
"SP6_RA_N : e21 , " &
"SP6_TB_P : a19 , " &
"SP6_TB_N : b19 , " &
"SP6_RB_P : e19 , " &
"SP6_RB_N : d19 , " &
"SP6_TC_P : b17 , " &
"SP6_TC_N : a17 , " &
"SP6_RC_P : d17 , " &
"SP6_RC_N : e17 , " &
"SP6_TD_P : a15 , " &
"SP6_TD_N : b15 , " &
"SP6_RD_P : e15 , " &
"SP6_RD_N : d15 , " &
"SP6_RREF : d18 , " &
"SP6_AVDD : e18 , " &
"SP6_VTT : e16 , " &
"SP8_TA_P : l2 , " &
"SP8_TA_N : l1 , " &
"SP8_RA_P : l4 , " &
"SP8_RA_N : l5 , " &
"SP8_TB_P : n1 , " &
"SP8_TB_N : n2 , " &
"SP8_RB_P : n5 , " &
"SP8_RB_N : n4 , " &
"SP8_TC_P : r2 , " &
"SP8_TC_N : r1 , " &
"SP8_RC_P : r4 , " &
"SP8_RC_N : r5 , " &
"SP8_TD_P : u1 , " &
"SP8_TD_N : u2 , " &
"SP8_RD_P : u5 , " &
"SP8_RD_N : u4 , " &
"SP8_RREF : p4 , " &
"SP8_AVDD : p5 , " &
"SP8_VTT : t5 , " &
"SP10_TA_P : ae14 , " &
"SP10_TA_N : af14 , " &
"SP10_RA_P : ac14 , " &
"SP10_RA_N : ab14 , " &
"SP10_TB_P : af16 , " &
"SP10_TB_N : ae16 , " &
"SP10_RB_P : ab16 , " &
"SP10_RB_N : ac16 , " &
"SP10_TC_P : ae18 , " &
"SP10_TC_N : af18 , " &
"SP10_RC_P : ac18 , " &
"SP10_RC_N : ab18 , " &
"SP10_TD_P : af20 , " &
"SP10_TD_N : ae20 , " &
"SP10_RD_P : ab20 , " &
"SP10_RD_N : ac20 , " &
"SP10_RREF : ac17 , " &
"SP10_AVDD : ab17 , " &
"SP10_VTT : ab19 , " &
"SP12_TA_P : n25 , " &
"SP12_TA_N : n26 , " &
"SP12_RA_P : n23 , " &
"SP12_RA_N : n22 , " &
"SP12_TB_P : l26 , " &
"SP12_TB_N : l25 , " &
"SP12_RB_P : l22 , " &
"SP12_RB_N : l23 , " &
"SP12_TC_P : j25 , " &
"SP12_TC_N : j26 , " &
"SP12_RC_P : j23 , " &
"SP12_RC_N : j22 , " &
"SP12_TD_P : g26 , " &
"SP12_TD_N : g25 , " &
"SP12_RD_P : g22 , " &
"SP12_RD_N : g23 , " &
"SP12_RREF : k23 , " &
"SP12_AVDD : k22 , " &
"SP12_VTT : h22 , " &
"SP14_TA_P : b13 , " &
"SP14_TA_N : a13 , " &
"SP14_RA_P : d13 , " &
"SP14_RA_N : e13 , " &
"SP14_TB_P : a11 , " &
"SP14_TB_N : b11 , " &
"SP14_RB_P : e11 , " &
"SP14_RB_N : d11 , " &
"SP14_TC_P : b9 , " &
"SP14_TC_N : a9 , " &
"SP14_RC_P : d9 , " &
"SP14_RC_N : e9 , " &
"SP14_TD_P : a7 , " &
"SP14_TD_N : b7 , " &
"SP14_RD_P : e7 , " &
"SP14_RD_N : d7 , " &
"SP14_RREF : d10 , " &
"SP14_AVDD : e10 , " &
"SP14_VTT : e8 , " &
"P_CLK : af1 , " &
"S_CLK_1_P : b24 , " &
"S_CLK_1_N : b25 , " &
"S_CLK_2_P : d24 , " &
"S_CLK_2_N : d25 , " &
"I2C_SCLK : af25 , " &
"I2C_SD : ae24 , " &
"I2C_DISABLE : ac24 , " &
"HARD_RST_B : af2 , " &
"INT_B : ac2 , " &
"SW_RST_B : ad3 , " &
"TCK : af26 , " &
"TMS : ac26 , " &
"TDI : ad26 , " &
"TDO : ad25 , " &
"TRST_B : ae26 , " &
"DI : ae3 , " &
"DO : ae2 , " &
"SP_IO_SPEED :(ac23 , " & -- SP_IO_SPEED[1]
"ac22), " & -- SP_IO_SPEED[0]
"SP0_PWRDN : ae22 , " &
"SP1_PWRDN : af22 , " &
"SP2_PWRDN : ae23 , " &
"SP3_PWRDN : af23 , " &
"SP4_PWRDN : w2 , " &
"SP5_PWRDN : w3 , " &
"SP6_PWRDN : w5 , " &
"SP7_PWRDN : w6 , " &
"SP8_PWRDN : y1 , " &
"SP9_PWRDN : y3 , " &
"SP10_PWRDN : y4 , " &
"SP11_PWRDN : y6 , " &
"SP12_PWRDN : aa2 , " &
"SP13_PWRDN : aa3 , " &
"SP14_PWRDN : w7 , " &
"SP15_PWRDN : y8 , " &
"SP0_MODESEL : ad22 , " &
"SP2_MODESEL : ad23 , " &
"SP4_MODESEL : ab1 , " &
"SP6_MODESEL : ab3 , " &
"SP8_MODESEL : ab4 , " &
"SP10_MODESEL : ac3 , " &
"SP12_MODESEL : af3 , " &
"SP14_MODESEL : af4 , " &
"DEV_ID_SEL : w20 , " &
"SP_RX_SWAP : y19 , " &
"SP_TX_SWAP : y20 , " &
"SPY_CLK_0 : ad1 , " &
"SPY_CLK_1 : ad4 , " &
"VDD_IO :(v2 , " & -- VDD_IO[11]
"v6 , " & -- VDD_IO[10]
"w4 , " & -- VDD_IO[9]
"y2 , " & -- VDD_IO[8]
"y7 , " & -- VDD_IO[7]
"aa4 , " & -- VDD_IO[6]
"ab2 , " & -- VDD_IO[5]
"ac4 , " & -- VDD_IO[4]
"ad2 , " & -- VDD_IO[3]
"ae4 , " & -- VDD_IO[2]
"ac25 , " & -- VDD_IO[1]
"ae25 ), " & -- VDD_IO[0]
"VSS_IO :(v3 , " & -- VSS_IO[12]
"v5 , " & -- VSS_IO[11]
"w1 , " & -- VSS_IO[10]
"w8 , " & -- VSS_IO[9]
"w19 , " & -- VSS_IO[8]
"Y5 , " & -- VSS_IO[7]
"aa1 , " & -- VSS_IO[6]
"ac1 , " & -- VSS_IO[5]
"ae1 , " & -- VSS_IO[4]
"ad24 , " & -- VSS_IO[3]
"ad21 , " & -- VSS_IO[2]
"af21 , " & -- VSS_IO[1]
"af24 ), " & -- VSS_IO[0]
"VSS :(a2 , " & -- VSS[90]
"a3 , " & -- VSS[89]
"a4 , " & -- VSS[88]
"a5 , " & -- VSS[87]
"a6 , " & -- VSS[86]
"a23 , " & -- VSS[85]
"a24 , " & -- VSS[84]
"a25 , " & -- VSS[83]
"a26 , " & -- VSS[82]
"b23 , " & -- VSS[81]
"b26 , " & -- VSS[80]
"c23 , " & -- VSS[79]
"c25 , " & -- VSS[78]
"d23 , " & -- VSS[77]
"d26 , " & -- VSS[76]
"e23 , " & -- VSS[75]
"e24 , " & -- VSS[74]
"e25 , " & -- VSS[73]
"e26 , " & -- VSS[72]
"f23 , " & -- VSS[71]
"f24 , " & -- VSS[70]
"f25 , " & -- VSS[69]
"f26 , " & -- VSS[68]
"g7 , " & -- VSS[67]
"g9 , " & -- VSS[66]
"g11 , " & -- VSS[65]
"g13 , " & -- VSS[64]
"g15 , " & -- VSS[63]
"g17 , " & -- VSS[62]
"g19 , " & -- VSS[61]
"h8 , " & -- VSS[60]
"h9 , " & -- VSS[59]
"h10 , " & -- VSS[58]
"h11 , " & -- VSS[57]
"h12 , " & -- VSS[56]
"h13 , " & -- VSS[55]
"h14 , " & -- VSS[54]
"h15 , " & -- VSS[53]
"h16 , " & -- VSS[52]
"h17 , " & -- VSS[51]
"h18 , " & -- VSS[50]
"h19 , " & -- VSS[49]
"j7 , " & -- VSS[48]
"j8 , " & -- VSS[47]
"j19 , " & -- VSS[46]
"j20 , " & -- VSS[45]
"k8 , " & -- VSS[44]
"k19 , " & -- VSS[43]
"l7 , " & -- VSS[42]
"l8 , " & -- VSS[41]
"l19 , " & -- VSS[40]
"l20 , " & -- VSS[39]
"m8 , " & -- VSS[38]
"m19 , " & -- VSS[37]
"n7 , " & -- VSS[36]
"n8 , " & -- VSS[35]
"n19 , " & -- VSS[34]
"n20 , " & -- VSS[33]
"p8 , " & -- VSS[32]
"p19 , " & -- VSS[31]
"r7 , " & -- VSS[30]
"r8 , " & -- VSS[29]
"r19 , " & -- VSS[28]
"r20 , " & -- VSS[27]
"t8 , " & -- VSS[26]
"t19 , " & -- VSS[25]
"u7 , " & -- VSS[24]
"u8 , " & -- VSS[23]
"u19 , " & -- VSS[22]
"u20 , " & -- VSS[21]
"v1 , " & -- VSS[20]
"v4 , " & -- VSS[19]
"v8 , " & -- VSS[18]
"v19 , " & -- VSS[17]
"w9 , " & -- VSS[16]
"w10 , " & -- VSS[15]
"w11 , " & -- VSS[14]
"w12 , " & -- VSS[13]
"w13 , " & -- VSS[12]
"w14 , " & -- VSS[11]
"w15 , " & -- VSS[10]
"w16 , " & -- VSS[9]
"w17 , " & -- VSS[8]
"w18 , " & -- VSS[7]
"y10 , " & -- VSS[6]
"y12 , " & -- VSS[5]
"y14 , " & -- VSS[4]
"y16 , " & -- VSS[3]
"y18 , " & -- VSS[2]
"ac21 , " & -- VSS[1]
"ae21 ), " & -- VSS[0]
"VDD :(j10 , " & -- VDD[49]
"j12 , " & -- VDD[48]
"j14 , " & -- VDD[47]
"j16 , " & -- VDD[46]
"j18 , " & -- VDD[45]
"k11 , " & -- VDD[44]
"k13 , " & -- VDD[43]
"k15 , " & -- VDD[42]
"k17 , " & -- VDD[41]
"v9 , " & -- VDD[40]
"l10 , " & -- VDD[39]
"l12 , " & -- VDD[38]
"l14 , " & -- VDD[37]
"l16 , " & -- VDD[36]
"l18 , " & -- VDD[35]
"m11 , " & -- VDD[34]
"m13 , " & -- VDD[33]
"m15 , " & -- VDD[32]
"m17 , " & -- VDD[31]
"v11 , " & -- VDD[30]
"n10 , " & -- VDD[29]
"n12 , " & -- VDD[28]
"n14 , " & -- VDD[27]
"n16 , " & -- VDD[26]
"n18 , " & -- VDD[25]
"p11 , " & -- VDD[24]
"p13 , " & -- VDD[23]
"p15 , " & -- VDD[22]
"p17 , " & -- VDD[21]
"v13 , " & -- VDD[20]
"r10 , " & -- VDD[19]
"r12 , " & -- VDD[18]
"r14 , " & -- VDD[17]
"r16 , " & -- VDD[16]
"r18 , " & -- VDD[15]
"t11 , " & -- VDD[14]
"t13 , " & -- VDD[13]
"t15 , " & -- VDD[12]
"t17 , " & -- VDD[11]
"v15 , " & -- VDD[10]
"u10 , " & -- VDD[9]
"u12 , " & -- VDD[8]
"u14 , " & -- VDD[7]
"u16 , " & -- VDD[6]
"u18 , " & -- VDD[5]
"v17 , " & -- VDD[4]
"k9 , " & -- VDD[3]
"t9 , " & -- VDD[2]
"m9 , " & -- VDD[1]
"p9 ), " & -- VDD[0]
"SP_VDD :(h7 , " & -- SP_VDD[25]
"k7 , " & -- SP_VDD[24]
"m7 , " & -- SP_VDD[23]
"p7 , " & -- SP_VDD[22]
"t7 , " & -- SP_VDD[21]
"v7 , " & -- SP_VDD[20]
"y9 , " & -- SP_VDD[19]
"y11 , " & -- SP_VDD[18]
"y13 , " & -- SP_VDD[17]
"y15 , " & -- SP_VDD[16]
"y17 , " & -- SP_VDD[15]
"g8 , " & -- SP_VDD[14]
"g10 , " & -- SP_VDD[13]
"g12 , " & -- SP_VDD[12]
"g14 , " & -- SP_VDD[11]
"g16 , " & -- SP_VDD[10]
"g18 , " & -- SP_VDD[9]
"g20 , " & -- SP_VDD[8]
"h20 , " & -- SP_VDD[7]
"k20 , " & -- SP_VDD[6]
"m20 , " & -- SP_VDD[5]
"p20 , " & -- SP_VDD[4]
"t20 , " & -- SP_VDD[3]
"v20 , " & -- SP_VDD[2]
"c24 , " & -- SP_VDD[1]
"c26 ) " ; -- SP_VDD[0]
attribute TAP_SCAN_RESET of TRST_B : signal is true;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (1.0000000000000000000e+07, BOTH);
attribute INSTRUCTION_LENGTH of Tsi568: entity is 55;
attribute INSTRUCTION_OPCODE of Tsi568: entity is
"IDCODE (1111111111111111111111111111111111111111111111111111110)," &
"BYPASS (0000000000000000000000000000000000000000000000000000000," &
" 1111111111111111111111111111111111111111111111111111111)," &
"EXTEST (1111111111111111111111111111111111111111111111111101000)," &
"SAMPLE (1111111111111111111111111111111111111111111111111111000)," &
"PRELOAD (1111111111111111111111111111111111111111111111111111000)," &
"HIGHZ (1111111111111111111111111111111111111111111111111001111)," &
"CLAMP (1111111111111111111111111111111111111111111111111101111) " ;
attribute INSTRUCTION_CAPTURE of Tsi568: entity is
"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01";
attribute IDCODE_REGISTER of Tsi568: entity is
"0010" & -- version
"0000010101100000" & -- part number
"00010110011" & -- manufacturer's identity
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of Tsi568: entity is
"BOUNDARY ( SAMPLE, PRELOAD )," &
"BYPASS ( HIGHZ, CLAMP, BYPASS ) " ;
--Boundary scan definition
attribute BOUNDARY_LENGTH of Tsi568: entity is 49;
attribute BOUNDARY_REGISTER of Tsi568: entity is
-- num cell port function safe [ccell disval rslt]
" 48 (BC_4 , P_CLK , clock , X ) ,"&
" 47 (BC_2 , * , control , 0 ) ,"&
" 46 (LV_BC_7 , I2C_SCLK , bidir , X , 47 , 0 , Z ),"&
" 45 (BC_2 , * , control , 0 ) ,"&
" 44 (LV_BC_7 , I2C_SD , bidir , X , 45 , 0 , Z ),"&
" 43 (BC_2 , * , control , 0 ) ,"&
" 42 (LV_BC_7 , I2C_DISABLE , bidir , X , 43 , 0 , Z ),"&
" 41 (BC_2 , * , control , 0 ) ,"&
" 40 (LV_BC_7 , INT_B , bidir , X , 41 , 0 , Z ),"&
" 39 (BC_2 , * , control , 0 ) ,"&
" 38 (LV_BC_7 , SW_RST_B , bidir , X , 39 , 0 , Z ),"&
" 37 (BC_2 , DI , input , X ) ,"&
" 36 (BC_2 , * , control , 0 ) ,"&
" 35 (BC_2 , DO , output3 , X , 36 , 0 , Z ),"&
" 34 (BC_2 , * , control , 0 ) ,"&
" 33 (LV_BC_7 , SP_IO_SPEED(1) , bidir , X , 34 , 0 , Z ),"&
" 32 (LV_BC_7 , SP_IO_SPEED(0) , bidir , X , 34 , 0 , Z ),"&
" 31 (LV_BC_7 , SP0_PWRDN , bidir , X , 34 , 0 , Z ),"&
" 30 (LV_BC_7 , SP1_PWRDN , bidir , X , 34 , 0 , Z ),"&
" 29 (BC_2 , * , control , 0 ) ,"&
" 28 (LV_BC_7 , SP2_PWRDN , bidir , X , 29 , 0 , Z ),"&
" 27 (LV_BC_7 , SP3_PWRDN , bidir , X , 29 , 0 , Z ),"&
" 26 (BC_2 , * , control , 0 ) ,"&
" 25 (LV_BC_7 , SP4_PWRDN , bidir , X , 26 , 0 , Z ),"&
" 24 (LV_BC_7 , SP5_PWRDN , bidir , X , 26 , 0 , Z ),"&
" 23 (LV_BC_7 , SP6_PWRDN , bidir , X , 26 , 0 , Z ),"&
" 22 (LV_BC_7 , SP7_PWRDN , bidir , X , 26 , 0 , Z ),"&
" 21 (BC_2 , * , control , 0 ) ,"&
" 20 (LV_BC_7 , SP8_PWRDN , bidir , X , 21 , 0 , Z ),"&
" 19 (LV_BC_7 , SP9_PWRDN , bidir , X , 21 , 0 , Z ),"&
" 18 (LV_BC_7 , SP10_PWRDN , bidir , X , 21 , 0 , Z ),"&
" 17 (LV_BC_7 , SP11_PWRDN , bidir , X , 21 , 0 , Z ),"&
" 16 (BC_2 , * , control , 0 ) ,"&
" 15 (LV_BC_7 , SP12_PWRDN , bidir , X , 16 , 0 , Z ),"&
" 14 (LV_BC_7 , SP13_PWRDN , bidir , X , 16 , 0 , Z ),"&
" 13 (LV_BC_7 , SP14_PWRDN , bidir , X , 16 , 0 , Z ),"&
" 12 (LV_BC_7 , SP15_PWRDN , bidir , X , 16 , 0 , Z ),"&
" 11 (LV_BC_7 , SP0_MODESEL , bidir , X , 29 , 0 , Z ),"&
" 10 (LV_BC_7 , SP2_MODESEL , bidir , X , 29 , 0 , Z ),"&
" 9 (BC_2 , * , control , 0 ) ,"&
" 8 (LV_BC_7 , SP4_MODESEL , bidir , X , 9 , 0 , Z ),"&
" 7 (LV_BC_7 , SP6_MODESEL , bidir , X , 9 , 0 , Z ),"&
" 6 (LV_BC_7 , SP8_MODESEL , bidir , X , 9 , 0 , Z ),"&
" 5 (LV_BC_7 , SP10_MODESEL , bidir , X , 9 , 0 , Z ),"&
" 4 (BC_2 , * , control , 0 ) ,"&
" 3 (LV_BC_7 , SP12_MODESEL , bidir , X , 4 , 0 , Z ),"&
" 2 (LV_BC_7 , SP14_MODESEL , bidir , X , 4 , 0 , Z ),"&
" 1 (LV_BC_7 , SP_RX_SWAP , bidir , X , 4 , 0 , Z ),"&
" 0 (LV_BC_7 , SP_TX_SWAP , bidir , X , 4 , 0 , Z ) ";
end Tsi568;
--
-- package LVS_BSCAN_CELLS is
-- use STD_1149_1_2001.all;
-- constant LV_BC_7: CELL_INFO;
--
-- end LVS_BSCAN_CELLS;
-- package body LVS_BSCAN_CELLS is
-- use STD_1149_1_2001.all;
-- constant LV_BC_7: CELL_INFO :=
-- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PO),
-- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
-- (BIDIR_IN, INTEST, X), (BIDIR_OUT, INTEST, PI));
--
-- end LVS_BSCAN_CELLS;
--