-- **********************************************************************
--
-- FILE : zl50114gag.bsd
-- generated by Cz.P. as zl50114 on Tue Mar 15 12:26 EDT 2005
-- using p.jtag.bsd rev 3.3 July 18, 2003
--
-- BSDL description for top level entity zl50114
-- Device : ZL50114 Circuit Emulation Services over Packets (CESoP)
-- Package : 552-balls PBGA (35mmx35mm)
--
-- Number of BSC cells: 476
--
-- **********************************************************************
-- Modification History:
-- rev 1.1: Tue Mar 15 12:26 EDT 2005
-- Fixed typo error for the SAMPLE instruction opcode.
-- rev 1.0: Tue Sep 7 13:03:12 EDT 2004
-- Initial release: Mon Mar 24 12:05:38 EST 2003
-- ********************************************************************
--
-- IMPORTANT NOTICE
--
-- This information is for modeling purposes only, and is not guaranteed.
--
-- This information is provided "as is" without warranty of any kind.
-- It may contain technical inaccuracies or typographical errors.
--
-- ZARLINK and ZL50114 are trademarks of ZARLINK Semiconductor. ZARLINK
-- products, marketed under trademarks, are protected under numerous US
-- and foreign patents and pending applications, maskwork rights, and
-- copyrights.
--
-- ZARLINK reserves the right to make changes to any products and
-- services at any time without notice. ZARLINK assumes no
-- responsibility or liability arising out of the application or use of
-- any information, product, or service described herein except as
-- expressly agreed to in writing by ZARLINK Corporation. ZARLINK
-- customers are advised to obtain the latest version of device
-- specifications before relying on any published information and before
-- placing orders for products or services.
--
--
-- ********************************************************************
--
-- SPECIAL NOTES
--
-- 1. All instruction opcodes other than those defined in this file
-- should be considered PRIVATE.
--
-- 2. For normal operation the following balls should be tied to GROUND:
-- AF6, AB9, AC8, AD9, AF8, R5, T4, AE8
-- corresponding to the signals: TEST_MODE(0 to 2), IC_GND(1 to 5)
--
-- 3. Balls named NC_OPEN(1:3) {R6, AC16, AE17} are Internal
-- Connects, and they should be left open for normal operation.
--
-- 4. Ball AF16, signal IC_VDD is Internal Connect, and it should be
-- tied to VDD_IO for normal operation.
--
-- 5. Linkage bit_vector NC(0 to 147) balls are No Connects.
--
-- ********************************************************************
entity zl50114 is
generic(PHYSICAL_PIN_MAP : string := "PBGA_PACKAGE");
port (
CPU_ADDR: in bit_vector (2 to 23);
CPU_CLK: in bit;
CPU_CS: in bit;
CPU_DATA: inout bit_vector (0 to 31);
CPU_DREQ0: inout bit;
CPU_DREQ1: inout bit;
CPU_IREQ0: inout bit;
CPU_IREQ1: inout bit;
CPU_OE: in bit;
CPU_SDACK1: in bit;
CPU_SDACK2: in bit;
CPU_TA: inout bit;
CPU_TS_ALE: in bit;
CPU_WE: in bit;
GPIO: inout bit_vector (0 to 15);
IC_GND: linkage bit_vector (1 to 5);
IC_VDD: linkage bit;
JTAG_TCK: in bit;
JTAG_TDI: in bit;
JTAG_TDO: out bit;
JTAG_TMS: in bit;
JTAG_TRST: in bit;
M0_ACTIVE_LED: out bit;
M0_COL: in bit;
M0_CRS: in bit;
M0_GIGABIT_LED: out bit;
M0_GTX_CLK: out bit;
M0_LINKUP_LED: out bit;
M0_RBC0: in bit;
M0_RBC1: in bit;
M0_REFCLK: in bit;
M0_RXCLK: in bit;
M0_RXD: in bit_vector (0 to 7);
M0_RXDV: in bit;
M0_RXER: in bit;
M0_TXCLK: in bit;
M0_TXD: out bit_vector (0 to 7);
M0_TXEN: out bit;
M0_TXER: out bit;
M1_ACTIVE_LED: out bit;
M1_COL: in bit;
M1_CRS: in bit;
M1_GIGABIT_LED: out bit;
M1_GTX_CLK: out bit;
M1_LINKUP_LED: out bit;
M1_RBC0: in bit;
M1_RBC1: in bit;
M1_REFCLK: in bit;
M1_RXCLK: in bit;
M1_RXD: in bit_vector (0 to 7);
M1_RXDV: in bit;
M1_RXER: in bit;
M1_TXCLK: in bit;
M1_TXD: out bit_vector (0 to 7);
M1_TXEN: out bit;
M1_TXER: out bit;
M_MDC: out bit;
M_MDIO: inout bit;
NC: linkage bit_vector (0 to 147);
NC_OPEN: linkage bit_vector (1 to 3);
PLL_PRI: out bit;
PLL_SEC: out bit;
RAM_ADDR: out bit_vector (0 to 19);
RAM_BW_A: inout bit;
RAM_BW_B: inout bit;
RAM_BW_C: inout bit;
RAM_BW_D: inout bit;
RAM_BW_E: inout bit;
RAM_BW_F: inout bit;
RAM_BW_G: inout bit;
RAM_BW_H: inout bit;
RAM_DATA: inout bit_vector (0 to 63);
RAM_PARITY: inout bit_vector (0 to 7);
RAM_RW: inout bit;
SYSTEM_CLK: in bit;
SYSTEM_DEBUG: in bit;
SYSTEM_RST: linkage bit;
TDM_CLKI: in bit_vector (0 to 3);
TDM_CLKI_REF: in bit;
TDM_CLKIP: in bit;
TDM_CLKIS: in bit;
TDM_CLKO: out bit_vector (0 to 3);
TDM_CLKO_REF: out bit;
TDM_FRMI_REF: in bit;
TDM_FRMO_REF: out bit;
TDM_STI: in bit_vector (0 to 3);
TDM_STO: out bit_vector (0 to 3);
TEST_MODE: linkage bit_vector (0 to 2);
A1VDD: linkage bit;
GND: linkage bit_vector (0 to 57);
VDD_CORE: linkage bit_vector (0 to 17);
VDD_IO: linkage bit_vector (0 to 35)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of zl50114 : entity is
"STD_1149_1_1993";
attribute PIN_MAP of zl50114 : entity is PHYSICAL_PIN_MAP;
constant PBGA_PACKAGE : PIN_MAP_STRING :=
"CPU_ADDR :(AA11 , " & -- CPU_ADDR[2]
"AE9 , " & -- CPU_ADDR[3]
"AC10 , " & -- CPU_ADDR[4]
"AF9 , " & -- CPU_ADDR[5]
"AB11 , " & -- CPU_ADDR[6]
"AD10 , " & -- CPU_ADDR[7]
"AE10 , " & -- CPU_ADDR[8]
"AC11 , " & -- CPU_ADDR[9]
"AF10 , " & -- CPU_ADDR[10]
"AD11 , " & -- CPU_ADDR[11]
"AA12 , " & -- CPU_ADDR[12]
"AE11 , " & -- CPU_ADDR[13]
"AB12 , " & -- CPU_ADDR[14]
"AF11 , " & -- CPU_ADDR[15]
"AC12 , " & -- CPU_ADDR[16]
"AD12 , " & -- CPU_ADDR[17]
"AE12 , " & -- CPU_ADDR[18]
"AF12 , " & -- CPU_ADDR[19]
"AE13 , " & -- CPU_ADDR[20]
"AD13 , " & -- CPU_ADDR[21]
"AC13 , " & -- CPU_ADDR[22]
"AB13 ), " & -- CPU_ADDR[23]
"CPU_CLK : AC14 , " &
"CPU_CS : AF14 , " &
"CPU_DATA :(AF18 , " & -- CPU_DATA[0]
"AB15 , " & -- CPU_DATA[1]
"AF20 , " & -- CPU_DATA[2]
"AD17 , " & -- CPU_DATA[3]
"AE18 , " & -- CPU_DATA[4]
"AF19 , " & -- CPU_DATA[5]
"AD18 , " & -- CPU_DATA[6]
"AB16 , " & -- CPU_DATA[7]
"AA15 , " & -- CPU_DATA[8]
"AE19 , " & -- CPU_DATA[9]
"AC17 , " & -- CPU_DATA[10]
"AF21 , " & -- CPU_DATA[11]
"AB17 , " & -- CPU_DATA[12]
"AE20 , " & -- CPU_DATA[13]
"AD19 , " & -- CPU_DATA[14]
"AA16 , " & -- CPU_DATA[15]
"AC18 , " & -- CPU_DATA[16]
"AF22 , " & -- CPU_DATA[17]
"AE21 , " & -- CPU_DATA[18]
"AF23 , " & -- CPU_DATA[19]
"AD20 , " & -- CPU_DATA[20]
"AC19 , " & -- CPU_DATA[21]
"AB18 , " & -- CPU_DATA[22]
"AA17 , " & -- CPU_DATA[23]
"AD21 , " & -- CPU_DATA[24]
"AE22 , " & -- CPU_DATA[25]
"AF24 , " & -- CPU_DATA[26]
"AC20 , " & -- CPU_DATA[27]
"AE23 , " & -- CPU_DATA[28]
"AD22 , " & -- CPU_DATA[29]
"AB19 , " & -- CPU_DATA[30]
"AF25 ), " & -- CPU_DATA[31]
"CPU_DREQ0 : AC15 , " &
"CPU_DREQ1 : AE16 , " &
"CPU_IREQ0 : AF17 , " &
"CPU_IREQ1 : AD16 , " &
"CPU_OE : AE14 , " &
"CPU_SDACK1 : AF15 , " &
"CPU_SDACK2 : AD15 , " &
"CPU_TA : AB14 , " &
"CPU_TS_ALE : AE15 , " &
"CPU_WE : AD14 , " &
"GPIO :(W3 , " & -- GPIO[0]
"AA1 , " & -- GPIO[1]
"V5 , " & -- GPIO[2]
"W4 , " & -- GPIO[3]
"Y2 , " & -- GPIO[4]
"AB1 , " & -- GPIO[5]
"Y3 , " & -- GPIO[6]
"AA2 , " & -- GPIO[7]
"AA3 , " & -- GPIO[8]
"W5 , " & -- GPIO[9]
"Y4 , " & -- GPIO[10]
"AB2 , " & -- GPIO[11]
"AC1 , " & -- GPIO[12]
"AC2 , " & -- GPIO[13]
"AB3 , " & -- GPIO[14]
"AA4 ), " & -- GPIO[15]
"IC_GND :(AD9 , " & -- IC_GND[1]
"AF8 , " & -- IC_GND[2]
"R5 , " & -- IC_GND[3]
"T4 , " & -- IC_GND[4]
"AE8 ), " & -- IC_GND[5]
"IC_VDD : AF16 , " &
"JTAG_TCK : AD8 , " &
"JTAG_TDI : AF7 , " &
"JTAG_TDO : AC9 , " &
"JTAG_TMS : AA10 , " &
"JTAG_TRST : AE7 , " &
"M0_ACTIVE_LED : AC26 , " &
"M0_COL : Y25 , " &
"M0_CRS : U25 , " &
"M0_GIGABIT_LED : H22 , " &
"M0_GTX_CLK : U21 , " &
"M0_LINKUP_LED : G24 , " &
"M0_RBC0 : Y24 , " &
"M0_RBC1 : AA25 , " &
"M0_REFCLK : AA24 , " &
"M0_RXCLK : AB22 , " &
"M0_RXD :(AA26 , " & -- M0_RXD[0]
"Y26 , " & -- M0_RXD[1]
"U22 , " & -- M0_RXD[2]
"W26 , " & -- M0_RXD[3]
"V24 , " & -- M0_RXD[4]
"U23 , " & -- M0_RXD[5]
"W24 , " & -- M0_RXD[6]
"W25 ), " & -- M0_RXD[7]
"M0_RXDV : V25 , " &
"M0_RXER : V26 , " &
"M0_TXCLK : U24 , " &
"M0_TXD :(AA22 , " & -- M0_TXD[0]
"Y22 , " & -- M0_TXD[1]
"W21 , " & -- M0_TXD[2]
"AA23 , " & -- M0_TXD[3]
"Y23 , " & -- M0_TXD[4]
"W22 , " & -- M0_TXD[5]
"W23 , " & -- M0_TXD[6]
"V21 ), " & -- M0_TXD[7]
"M0_TXEN : V23 , " &
"M0_TXER : V22 , " &
"M1_ACTIVE_LED : AB25 , " &
"M1_COL : R25 , " &
"M1_CRS : L23 , " &
"M1_GIGABIT_LED : G25 , " &
"M1_GTX_CLK : N21 , " &
"M1_LINKUP_LED : G23 , " &
"M1_RBC0 : U26 , " &
"M1_RBC1 : T25 , " &
"M1_REFCLK : M22 , " &
"M1_RXCLK : M23 , " &
"M1_RXD :(T26 , " & -- M1_RXD[0]
"R26 , " & -- M1_RXD[1]
"N24 , " & -- M1_RXD[2]
"N25 , " & -- M1_RXD[3]
"P25 , " & -- M1_RXD[4]
"M24 , " & -- M1_RXD[5]
"P26 , " & -- M1_RXD[6]
"M25 ), " & -- M1_RXD[7]
"M1_RXDV : M26 , " &
"M1_RXER : L21 , " &
"M1_TXCLK : L22 , " &
"M1_TXD :(R21 , " & -- M1_TXD[0]
"T22 , " & -- M1_TXD[1]
"P21 , " & -- M1_TXD[2]
"R22 , " & -- M1_TXD[3]
"T23 , " & -- M1_TXD[4]
"R23 , " & -- M1_TXD[5]
"P22 , " & -- M1_TXD[6]
"R24 ), " & -- M1_TXD[7]
"M1_TXEN : P23 , " &
"M1_TXER : N23 , " &
"M_MDC : H23 , " &
"M_MDIO : G26 , " &
"NC :(A10 , " & -- NC[0]
"A11 , " & -- NC[1]
"A12 , " & -- NC[2]
"A14 , " & -- NC[3]
"A15 , " & -- NC[4]
"A16 , " & -- NC[5]
"A17 , " & -- NC[6]
"A18 , " & -- NC[7]
"A19 , " & -- NC[8]
"A20 , " & -- NC[9]
"A21 , " & -- NC[10]
"A22 , " & -- NC[11]
"A23 , " & -- NC[12]
"A24 , " & -- NC[13]
"A25 , " & -- NC[14]
"A4 , " & -- NC[15]
"A5 , " & -- NC[16]
"A6 , " & -- NC[17]
"A7 , " & -- NC[18]
"A8 , " & -- NC[19]
"A9 , " & -- NC[20]
"AA19 , " & -- NC[21]
"AA20 , " & -- NC[22]
"AB20 , " & -- NC[23]
"AB21 , " & -- NC[24]
"AB23 , " & -- NC[25]
"AB24 , " & -- NC[26]
"AB26 , " & -- NC[27]
"AC21 , " & -- NC[28]
"AC22 , " & -- NC[29]
"AC23 , " & -- NC[30]
"AC24 , " & -- NC[31]
"AC25 , " & -- NC[32]
"AD23 , " & -- NC[33]
"AD24 , " & -- NC[34]
"AD25 , " & -- NC[35]
"AD26 , " & -- NC[36]
"AE24 , " & -- NC[37]
"AE25 , " & -- NC[38]
"AE26 , " & -- NC[39]
"B10 , " & -- NC[40]
"B11 , " & -- NC[41]
"B12 , " & -- NC[42]
"B13 , " & -- NC[43]
"B14 , " & -- NC[44]
"B15 , " & -- NC[45]
"B16 , " & -- NC[46]
"B17 , " & -- NC[47]
"B18 , " & -- NC[48]
"B19 , " & -- NC[49]
"B20 , " & -- NC[50]
"B21 , " & -- NC[51]
"B22 , " & -- NC[52]
"B23 , " & -- NC[53]
"B24 , " & -- NC[54]
"B25 , " & -- NC[55]
"B26 , " & -- NC[56]
"B5 , " & -- NC[57]
"B6 , " & -- NC[58]
"B7 , " & -- NC[59]
"B8 , " & -- NC[60]
"B9 , " & -- NC[61]
"C10 , " & -- NC[62]
"C11 , " & -- NC[63]
"C12 , " & -- NC[64]
"C13 , " & -- NC[65]
"C14 , " & -- NC[66]
"C15 , " & -- NC[67]
"C16 , " & -- NC[68]
"C17 , " & -- NC[69]
"C18 , " & -- NC[70]
"C19 , " & -- NC[71]
"C20 , " & -- NC[72]
"C21 , " & -- NC[73]
"C22 , " & -- NC[74]
"C23 , " & -- NC[75]
"C24 , " & -- NC[76]
"C25 , " & -- NC[77]
"C26 , " & -- NC[78]
"C7 , " & -- NC[79]
"C8 , " & -- NC[80]
"C9 , " & -- NC[81]
"D10 , " & -- NC[82]
"D11 , " & -- NC[83]
"D12 , " & -- NC[84]
"D13 , " & -- NC[85]
"D14 , " & -- NC[86]
"D15 , " & -- NC[87]
"D16 , " & -- NC[88]
"D17 , " & -- NC[89]
"D18 , " & -- NC[90]
"D19 , " & -- NC[91]
"D20 , " & -- NC[92]
"D21 , " & -- NC[93]
"D22 , " & -- NC[94]
"D23 , " & -- NC[95]
"D24 , " & -- NC[96]
"D25 , " & -- NC[97]
"D26 , " & -- NC[98]
"D8 , " & -- NC[99]
"D9 , " & -- NC[100]
"E10 , " & -- NC[101]
"E11 , " & -- NC[102]
"E12 , " & -- NC[103]
"E13 , " & -- NC[104]
"E14 , " & -- NC[105]
"E15 , " & -- NC[106]
"E16 , " & -- NC[107]
"E17 , " & -- NC[108]
"E18 , " & -- NC[109]
"E19 , " & -- NC[110]
"E20 , " & -- NC[111]
"E21 , " & -- NC[112]
"E23 , " & -- NC[113]
"E24 , " & -- NC[114]
"E25 , " & -- NC[115]
"E26 , " & -- NC[116]
"E8 , " & -- NC[117]
"F11 , " & -- NC[118]
"F13 , " & -- NC[119]
"F14 , " & -- NC[120]
"F16 , " & -- NC[121]
"F17 , " & -- NC[122]
"F18 , " & -- NC[123]
"F19 , " & -- NC[124]
"F22 , " & -- NC[125]
"F23 , " & -- NC[126]
"F24 , " & -- NC[127]
"F25 , " & -- NC[128]
"F26 , " & -- NC[129]
"G21 , " & -- NC[130]
"G22 , " & -- NC[131]
"H24 , " & -- NC[132]
"H25 , " & -- NC[133]
"H26 , " & -- NC[134]
"J21 , " & -- NC[135]
"J22 , " & -- NC[136]
"J23 , " & -- NC[137]
"J24 , " & -- NC[138]
"J25 , " & -- NC[139]
"J26 , " & -- NC[140]
"K23 , " & -- NC[141]
"K24 , " & -- NC[142]
"K25 , " & -- NC[143]
"K26 , " & -- NC[144]
"L24 , " & -- NC[145]
"L25 , " & -- NC[146]
"L26 ), " & -- NC[147]
"NC_OPEN :(R6 , " & -- NC_OPEN[1]
"AC16 , " & -- NC_OPEN[2]
"AE17 ), " & -- NC_OPEN[3]
"PLL_PRI : U1 , " &
"PLL_SEC : V1 , " &
"RAM_ADDR :(M5 , " & -- RAM_ADDR[0]
"M6 , " & -- RAM_ADDR[1]
"M3 , " & -- RAM_ADDR[2]
"M4 , " & -- RAM_ADDR[3]
"M2 , " & -- RAM_ADDR[4]
"M1 , " & -- RAM_ADDR[5]
"N2 , " & -- RAM_ADDR[6]
"N3 , " & -- RAM_ADDR[7]
"N4 , " & -- RAM_ADDR[8]
"P1 , " & -- RAM_ADDR[9]
"P2 , " & -- RAM_ADDR[10]
"P3 , " & -- RAM_ADDR[11]
"R1 , " & -- RAM_ADDR[12]
"P4 , " & -- RAM_ADDR[13]
"R2 , " & -- RAM_ADDR[14]
"R3 , " & -- RAM_ADDR[15]
"P5 , " & -- RAM_ADDR[16]
"T1 , " & -- RAM_ADDR[17]
"T2 , " & -- RAM_ADDR[18]
"R4 ), " & -- RAM_ADDR[19]
"RAM_BW_A : U2 , " &
"RAM_BW_B : T3 , " &
"RAM_BW_C : U3 , " &
"RAM_BW_D : V2 , " &
"RAM_BW_E : W1 , " &
"RAM_BW_F : V3 , " &
"RAM_BW_G : W2 , " &
"RAM_BW_H : Y1 , " &
"RAM_DATA :(D4 , " & -- RAM_DATA[0]
"D2 , " & -- RAM_DATA[1]
"E5 , " & -- RAM_DATA[2]
"D1 , " & -- RAM_DATA[3]
"E4 , " & -- RAM_DATA[4]
"E3 , " & -- RAM_DATA[5]
"F4 , " & -- RAM_DATA[6]
"F5 , " & -- RAM_DATA[7]
"G6 , " & -- RAM_DATA[8]
"E2 , " & -- RAM_DATA[9]
"E1 , " & -- RAM_DATA[10]
"G5 , " & -- RAM_DATA[11]
"F3 , " & -- RAM_DATA[12]
"F2 , " & -- RAM_DATA[13]
"G4 , " & -- RAM_DATA[14]
"F1 , " & -- RAM_DATA[15]
"G3 , " & -- RAM_DATA[16]
"H5 , " & -- RAM_DATA[17]
"G2 , " & -- RAM_DATA[18]
"H4 , " & -- RAM_DATA[19]
"J6 , " & -- RAM_DATA[20]
"G1 , " & -- RAM_DATA[21]
"J5 , " & -- RAM_DATA[22]
"H3 , " & -- RAM_DATA[23]
"H2 , " & -- RAM_DATA[24]
"H1 , " & -- RAM_DATA[25]
"J4 , " & -- RAM_DATA[26]
"J3 , " & -- RAM_DATA[27]
"J2 , " & -- RAM_DATA[28]
"J1 , " & -- RAM_DATA[29]
"K4 , " & -- RAM_DATA[30]
"K3 , " & -- RAM_DATA[31]
"Y5 , " & -- RAM_DATA[32]
"W6 , " & -- RAM_DATA[33]
"AD1 , " & -- RAM_DATA[34]
"AE1 , " & -- RAM_DATA[35]
"AD2 , " & -- RAM_DATA[36]
"AC3 , " & -- RAM_DATA[37]
"AB4 , " & -- RAM_DATA[38]
"AA5 , " & -- RAM_DATA[39]
"AE2 , " & -- RAM_DATA[40]
"AD3 , " & -- RAM_DATA[41]
"AC4 , " & -- RAM_DATA[42]
"AB5 , " & -- RAM_DATA[43]
"AB6 , " & -- RAM_DATA[44]
"AA7 , " & -- RAM_DATA[45]
"AC5 , " & -- RAM_DATA[46]
"AD4 , " & -- RAM_DATA[47]
"AE3 , " & -- RAM_DATA[48]
"AC6 , " & -- RAM_DATA[49]
"AF2 , " & -- RAM_DATA[50]
"AB7 , " & -- RAM_DATA[51]
"AA8 , " & -- RAM_DATA[52]
"AD5 , " & -- RAM_DATA[53]
"AE4 , " & -- RAM_DATA[54]
"AF3 , " & -- RAM_DATA[55]
"AF4 , " & -- RAM_DATA[56]
"AE5 , " & -- RAM_DATA[57]
"AD6 , " & -- RAM_DATA[58]
"AC7 , " & -- RAM_DATA[59]
"AB8 , " & -- RAM_DATA[60]
"AF5 , " & -- RAM_DATA[61]
"AE6 , " & -- RAM_DATA[62]
"AD7 ), " & -- RAM_DATA[63]
"RAM_PARITY :(K2 , " & -- RAM_PARITY[0]
"K1 , " & -- RAM_PARITY[1]
"L6 , " & -- RAM_PARITY[2]
"L5 , " & -- RAM_PARITY[3]
"L4 , " & -- RAM_PARITY[4]
"L3 , " & -- RAM_PARITY[5]
"L2 , " & -- RAM_PARITY[6]
"L1 ), " & -- RAM_PARITY[7]
"RAM_RW : U4 , " &
"SYSTEM_CLK : U6 , " &
"SYSTEM_DEBUG : U5 , " &
"SYSTEM_RST : V4 , " &
"TDM_CLKI :(E7 , " & -- TDM_CLKI[0]
"D6 , " & -- TDM_CLKI[1]
"F10 , " & -- TDM_CLKI[2]
"B4 ), " & -- TDM_CLKI[3]
"TDM_CLKI_REF : C3 , " &
"TDM_CLKIP : C1 , " &
"TDM_CLKIS : D3 , " &
"TDM_CLKO :(F9 , " & -- TDM_CLKO[0]
"C4 , " & -- TDM_CLKO[1]
"C6 , " & -- TDM_CLKO[2]
"A3 ), " & -- TDM_CLKO[3]
"TDM_CLKO_REF : E6 , " &
"TDM_FRMI_REF : C2 , " &
"TDM_FRMO_REF : B1 , " &
"TDM_STI :(D5 , " & -- TDM_STI[0]
"E9 , " & -- TDM_STI[1]
"B3 , " & -- TDM_STI[2]
"C5 ), " & -- TDM_STI[3]
"TDM_STO :(B2 , " & -- TDM_STO[0]
"A2 , " & -- TDM_STO[1]
"F8 , " & -- TDM_STO[2]
"D7 ), " & -- TDM_STO[3]
"TEST_MODE :(AC8 , " & -- TEST_MODE[0]
"AB9 , " & -- TEST_MODE[1]
"AF6 ), " & -- TEST_MODE[2]
"A1VDD : T6 , " &
"GND :(A1, A13, A26, E22, F6, F21, K5, K22, L11, L12, L13, L14," &
"L15, L16, M11, M12, M13, M14, M15, M16, N1, N5, N11, N12," &
"N13, N14, N15, N16, N22, N26, P6, P11, P12, P13, P14, P15," &
"P16, P24, R11, R12, R13, R14, R15, R16, T5, T11, T12, T13," &
"T14, T15, T16, T24, AA6, AA21, AB10, AF1, AF13, AF26)," &
"VDD_CORE :(F7, F12, F15, F20, H6, H21, K6, K21, M21, N6, T21, V6," &
"Y6, Y21, AA9, AA13, AA14, AA18)," &
"VDD_IO :(J9, J10, J11, J12, J13, J14, J15, J16, J17, J18, K9, K18," &
"L9, L18, M9, M18, N9, N18, P9, P18, R9, R18, T9, T18," &
"U9, U18, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18)";
attribute TAP_SCAN_IN of JTAG_TDI : signal is true;
attribute TAP_SCAN_MODE of JTAG_TMS : signal is true;
attribute TAP_SCAN_OUT of JTAG_TDO : signal is true;
attribute TAP_SCAN_CLOCK of JTAG_TCK : signal is (10.0e6,BOTH);
attribute TAP_SCAN_RESET of JTAG_TRST : signal is true;
--
-- NOTE: All instruction opcodes other than those defined in this file
-- should be considered PRIVATE.
--
attribute INSTRUCTION_LENGTH of zl50114 : entity is 17;
attribute INSTRUCTION_OPCODE of zl50114 : entity is
"idcode (11111111111111110)," &
"bypass (11111111111111111)," &
"sample (11111111111111000)," &
"highz (11111111111001111)," &
"clamp (11111111111101111)," &
"extest (00000000000000000)," &
"extest (11111111111101000)";
attribute INSTRUCTION_CAPTURE of zl50114 : entity is "xxxxxxxxxxxxxxx01";
attribute IDCODE_REGISTER of zl50114 : entity is
"0000" & -- version
"1100001111000010" & -- part number
"00010100101" & -- manufacturer id
"1";
attribute REGISTER_ACCESS of zl50114 : entity is
"boundary (extest, sample)," &
"bypass (bypass, highz, clamp)," &
"device_id (idcode)" ;
attribute BOUNDARY_LENGTH of zl50114 : entity is 476;
attribute BOUNDARY_REGISTER of zl50114 : entity is
-- num cell port function safe ccel disval rslt
" 0 ( BC_7, RAM_DATA(63), bidir, X, 1, 1, Z) ," &
" 1 ( BC_2, *, control, 1) ," &
" 2 ( BC_7, RAM_DATA(62), bidir, X, 3, 1, Z) ," &
" 3 ( BC_2, *, control, 1) ," &
" 4 ( BC_7, RAM_DATA(61), bidir, X, 5, 1, Z) ," &
" 5 ( BC_2, *, control, 1) ," &
" 6 ( BC_7, RAM_DATA(60), bidir, X, 7, 1, Z) ," &
" 7 ( BC_2, *, control, 1) ," &
" 8 ( BC_7, RAM_DATA(59), bidir, X, 9, 1, Z) ," &
" 9 ( BC_2, *, control, 1) ," &
" 10 ( BC_7, RAM_DATA(58), bidir, X, 11, 1, Z) ," &
" 11 ( BC_2, *, control, 1) ," &
" 12 ( BC_7, RAM_DATA(57), bidir, X, 13, 1, Z) ," &
" 13 ( BC_2, *, control, 1) ," &
" 14 ( BC_7, RAM_DATA(56), bidir, X, 15, 1, Z) ," &
" 15 ( BC_2, *, control, 1) ," &
" 16 ( BC_7, RAM_DATA(55), bidir, X, 17, 1, Z) ," &
" 17 ( BC_2, *, control, 1) ," &
" 18 ( BC_7, RAM_DATA(54), bidir, X, 19, 1, Z) ," &
" 19 ( BC_2, *, control, 1) ," &
" 20 ( BC_7, RAM_DATA(53), bidir, X, 21, 1, Z) ," &
" 21 ( BC_2, *, control, 1) ," &
" 22 ( BC_7, RAM_DATA(52), bidir, X, 23, 1, Z) ," &
" 23 ( BC_2, *, control, 1) ," &
" 24 ( BC_7, RAM_DATA(51), bidir, X, 25, 1, Z) ," &
" 25 ( BC_2, *, control, 1) ," &
" 26 ( BC_7, RAM_DATA(50), bidir, X, 27, 1, Z) ," &
" 27 ( BC_2, *, control, 1) ," &
" 28 ( BC_7, RAM_DATA(49), bidir, X, 29, 1, Z) ," &
" 29 ( BC_2, *, control, 1) ," &
" 30 ( BC_7, RAM_DATA(48), bidir, X, 31, 1, Z) ," &
" 31 ( BC_2, *, control, 1) ," &
" 32 ( BC_7, RAM_DATA(47), bidir, X, 33, 1, Z) ," &
" 33 ( BC_2, *, control, 1) ," &
" 34 ( BC_7, RAM_DATA(46), bidir, X, 35, 1, Z) ," &
" 35 ( BC_2, *, control, 1) ," &
" 36 ( BC_7, RAM_DATA(45), bidir, X, 37, 1, Z) ," &
" 37 ( BC_2, *, control, 1) ," &
" 38 ( BC_7, RAM_DATA(44), bidir, X, 39, 1, Z) ," &
" 39 ( BC_2, *, control, 1) ," &
" 40 ( BC_7, RAM_DATA(43), bidir, X, 41, 1, Z) ," &
" 41 ( BC_2, *, control, 1) ," &
" 42 ( BC_7, RAM_DATA(42), bidir, X, 43, 1, Z) ," &
" 43 ( BC_2, *, control, 1) ," &
" 44 ( BC_7, RAM_DATA(41), bidir, X, 45, 1, Z) ," &
" 45 ( BC_2, *, control, 1) ," &
" 46 ( BC_7, RAM_DATA(40), bidir, X, 47, 1, Z) ," &
" 47 ( BC_2, *, control, 1) ," &
" 48 ( BC_7, RAM_DATA(39), bidir, X, 49, 1, Z) ," &
" 49 ( BC_2, *, control, 1) ," &
" 50 ( BC_7, RAM_DATA(38), bidir, X, 51, 1, Z) ," &
" 51 ( BC_2, *, control, 1) ," &
" 52 ( BC_7, RAM_DATA(37), bidir, X, 53, 1, Z) ," &
" 53 ( BC_2, *, control, 1) ," &
" 54 ( BC_7, RAM_DATA(36), bidir, X, 55, 1, Z) ," &
" 55 ( BC_2, *, control, 1) ," &
" 56 ( BC_7, RAM_DATA(35), bidir, X, 57, 1, Z) ," &
" 57 ( BC_2, *, control, 1) ," &
" 58 ( BC_7, RAM_DATA(34), bidir, X, 59, 1, Z) ," &
" 59 ( BC_2, *, control, 1) ," &
" 60 ( BC_7, RAM_DATA(33), bidir, X, 61, 1, Z) ," &
" 61 ( BC_2, *, control, 1) ," &
" 62 ( BC_7, RAM_DATA(32), bidir, X, 63, 1, Z) ," &
" 63 ( BC_2, *, control, 1) ," &
" 64 ( BC_7, GPIO(15), bidir, X, 65, 1, Z) ," &
" 65 ( BC_2, *, control, 1) ," &
" 66 ( BC_7, GPIO(14), bidir, X, 67, 1, Z) ," &
" 67 ( BC_2, *, control, 1) ," &
" 68 ( BC_7, GPIO(13), bidir, X, 69, 1, Z) ," &
" 69 ( BC_2, *, control, 1) ," &
" 70 ( BC_7, GPIO(12), bidir, X, 71, 1, Z) ," &
" 71 ( BC_2, *, control, 1) ," &
" 72 ( BC_7, GPIO(11), bidir, X, 73, 1, Z) ," &
" 73 ( BC_2, *, control, 1) ," &
" 74 ( BC_7, GPIO(10), bidir, X, 75, 1, Z) ," &
" 75 ( BC_2, *, control, 1) ," &
" 76 ( BC_7, GPIO(9), bidir, X, 77, 1, Z) ," &
" 77 ( BC_2, *, control, 1) ," &
" 78 ( BC_7, GPIO(8), bidir, X, 79, 1, Z) ," &
" 79 ( BC_2, *, control, 1) ," &
" 80 ( BC_7, GPIO(7), bidir, X, 81, 1, Z) ," &
" 81 ( BC_2, *, control, 1) ," &
" 82 ( BC_7, GPIO(6), bidir, X, 83, 1, Z) ," &
" 83 ( BC_2, *, control, 1) ," &
" 84 ( BC_7, GPIO(5), bidir, X, 85, 1, Z) ," &
" 85 ( BC_2, *, control, 1) ," &
" 86 ( BC_7, GPIO(4), bidir, X, 87, 1, Z) ," &
" 87 ( BC_2, *, control, 1) ," &
" 88 ( BC_7, GPIO(3), bidir, X, 89, 1, Z) ," &
" 89 ( BC_2, *, control, 1) ," &
" 90 ( BC_7, GPIO(2), bidir, X, 91, 1, Z) ," &
" 91 ( BC_2, *, control, 1) ," &
" 92 ( BC_7, GPIO(1), bidir, X, 93, 1, Z) ," &
" 93 ( BC_2, *, control, 1) ," &
" 94 ( BC_7, GPIO(0), bidir, X, 95, 1, Z) ," &
" 95 ( BC_2, *, control, 1) ," &
" 96 ( BC_4, SYSTEM_CLK, input, X) ," &
" 97 ( BC_2, SYSTEM_DEBUG, input, X) ," &
" 98 ( BC_7, RAM_RW, bidir, X, 99, 1, Z) ," &
" 99 ( BC_2, *, control, 1) ," &
" 100 ( BC_7, RAM_BW_H, bidir, X, 101, 1, Z) ," &
" 101 ( BC_2, *, control, 1) ," &
" 102 ( BC_7, RAM_BW_G, bidir, X, 103, 1, Z) ," &
" 103 ( BC_2, *, control, 1) ," &
" 104 ( BC_7, RAM_BW_F, bidir, X, 105, 1, Z) ," &
" 105 ( BC_2, *, control, 1) ," &
" 106 ( BC_7, RAM_BW_E, bidir, X, 107, 1, Z) ," &
" 107 ( BC_2, *, control, 1) ," &
" 108 ( BC_7, RAM_BW_D, bidir, X, 109, 1, Z) ," &
" 109 ( BC_2, *, control, 1) ," &
" 110 ( BC_7, RAM_BW_C, bidir, X, 111, 1, Z) ," &
" 111 ( BC_2, *, control, 1) ," &
" 112 ( BC_7, RAM_BW_B, bidir, X, 113, 1, Z) ," &
" 113 ( BC_2, *, control, 1) ," &
" 114 ( BC_7, RAM_BW_A, bidir, X, 115, 1, Z) ," &
" 115 ( BC_2, *, control, 1) ," &
" 116 ( BC_2, PLL_SEC, output3, X, 117, 1, Z) ," &
" 117 ( BC_2, *, control, 1) ," &
" 118 ( BC_2, PLL_PRI, output3, X, 119, 1, Z) ," &
" 119 ( BC_2, *, control, 1) ," &
" 120 ( BC_2, RAM_ADDR(19), output3, X, 121, 1, Z) ," &
" 121 ( BC_2, *, control, 1) ," &
" 122 ( BC_2, RAM_ADDR(18), output3, X, 123, 1, Z) ," &
" 123 ( BC_2, *, control, 1) ," &
" 124 ( BC_2, RAM_ADDR(17), output3, X, 125, 1, Z) ," &
" 125 ( BC_2, *, control, 1) ," &
" 126 ( BC_2, RAM_ADDR(16), output3, X, 127, 1, Z) ," &
" 127 ( BC_2, *, control, 1) ," &
" 128 ( BC_2, RAM_ADDR(15), output3, X, 129, 1, Z) ," &
" 129 ( BC_2, *, control, 1) ," &
" 130 ( BC_2, RAM_ADDR(14), output3, X, 131, 1, Z) ," &
" 131 ( BC_2, *, control, 1) ," &
" 132 ( BC_2, RAM_ADDR(13), output3, X, 133, 1, Z) ," &
" 133 ( BC_2, *, control, 1) ," &
" 134 ( BC_2, RAM_ADDR(12), output3, X, 135, 1, Z) ," &
" 135 ( BC_2, *, control, 1) ," &
" 136 ( BC_2, RAM_ADDR(11), output3, X, 137, 1, Z) ," &
" 137 ( BC_2, *, control, 1) ," &
" 138 ( BC_2, RAM_ADDR(10), output3, X, 139, 1, Z) ," &
" 139 ( BC_2, *, control, 1) ," &
" 140 ( BC_2, RAM_ADDR(9), output3, X, 141, 1, Z) ," &
" 141 ( BC_2, *, control, 1) ," &
" 142 ( BC_2, RAM_ADDR(8), output3, X, 143, 1, Z) ," &
" 143 ( BC_2, *, control, 1) ," &
" 144 ( BC_2, RAM_ADDR(7), output3, X, 145, 1, Z) ," &
" 145 ( BC_2, *, control, 1) ," &
" 146 ( BC_2, RAM_ADDR(6), output3, X, 147, 1, Z) ," &
" 147 ( BC_2, *, control, 1) ," &
" 148 ( BC_2, RAM_ADDR(5), output3, X, 149, 1, Z) ," &
" 149 ( BC_2, *, control, 1) ," &
" 150 ( BC_2, RAM_ADDR(4), output3, X, 151, 1, Z) ," &
" 151 ( BC_2, *, control, 1) ," &
" 152 ( BC_2, RAM_ADDR(3), output3, X, 153, 1, Z) ," &
" 153 ( BC_2, *, control, 1) ," &
" 154 ( BC_2, RAM_ADDR(2), output3, X, 155, 1, Z) ," &
" 155 ( BC_2, *, control, 1) ," &
" 156 ( BC_2, RAM_ADDR(1), output3, X, 157, 1, Z) ," &
" 157 ( BC_2, *, control, 1) ," &
" 158 ( BC_2, RAM_ADDR(0), output3, X, 159, 1, Z) ," &
" 159 ( BC_2, *, control, 1) ," &
" 160 ( BC_7, RAM_PARITY(7), bidir, X, 161, 1, Z) ," &
" 161 ( BC_2, *, control, 1) ," &
" 162 ( BC_7, RAM_PARITY(6), bidir, X, 163, 1, Z) ," &
" 163 ( BC_2, *, control, 1) ," &
" 164 ( BC_7, RAM_PARITY(5), bidir, X, 165, 1, Z) ," &
" 165 ( BC_2, *, control, 1) ," &
" 166 ( BC_7, RAM_PARITY(4), bidir, X, 167, 1, Z) ," &
" 167 ( BC_2, *, control, 1) ," &
" 168 ( BC_7, RAM_PARITY(3), bidir, X, 169, 1, Z) ," &
" 169 ( BC_2, *, control, 1) ," &
" 170 ( BC_7, RAM_PARITY(2), bidir, X, 171, 1, Z) ," &
" 171 ( BC_2, *, control, 1) ," &
" 172 ( BC_7, RAM_PARITY(1), bidir, X, 173, 1, Z) ," &
" 173 ( BC_2, *, control, 1) ," &
" 174 ( BC_7, RAM_PARITY(0), bidir, X, 175, 1, Z) ," &
" 175 ( BC_2, *, control, 1) ," &
" 176 ( BC_7, RAM_DATA(31), bidir, X, 177, 1, Z) ," &
" 177 ( BC_2, *, control, 1) ," &
" 178 ( BC_7, RAM_DATA(30), bidir, X, 179, 1, Z) ," &
" 179 ( BC_2, *, control, 1) ," &
" 180 ( BC_7, RAM_DATA(29), bidir, X, 181, 1, Z) ," &
" 181 ( BC_2, *, control, 1) ," &
" 182 ( BC_7, RAM_DATA(28), bidir, X, 183, 1, Z) ," &
" 183 ( BC_2, *, control, 1) ," &
" 184 ( BC_7, RAM_DATA(27), bidir, X, 185, 1, Z) ," &
" 185 ( BC_2, *, control, 1) ," &
" 186 ( BC_7, RAM_DATA(26), bidir, X, 187, 1, Z) ," &
" 187 ( BC_2, *, control, 1) ," &
" 188 ( BC_7, RAM_DATA(25), bidir, X, 189, 1, Z) ," &
" 189 ( BC_2, *, control, 1) ," &
" 190 ( BC_7, RAM_DATA(24), bidir, X, 191, 1, Z) ," &
" 191 ( BC_2, *, control, 1) ," &
" 192 ( BC_7, RAM_DATA(23), bidir, X, 193, 1, Z) ," &
" 193 ( BC_2, *, control, 1) ," &
" 194 ( BC_7, RAM_DATA(22), bidir, X, 195, 1, Z) ," &
" 195 ( BC_2, *, control, 1) ," &
" 196 ( BC_7, RAM_DATA(21), bidir, X, 197, 1, Z) ," &
" 197 ( BC_2, *, control, 1) ," &
" 198 ( BC_7, RAM_DATA(20), bidir, X, 199, 1, Z) ," &
" 199 ( BC_2, *, control, 1) ," &
" 200 ( BC_7, RAM_DATA(19), bidir, X, 201, 1, Z) ," &
" 201 ( BC_2, *, control, 1) ," &
" 202 ( BC_7, RAM_DATA(18), bidir, X, 203, 1, Z) ," &
" 203 ( BC_2, *, control, 1) ," &
" 204 ( BC_7, RAM_DATA(17), bidir, X, 205, 1, Z) ," &
" 205 ( BC_2, *, control, 1) ," &
" 206 ( BC_7, RAM_DATA(16), bidir, X, 207, 1, Z) ," &
" 207 ( BC_2, *, control, 1) ," &
" 208 ( BC_7, RAM_DATA(15), bidir, X, 209, 1, Z) ," &
" 209 ( BC_2, *, control, 1) ," &
" 210 ( BC_7, RAM_DATA(14), bidir, X, 211, 1, Z) ," &
" 211 ( BC_2, *, control, 1) ," &
" 212 ( BC_7, RAM_DATA(13), bidir, X, 213, 1, Z) ," &
" 213 ( BC_2, *, control, 1) ," &
" 214 ( BC_7, RAM_DATA(12), bidir, X, 215, 1, Z) ," &
" 215 ( BC_2, *, control, 1) ," &
" 216 ( BC_7, RAM_DATA(11), bidir, X, 217, 1, Z) ," &
" 217 ( BC_2, *, control, 1) ," &
" 218 ( BC_7, RAM_DATA(10), bidir, X, 219, 1, Z) ," &
" 219 ( BC_2, *, control, 1) ," &
" 220 ( BC_7, RAM_DATA(9), bidir, X, 221, 1, Z) ," &
" 221 ( BC_2, *, control, 1) ," &
" 222 ( BC_7, RAM_DATA(8), bidir, X, 223, 1, Z) ," &
" 223 ( BC_2, *, control, 1) ," &
" 224 ( BC_7, RAM_DATA(7), bidir, X, 225, 1, Z) ," &
" 225 ( BC_2, *, control, 1) ," &
" 226 ( BC_7, RAM_DATA(6), bidir, X, 227, 1, Z) ," &
" 227 ( BC_2, *, control, 1) ," &
" 228 ( BC_7, RAM_DATA(5), bidir, X, 229, 1, Z) ," &
" 229 ( BC_2, *, control, 1) ," &
" 230 ( BC_7, RAM_DATA(4), bidir, X, 231, 1, Z) ," &
" 231 ( BC_2, *, control, 1) ," &
" 232 ( BC_7, RAM_DATA(3), bidir, X, 233, 1, Z) ," &
" 233 ( BC_2, *, control, 1) ," &
" 234 ( BC_7, RAM_DATA(2), bidir, X, 235, 1, Z) ," &
" 235 ( BC_2, *, control, 1) ," &
" 236 ( BC_7, RAM_DATA(1), bidir, X, 237, 1, Z) ," &
" 237 ( BC_2, *, control, 1) ," &
" 238 ( BC_7, RAM_DATA(0), bidir, X, 239, 1, Z) ," &
" 239 ( BC_2, *, control, 1) ," &
" 240 ( BC_4, TDM_CLKIS, input, X) ," &
" 241 ( BC_4, TDM_CLKIP, input, X) ," &
" 242 ( BC_2, TDM_FRMO_REF, output3, X, 243, 1, Z) ," &
" 243 ( BC_2, *, control, 1) ," &
" 244 ( BC_2, TDM_CLKO_REF, output3, X, 245, 1, Z) ," &
" 245 ( BC_2, *, control, 1) ," &
" 246 ( BC_4, TDM_FRMI_REF, input, X) ," &
" 247 ( BC_4, TDM_CLKI_REF, input, X) ," &
" 248 ( BC_2, TDM_CLKO(0), output3, X, 249, 1, Z) ," &
" 249 ( BC_2, *, control, 1) ," &
" 250 ( BC_2, TDM_CLKI(0), input, X) ," &
" 251 ( BC_2, TDM_STO(0), output3, X, 252, 1, Z) ," &
" 252 ( BC_2, *, control, 1) ," &
" 253 ( BC_2, TDM_STI(0), input, X) ," &
" 254 ( BC_2, TDM_CLKO(1), output3, X, 255, 1, Z) ," &
" 255 ( BC_2, *, control, 1) ," &
" 256 ( BC_2, TDM_CLKI(1), input, X) ," &
" 257 ( BC_2, TDM_STO(1), output3, X, 258, 1, Z) ," &
" 258 ( BC_2, *, control, 1) ," &
" 259 ( BC_2, TDM_STI(1), input, X) ," &
" 260 ( BC_2, TDM_CLKO(2), output3, X, 261, 1, Z) ," &
" 261 ( BC_2, *, control, 1) ," &
" 262 ( BC_2, TDM_CLKI(2), input, X) ," &
" 263 ( BC_2, TDM_STO(2), output3, X, 264, 1, Z) ," &
" 264 ( BC_2, *, control, 1) ," &
" 265 ( BC_2, TDM_STI(2), input, X) ," &
" 266 ( BC_2, TDM_CLKO(3), output3, X, 267, 1, Z) ," &
" 267 ( BC_2, *, control, 1) ," &
" 268 ( BC_2, TDM_CLKI(3), input, X) ," &
" 269 ( BC_2, TDM_STO(3), output3, X, 270, 1, Z) ," &
" 270 ( BC_2, *, control, 1) ," &
" 271 ( BC_2, TDM_STI(3), input, X) ," &
" 272 ( BC_2, M1_LINKUP_LED, output3, X, 273, 1, Z) ," &
" 273 ( BC_2, *, control, 1) ," &
" 274 ( BC_2, M0_LINKUP_LED, output3, X, 275, 1, Z) ," &
" 275 ( BC_2, *, control, 1) ," &
" 276 ( BC_2, M1_GIGABIT_LED, output3, X, 277, 1, Z) ," &
" 277 ( BC_2, *, control, 1) ," &
" 278 ( BC_2, M0_GIGABIT_LED, output3, X, 279, 1, Z) ," &
" 279 ( BC_2, *, control, 1) ," &
" 280 ( BC_7, M_MDIO, bidir, X, 281, 1, Z) ," &
" 281 ( BC_2, *, control, 1) ," &
" 282 ( BC_2, M_MDC, output3, X, 283, 1, Z) ," &
" 283 ( BC_2, *, control, 1) ," &
" 284 ( BC_2, M1_CRS, input, X) ," &
" 285 ( BC_4, M1_TXCLK, input, X) ," &
" 286 ( BC_2, M1_RXER, input, X) ," &
" 287 ( BC_2, M1_RXDV, input, X) ," &
" 288 ( BC_2, M1_RXD(7), input, X) ," &
" 289 ( BC_2, M1_RXD(6), input, X) ," &
" 290 ( BC_2, M1_RXD(5), input, X) ," &
" 291 ( BC_2, M1_RXD(4), input, X) ," &
" 292 ( BC_2, M1_RXD(3), input, X) ," &
" 293 ( BC_2, M1_RXD(2), input, X) ," &
" 294 ( BC_2, M1_RXD(1), input, X) ," &
" 295 ( BC_2, M1_RXD(0), input, X) ," &
" 296 ( BC_2, M1_COL, input, X) ," &
" 297 ( BC_4, M1_RXCLK, input, X) ," &
" 298 ( BC_4, M1_RBC1, input, X) ," &
" 299 ( BC_4, M1_RBC0, input, X) ," &
" 300 ( BC_4, M1_REFCLK, input, X) ," &
" 301 ( BC_2, M1_GTX_CLK, output3, X, 302, 1, Z) ," &
" 302 ( BC_2, *, control, 1) ," &
" 303 ( BC_2, M1_TXER, output3, X, 304, 1, Z) ," &
" 304 ( BC_2, *, control, 1) ," &
" 305 ( BC_2, M1_TXEN, output3, X, 306, 1, Z) ," &
" 306 ( BC_2, *, control, 1) ," &
" 307 ( BC_2, M1_TXD(7), output3, X, 308, 1, Z) ," &
" 308 ( BC_2, *, control, 1) ," &
" 309 ( BC_2, M1_TXD(6), output3, X, 310, 1, Z) ," &
" 310 ( BC_2, *, control, 1) ," &
" 311 ( BC_2, M1_TXD(5), output3, X, 312, 1, Z) ," &
" 312 ( BC_2, *, control, 1) ," &
" 313 ( BC_2, M1_TXD(4), output3, X, 314, 1, Z) ," &
" 314 ( BC_2, *, control, 1) ," &
" 315 ( BC_2, M1_TXD(3), output3, X, 316, 1, Z) ," &
" 316 ( BC_2, *, control, 1) ," &
" 317 ( BC_2, M1_TXD(2), output3, X, 318, 1, Z) ," &
" 318 ( BC_2, *, control, 1) ," &
" 319 ( BC_2, M1_TXD(1), output3, X, 320, 1, Z) ," &
" 320 ( BC_2, *, control, 1) ," &
" 321 ( BC_2, M1_TXD(0), output3, X, 322, 1, Z) ," &
" 322 ( BC_2, *, control, 1) ," &
" 323 ( BC_2, M0_CRS, input, X) ," &
" 324 ( BC_4, M0_TXCLK, input, X) ," &
" 325 ( BC_2, M0_RXER, input, X) ," &
" 326 ( BC_2, M0_RXDV, input, X) ," &
" 327 ( BC_2, M0_RXD(7), input, X) ," &
" 328 ( BC_2, M0_RXD(6), input, X) ," &
" 329 ( BC_2, M0_RXD(5), input, X) ," &
" 330 ( BC_2, M0_RXD(4), input, X) ," &
" 331 ( BC_2, M0_RXD(3), input, X) ," &
" 332 ( BC_2, M0_RXD(2), input, X) ," &
" 333 ( BC_2, M0_RXD(1), input, X) ," &
" 334 ( BC_2, M0_RXD(0), input, X) ," &
" 335 ( BC_2, M0_COL, input, X) ," &
" 336 ( BC_4, M0_RXCLK, input, X) ," &
" 337 ( BC_4, M0_RBC1, input, X) ," &
" 338 ( BC_4, M0_RBC0, input, X) ," &
" 339 ( BC_4, M0_REFCLK, input, X) ," &
" 340 ( BC_2, M0_GTX_CLK, output3, X, 341, 1, Z) ," &
" 341 ( BC_2, *, control, 1) ," &
" 342 ( BC_2, M0_TXER, output3, X, 343, 1, Z) ," &
" 343 ( BC_2, *, control, 1) ," &
" 344 ( BC_2, M0_TXEN, output3, X, 345, 1, Z) ," &
" 345 ( BC_2, *, control, 1) ," &
" 346 ( BC_2, M0_TXD(7), output3, X, 347, 1, Z) ," &
" 347 ( BC_2, *, control, 1) ," &
" 348 ( BC_2, M0_TXD(6), output3, X, 349, 1, Z) ," &
" 349 ( BC_2, *, control, 1) ," &
" 350 ( BC_2, M0_TXD(5), output3, X, 351, 1, Z) ," &
" 351 ( BC_2, *, control, 1) ," &
" 352 ( BC_2, M0_TXD(4), output3, X, 353, 1, Z) ," &
" 353 ( BC_2, *, control, 1) ," &
" 354 ( BC_2, M0_TXD(3), output3, X, 355, 1, Z) ," &
" 355 ( BC_2, *, control, 1) ," &
" 356 ( BC_2, M0_TXD(2), output3, X, 357, 1, Z) ," &
" 357 ( BC_2, *, control, 1) ," &
" 358 ( BC_2, M0_TXD(1), output3, X, 359, 1, Z) ," &
" 359 ( BC_2, *, control, 1) ," &
" 360 ( BC_2, M0_TXD(0), output3, X, 361, 1, Z) ," &
" 361 ( BC_2, *, control, 1) ," &
" 362 ( BC_2, M1_ACTIVE_LED, output3, X, 363, 1, Z) ," &
" 363 ( BC_2, *, control, 1) ," &
" 364 ( BC_2, M0_ACTIVE_LED, output3, X, 365, 1, Z) ," &
" 365 ( BC_2, *, control, 1) ," &
" 366 ( BC_7, CPU_DATA(31), bidir, X, 367, 1, Z) ," &
" 367 ( BC_2, *, control, 1) ," &
" 368 ( BC_7, CPU_DATA(30), bidir, X, 369, 1, Z) ," &
" 369 ( BC_2, *, control, 1) ," &
" 370 ( BC_7, CPU_DATA(29), bidir, X, 371, 1, Z) ," &
" 371 ( BC_2, *, control, 1) ," &
" 372 ( BC_7, CPU_DATA(28), bidir, X, 373, 1, Z) ," &
" 373 ( BC_2, *, control, 1) ," &
" 374 ( BC_7, CPU_DATA(27), bidir, X, 375, 1, Z) ," &
" 375 ( BC_2, *, control, 1) ," &
" 376 ( BC_7, CPU_DATA(26), bidir, X, 377, 1, Z) ," &
" 377 ( BC_2, *, control, 1) ," &
" 378 ( BC_7, CPU_DATA(25), bidir, X, 379, 1, Z) ," &
" 379 ( BC_2, *, control, 1) ," &
" 380 ( BC_7, CPU_DATA(24), bidir, X, 381, 1, Z) ," &
" 381 ( BC_2, *, control, 1) ," &
" 382 ( BC_7, CPU_DATA(23), bidir, X, 383, 1, Z) ," &
" 383 ( BC_2, *, control, 1) ," &
" 384 ( BC_7, CPU_DATA(22), bidir, X, 385, 1, Z) ," &
" 385 ( BC_2, *, control, 1) ," &
" 386 ( BC_7, CPU_DATA(21), bidir, X, 387, 1, Z) ," &
" 387 ( BC_2, *, control, 1) ," &
" 388 ( BC_7, CPU_DATA(20), bidir, X, 389, 1, Z) ," &
" 389 ( BC_2, *, control, 1) ," &
" 390 ( BC_7, CPU_DATA(19), bidir, X, 391, 1, Z) ," &
" 391 ( BC_2, *, control, 1) ," &
" 392 ( BC_7, CPU_DATA(18), bidir, X, 393, 1, Z) ," &
" 393 ( BC_2, *, control, 1) ," &
" 394 ( BC_7, CPU_DATA(17), bidir, X, 395, 1, Z) ," &
" 395 ( BC_2, *, control, 1) ," &
" 396 ( BC_7, CPU_DATA(16), bidir, X, 397, 1, Z) ," &
" 397 ( BC_2, *, control, 1) ," &
" 398 ( BC_7, CPU_DATA(15), bidir, X, 399, 1, Z) ," &
" 399 ( BC_2, *, control, 1) ," &
" 400 ( BC_7, CPU_DATA(14), bidir, X, 401, 1, Z) ," &
" 401 ( BC_2, *, control, 1) ," &
" 402 ( BC_7, CPU_DATA(13), bidir, X, 403, 1, Z) ," &
" 403 ( BC_2, *, control, 1) ," &
" 404 ( BC_7, CPU_DATA(12), bidir, X, 405, 1, Z) ," &
" 405 ( BC_2, *, control, 1) ," &
" 406 ( BC_7, CPU_DATA(11), bidir, X, 407, 1, Z) ," &
" 407 ( BC_2, *, control, 1) ," &
" 408 ( BC_7, CPU_DATA(10), bidir, X, 409, 1, Z) ," &
" 409 ( BC_2, *, control, 1) ," &
" 410 ( BC_7, CPU_DATA(9), bidir, X, 411, 1, Z) ," &
" 411 ( BC_2, *, control, 1) ," &
" 412 ( BC_7, CPU_DATA(8), bidir, X, 413, 1, Z) ," &
" 413 ( BC_2, *, control, 1) ," &
" 414 ( BC_7, CPU_DATA(7), bidir, X, 415, 1, Z) ," &
" 415 ( BC_2, *, control, 1) ," &
" 416 ( BC_7, CPU_DATA(6), bidir, X, 417, 1, Z) ," &
" 417 ( BC_2, *, control, 1) ," &
" 418 ( BC_7, CPU_DATA(5), bidir, X, 419, 1, Z) ," &
" 419 ( BC_2, *, control, 1) ," &
" 420 ( BC_7, CPU_DATA(4), bidir, X, 421, 1, Z) ," &
" 421 ( BC_2, *, control, 1) ," &
" 422 ( BC_7, CPU_DATA(3), bidir, X, 423, 1, Z) ," &
" 423 ( BC_2, *, control, 1) ," &
" 424 ( BC_7, CPU_DATA(2), bidir, X, 425, 1, Z) ," &
" 425 ( BC_2, *, control, 1) ," &
" 426 ( BC_7, CPU_DATA(1), bidir, X, 427, 1, Z) ," &
" 427 ( BC_2, *, control, 1) ," &
" 428 ( BC_7, CPU_DATA(0), bidir, X, 429, 1, Z) ," &
" 429 ( BC_2, *, control, 1) ," &
" 430 ( BC_0, *, internal, X) ," &
" 431 ( BC_0, *, internal, 1) ," &
" 432 ( BC_0, *, internal, X) ," &
" 433 ( BC_0, *, internal, 1) ," &
" 434 ( BC_7, CPU_IREQ1, bidir, X, 435, 1, Z) ," &
" 435 ( BC_2, *, control, 1) ," &
" 436 ( BC_7, CPU_IREQ0, bidir, X, 437, 1, Z) ," &
" 437 ( BC_2, *, control, 1) ," &
" 438 ( BC_7, CPU_DREQ1, bidir, X, 439, 1, Z) ," &
" 439 ( BC_2, *, control, 1) ," &
" 440 ( BC_7, CPU_DREQ0, bidir, X, 441, 1, Z) ," &
" 441 ( BC_2, *, control, 1) ," &
" 442 ( BC_7, CPU_TA, bidir, X, 443, 1, Z) ," &
" 443 ( BC_2, *, control, 1) ," &
" 444 ( BC_0, *, internal, X) ," &
" 445 ( BC_4, CPU_CLK, input, X) ," &
" 446 ( BC_2, CPU_SDACK2, input, X) ," &
" 447 ( BC_2, CPU_SDACK1, input, X) ," &
" 448 ( BC_2, CPU_TS_ALE, input, X) ," &
" 449 ( BC_2, CPU_OE, input, X) ," &
" 450 ( BC_2, CPU_WE, input, X) ," &
" 451 ( BC_2, CPU_CS, input, X) ," &
" 452 ( BC_2, CPU_ADDR(23), input, X) ," &
" 453 ( BC_2, CPU_ADDR(22), input, X) ," &
" 454 ( BC_2, CPU_ADDR(21), input, X) ," &
" 455 ( BC_2, CPU_ADDR(20), input, X) ," &
" 456 ( BC_2, CPU_ADDR(19), input, X) ," &
" 457 ( BC_2, CPU_ADDR(18), input, X) ," &
" 458 ( BC_2, CPU_ADDR(17), input, X) ," &
" 459 ( BC_2, CPU_ADDR(16), input, X) ," &
" 460 ( BC_2, CPU_ADDR(15), input, X) ," &
" 461 ( BC_2, CPU_ADDR(14), input, X) ," &
" 462 ( BC_2, CPU_ADDR(13), input, X) ," &
" 463 ( BC_2, CPU_ADDR(12), input, X) ," &
" 464 ( BC_2, CPU_ADDR(11), input, X) ," &
" 465 ( BC_2, CPU_ADDR(10), input, X) ," &
" 466 ( BC_2, CPU_ADDR(9), input, X) ," &
" 467 ( BC_2, CPU_ADDR(8), input, X) ," &
" 468 ( BC_2, CPU_ADDR(7), input, X) ," &
" 469 ( BC_2, CPU_ADDR(6), input, X) ," &
" 470 ( BC_2, CPU_ADDR(5), input, X) ," &
" 471 ( BC_2, CPU_ADDR(4), input, X) ," &
" 472 ( BC_2, CPU_ADDR(3), input, X) ," &
" 473 ( BC_2, CPU_ADDR(2), input, X) ," &
" 474 ( BC_0, *, internal, X) ," &
" 475 ( BC_0, *, internal, X) ";
end zl50114;
------------- end of BSDL description for the zl50114 ----------