This BSDL contains syntax errors!
-- Motorola 68040 BSDL description
-- Version 2.3 08-12-93
-- Revision List:
-- (11) Added 184-pin QFP package description
-- (10) Port bit_vector ranges for EGND, PGND, and PVDD increased
-- (9) Added comments about package pin differences
-- (8) No other changes to Version 2.2 BSDL
-- (7) LOCK and LOCKE controlled by io.1 vice io.0 (4D98D)
-- (6) No other changes to Version 2.1 BSDL
-- (5) Instruction opcodes changed for SAMPLE, SHUTDOWN, and BYPASS
-- (4) New instructions DRVCTL.T, DRVCTL.S and PRIVATE added
-- (3) New instructions DRVCTL.T and DRVCTL.S renamed to
-- DRVCTL_T and DRVCTL_S for syntax compatibility
-- (2) Register access specified for
-- DRVCTL_T, DRVCTL_S, and PRIVATE instructions
-- (1) No other changes to Version 1.0 BSDL
-- Package type: 18 x 18 PGA
-- This BSDL is for the "newer" 68040 mask sets of E26A and after (roughly
-- after the 2nd half of 1992). It does not include the 0.8um mask sets
-- D43B, D50D, and D98D.
-- For EC/LC040 models, two pin names have changed. To make the necessary
-- modifications, change all occurrances of DLE to JS0 and MDIS to JS1.
-- Package type pin differences:
-- Signal pins are identical but some port linkage pin counts are different.
-- Where different, the port bit_vector range is the larger range.
-- These differences and the port bit_vector range changes are as follows:
-- -- EGND: QFP has 4 more than PGA bit_vector(1 to 27) vice (1 to 23)
-- -- PGND: QFP has 1 more than PGA bit_vector(1 to 4) vice (1 to 3)
-- -- PVDD: QFP has 2 more than PGA bit_vector(1 to 4) vice (1 to 2)
-- -- IGND: QFP has 2 less than PGA (no change)
entity MC68040 is
generic(PHYSICAL_PIN_MAP:string := "PGA_18x18");
port(TDI: in bit;
TDO: out bit;
TMS: in bit;
TCK: in bit;
TRST: in bit;
RSTO: buffer bit;
IPEND: buffer bit;
CIOUT: out bit;
UPA: out bit_vector(0 to 1);
TT: inout bit_vector(0 to 1);
A: inout bit_vector(0 to 31);
D: inout bit_vector(0 to 31);
LOCKE: out bit;
LOCK: out bit;
R_W: inout bit;
TLN: out bit_vector(0 to 1);
TM: out bit_vector(0 to 2);
SIZ: inout bit_vector(0 to 1);
MI: buffer bit;
BR: buffer bit;
TS: inout bit;
BB: inout bit;
TIP: out bit;
PST: buffer bit_vector(0 to 3);
TA: inout bit;
TEA: in bit;
BG: in bit;
SC: in bit_vector(0 to 1);
TBI: in bit;
AVEC: in bit;
TCI: in bit;
DLE: in bit;
PCLK: in bit;
BCLK: in bit;
IPL: in bit_vector(0 to 2);
RSTI: in bit;
CDIS: in bit;
MDIS: in bit;
EGND: linkage bit_vector(1 to 27);
EVDD: linkage bit_vector(1 to 12);
IGND: linkage bit_vector(1 to 12);
IVDD: linkage bit_vector(1 to 7);
CGND: linkage bit_vector(1 to 2);
CVDD: linkage bit_vector(1 to 6);
PGND: linkage bit_vector(1 to 4);
PVDD: linkage bit_vector(1 to 4)
);
use STD_1149_1_1990.all;
attribute PIN_MAP of MC68040 : entity is PHYSICAL_PIN_MAP;
-- 18x18 PGA Pin Map
constant PGA_18x18 : PIN_MAP_STRING :=
"TDI: S3, " &
"TDO: T2, " &
"TMS: S5, " &
"TCK: S4, " &
"TRST: T3, " &
"RSTO: R3, " &
"IPEND: S1, " &
"CIOUT: R1, " &
"UPA: (Q3, Q1), " &
"TT: (P3, P2), " &
"A: (L18, K18, J17, J18, H18, G18, G16, F18, E18, F16, P1, N3, " &
" N1, M1, L1, K1, K2, J1, H1, J2, G1, F1, E1, G3, " &
" D1, F3, E2, C1, E3, B1, D3, A1), " &
"D: (C3, B3, C4, A2, A3, A4, A5, A6, B7, A7, A8, A9, " &
" A10, A11, A12, A13, B11, A14, B12, A15, A16, A17, B16, C15," &
" A18, C16, B18, D16, C18, E16, E17, D18), " &
"LOCKE: R18, " &
"LOCK: S18, " &
"R_W: N16, " &
"TLN: (Q18, P18), " &
"TM: (N18, M18, K17), " &
"SIZ: (P17, P16), " &
"MI: Q16, " &
"BR: T18, " &
"TS: R16, " &
"BB: T17, " &
"TIP: R15, " &
"PST: (T15, S14, R14, T16), " &
"TA: T14, " &
"TEA: S13, " &
"BG: T13, " &
"SC: (T12, S12), " &
"TBI: S11, " &
"AVEC: T11, " &
"TCI: T10, " &
"DLE: T9, " &
"PCLK: R9, " &
"BCLK: R7, " &
"IPL: (T8, T7, T6), " &
"RSTI: S7, " &
"CDIS: T5, " &
"MDIS: S6, " &
"EGND: (S2, Q2, N2, L2, H2, F2, D2, B2, B4, B6, B8, B10," &
" B13, B15, B17, D17, F17, H17, L17, N17, Q17, S17, S15), " &
"EVDD: (R2, M2, G2, C2, B5, B9, B14, C17, G17, M17, R17, S16)," &
"IGND: (T4, R4, L3, K3, C7, C9, C11, K16, M16, R13, R11, S10)," &
"IVDD: (R5, M3, C8, C10, C12, L16, R12), " &
"CGND: (C6, C13), " &
"CVDD: (J3, H3, C5, C14, H16, J16), " &
"PGND: (S9, R10, R6), " &
"PVDD: (S8, R8) ";
-- 184 QFP Pin Map
constant QFP_184 : PIN_MAP_STRING :=
"TDI: 3, " &
"TDO: 2, " &
"TMS: 7, " &
"TCK: 4, " &
"TRST: 6, " &
"RSTO: 1, " &
"IPEND: 183, " &
"CIOUT: 182, " &
"UPA: (180, 179), " &
"TT: (177, 176), " &
"A: ( 70, 71, 73, 74, 76, 77, 79, 80, 82, 83, 173, 172, " &
" 170, 169, 167, 166, 164, 163, 160, 159, 157, 156, 154, 153, " &
" 151, 150, 148, 147, 145, 144, 142, 141), " &
"D: (138, 137, 134, 133, 131, 129, 127, 126, 124, 123, 120, 119, " &
" 117, 116, 114, 113, 111, 110, 107, 106, 104, 103, 101, 99, " &
" 97, 96, 93, 92, 90, 89, 87, 86), " &
"LOCKE: 57, " &
"LOCK: 53, " &
"R_W: 58, " &
"TLN: (61, 63), " &
"TM: (64, 66, 67), " &
"SIZ: (60, 54), " &
"MI: 51, " &
"BR: 50, " &
"TS: 48, " &
"BB: 47, " &
"TIP: 45, " &
"PST: (39, 41, 42, 44), " &
"TA: 38, " &
"TEA: 37, " &
"BG: 36, " &
"SC: (34, 35), " &
"TBI: 31, " &
"AVEC: 30, " &
"TCI: 29, " &
"DLE: 26, " &
"PCLK: 23, " &
"BCLK: 18, " &
"IPL: (15, 14, 13), " &
"RSTI: 12, " &
"CDIS: 11, " &
"MDIS: 10, " &
"EGND: ( 8, 28, 40, 46, 52, 59, 65, 72, 78, 84, 85, 91, " &
" 98, 105, 112, 118, 125, 132, 139, 140, 146, 152, 158, 165, " &
" 171, 178, 184), " &
"EVDD: ( 43, 49, 62, 75, 88, 102, 115, 128, 143, 155, 168, 181)," &
"IGND: ( 5, 27, 33, 55, 68, 108, 121, 130, 162, 174)," &
"IVDD: ( 9, 32, 56, 100, 109, 122, 175), " &
"CGND: ( 95, 135), " &
"CVDD: ( 69, 81, 94, 136, 149, 161), " &
"PGND: ( 17, 20, 22, 24), " &
"PVDD: ( 16, 19, 21, 25) ";
-- Other Pin Maps here when documented
attribute TAP_SCAN_IN of TDI:signal is true;
attribute TAP_SCAN_OUT of TDO:signal is true;
attribute TAP_SCAN_MODE of TMS:signal is true;
attribute TAP_SCAN_CLOCK of TCK:signal is (10.0e6, BOTH);
attribute TAP_SCAN_RESET of TRST:signal is true;
attribute INSTRUCTION_LENGTH of MC68040:entity is 3;
attribute INSTRUCTION_OPCODE of MC68040:entity is
"EXTEST (000)," &
"HI_Z (001)," &
"SAMPLE (010)," &
"DRVCTL_T (011)," &
"SHUTDOWN (100)," &
"PRIVATE (101)," &
"DRVCTL_S (110)," &
"BYPASS (111)";
attribute INSTRUCTION_CAPTURE of MC68040:entity is "001";
attribute INSTRUCTION_DISABLE of MC68040:entity is "HI_Z";
attribute REGISTER_ACCESS of MC68040:entity is
"BYPASS (SHUTDOWN, HI_Z, PRIVATE), " &
"BOUNDARY (DRVCTL_T, DRVCTL_S)";
attribute BOUNDARY_CELLS of MC68040:entity is
"BC_2, BC_4";
attribute BOUNDARY_LENGTH of MC68040:entity is 184;
attribute BOUNDARY_REGISTER of MC68040:entity is
--num cell port function safe ccell dsval rslt
"0 (BC_2, RSTO, output2, X), " &
"1 (BC_2, IPEND, output2, X), " &
"2 (BC_2, CIOUT, output3, X, 156, 0, Z), " & -- 156 = io.0
"3 (BC_2, UPA(0), output3, X, 156, 0, Z), " &
"4 (BC_2, UPA(1), output3, X, 156, 0, Z), " &
"5 (BC_2, TT(0), output3, X, 156, 0, Z), " &
"6 (BC_4, TT(0), input, X), " &
"7 (BC_2, TT(1), output3, X, 156, 0, Z), " &
"8 (BC_4, TT(1), input, X), " &
"9 (BC_2, A(10), output3, X, 150, 0, Z), " & -- 150 = io.ab
"10 (BC_4, A(10), input, X), " &
"11 (BC_2, A(11), output3, X, 150, 0, Z), " &
"12 (BC_4, A(11), input, X), " &
"13 (BC_2, A(12), output3, X, 150, 0, Z), " &
"14 (BC_4, A(12), input, X), " &
"15 (BC_2, A(13), output3, X, 150, 0, Z), " &
"16 (BC_4, A(13), input, X), " &
"17 (BC_2, A(14), output3, X, 150, 0, Z), " &
"18 (BC_4, A(14), input, X), " &
"19 (BC_2, A(15), output3, X, 150, 0, Z), " &
--num cell port function safe ccell dsval rslt
"20 (BC_4, A(15), input, X), " &
"21 (BC_2, A(16), output3, X, 150, 0, Z), " &
"22 (BC_4, A(16), input, X), " &
"23 (BC_2, A(17), output3, X, 150, 0, Z), " &
"24 (BC_4, A(17), input, X), " &
"25 (BC_2, A(18), output3, X, 150, 0, Z), " &
"26 (BC_4, A(18), input, X), " &
"27 (BC_2, A(19), output3, X, 150, 0, Z), " &
"28 (BC_4, A(19), input, X), " &
"29 (BC_2, A(20), output3, X, 150, 0, Z), " &
"30 (BC_4, A(20), input, X), " &
"31 (BC_2, A(21), output3, X, 150, 0, Z), " &
"32 (BC_4, A(21), input, X), " &
"33 (BC_2, A(22), output3, X, 150, 0, Z), " &
"34 (BC_4, A(22), input, X), " &
"35 (BC_2, A(23), output3, X, 150, 0, Z), " &
"36 (BC_4, A(23), input, X), " &
"37 (BC_2, A(24), output3, X, 150, 0, Z), " &
"38 (BC_4, A(24), input, X), " &
"39 (BC_2, A(25), output3, X, 150, 0, Z), " &
--num cell port function safe ccell dsval rslt
"40 (BC_4, A(25), input, X), " &
"41 (BC_2, A(26), output3, X, 150, 0, Z), " &
"42 (BC_4, A(26), input, X), " &
"43 (BC_2, A(27), output3, X, 150, 0, Z), " &
"44 (BC_4, A(27), input, X), " &
"45 (BC_2, A(28), output3, X, 150, 0, Z), " &
"46 (BC_4, A(28), input, X), " &
"47 (BC_2, A(29), output3, X, 150, 0, Z), " &
"48 (BC_4, A(29), input, X), " &
"49 (BC_2, A(30), output3, X, 150, 0, Z), " &
"50 (BC_4, A(30), input, X), " &
"51 (BC_2, A(31), output3, X, 150, 0, Z), " &
"52 (BC_4, A(31), input, X), " &
"53 (BC_2, D(0), output3, X, 151, 0, Z), " & -- 151 = io.db
"54 (BC_2, D(1), output3, X, 151, 0, Z), " &
"55 (BC_2, D(2), output3, X, 151, 0, Z), " &
"56 (BC_2, D(3), output3, X, 151, 0, Z), " &
"57 (BC_2, D(4), output3, X, 151, 0, Z), " &
"58 (BC_2, D(5), output3, X, 151, 0, Z), " &
"59 (BC_2, D(6), output3, X, 151, 0, Z), " &
--num cell port function safe ccell dsval rslt
"60 (BC_2, D(7), output3, X, 151, 0, Z), " &
"61 (BC_2, D(8), output3, X, 151, 0, Z), " &
"62 (BC_2, D(9), output3, X, 151, 0, Z), " &
"63 (BC_2, D(10), output3, X, 151, 0, Z), " &
"64 (BC_2, D(11), output3, X, 151, 0, Z), " &
"65 (BC_2, D(12), output3, X, 151, 0, Z), " &
"66 (BC_2, D(13), output3, X, 151, 0, Z), " &
"67 (BC_2, D(14), output3, X, 151, 0, Z), " &
"68 (BC_2, D(15), output3, X, 151, 0, Z), " &
"69 (BC_2, D(16), output3, X, 151, 0, Z), " &
"70 (BC_2, D(17), output3, X, 151, 0, Z), " &
"71 (BC_2, D(18), output3, X, 151, 0, Z), " &
"72 (BC_2, D(19), output3, X, 151, 0, Z), " &
"73 (BC_2, D(20), output3, X, 151, 0, Z), " &
"74 (BC_2, D(21), output3, X, 151, 0, Z), " &
"75 (BC_2, D(22), output3, X, 151, 0, Z), " &
"76 (BC_2, D(23), output3, X, 151, 0, Z), " &
"77 (BC_2, D(24), output3, X, 151, 0, Z), " &
"78 (BC_2, D(25), output3, X, 151, 0, Z), " &
"79 (BC_2, D(26), output3, X, 151, 0, Z), " &
--num cell port function safe ccell dsval rslt
"80 (BC_2, D(27), output3, X, 151, 0, Z), " &
"81 (BC_2, D(28), output3, X, 151, 0, Z), " &
"82 (BC_2, D(29), output3, X, 151, 0, Z), " &
"83 (BC_2, D(30), output3, X, 151, 0, Z), " &
"84 (BC_2, D(31), output3, X, 151, 0, Z), " &
"85 (BC_4, D(0), input, X), " &
"86 (BC_4, D(1), input, X), " &
"87 (BC_4, D(2), input, X), " &
"88 (BC_4, D(3), input, X), " &
"89 (BC_4, D(4), input, X), " &
"90 (BC_4, D(5), input, X), " &
"91 (BC_4, D(6), input, X), " &
"92 (BC_4, D(7), input, X), " &
"93 (BC_4, D(8), input, X), " &
"94 (BC_4, D(9), input, X), " &
"95 (BC_4, D(10), input, X), " &
"96 (BC_4, D(11), input, X), " &
"97 (BC_4, D(12), input, X), " &
"98 (BC_4, D(13), input, X), " &
"99 (BC_4, D(14), input, X), " &
--num cell port function safe ccell dsval rslt
"100 (BC_4, D(15), input, X), " &
"101 (BC_4, D(16), input, X), " &
"102 (BC_4, D(17), input, X), " &
"103 (BC_4, D(18), input, X), " &
"104 (BC_4, D(19), input, X), " &
"105 (BC_4, D(20), input, X), " &
"106 (BC_4, D(21), input, X), " &
"107 (BC_4, D(22), input, X), " &
"108 (BC_4, D(23), input, X), " &
"109 (BC_4, D(24), input, X), " &
"110 (BC_4, D(25), input, X), " &
"111 (BC_4, D(26), input, X), " &
"112 (BC_4, D(27), input, X), " &
"113 (BC_4, D(28), input, X), " &
"114 (BC_4, D(29), input, X), " &
"115 (BC_4, D(30), input, X), " &
"116 (BC_4, D(31), input, X), " &
"117 (BC_2, A(9), output3, X, 150, 0, Z), " & -- 150 = io.ab
"118 (BC_4, A(9), input, X), " &
"119 (BC_2, A(8), output3, X, 150, 0, Z), " &
--num cell port function safe ccell dsval rslt
"120 (BC_4, A(8), input, X), " &
"121 (BC_2, A(7), output3, X, 150, 0, Z), " &
"122 (BC_4, A(7), input, X), " &
"123 (BC_2, A(6), output3, X, 150, 0, Z), " &
"124 (BC_4, A(6), input, X), " &
"125 (BC_2, A(5), output3, X, 150, 0, Z), " &
"126 (BC_4, A(5), input, X), " &
"127 (BC_2, A(4), output3, X, 150, 0, Z), " &
"128 (BC_4, A(4), input, X), " &
"129 (BC_2, A(3), output3, X, 150, 0, Z), " &
"130 (BC_4, A(3), input, X), " &
"131 (BC_2, A(2), output3, X, 150, 0, Z), " &
"132 (BC_4, A(2), input, X), " &
"133 (BC_2, A(1), output3, X, 150, 0, Z), " &
"134 (BC_4, A(1), input, X), " &
"135 (BC_2, A(0), output3, X, 150, 0, Z), " &
"136 (BC_4, A(0), input, X), " &
"137 (BC_2, TM(2), output3, X, 156, 0, Z), " & -- 156 = io.0
"138 (BC_2, TM(1), output3, X, 156, 0, Z), " &
"139 (BC_2, TM(0), output3, X, 156, 0, Z), " &
--num cell port function safe ccell dsval rslt
"140 (BC_2, TLN(1), output3, X, 156, 0, Z), " &
"141 (BC_2, TLN(0), output3, X, 156, 0, Z), " &
"142 (BC_2, SIZ(0), output3, X, 156, 0, Z), " &
"143 (BC_4, SIZ(0), input, X), " &
"144 (BC_2, R_W, output3, X, 156, 0, Z), " &
"145 (BC_4, R_W, input, X), " &
"146 (BC_2, LOCKE, output3, X, 155, 0, Z), " &
"147 (BC_2, SIZ(1), output3, X, 156, 0, Z), " &
"148 (BC_4, SIZ(1), input, X), " &
"149 (BC_2, LOCK, output3, X, 155, 0, Z), " &
"150 (BC_2, *, controlr, 0), " & -- io.ab
"151 (BC_2, *, controlr, 0), " & -- io.db
"152 (BC_2, MI, output2, X), " &
"153 (BC_2, BR, output2, X), " &
"154 (BC_2, *, controlr, 0), " & -- io.2
"155 (BC_2, *, controlr, 0), " & -- io.1
"156 (BC_2, *, controlr, 0), " & -- io.0
"157 (BC_2, TS, output3, X, 156, 0, Z), " & -- 156 = io.0
"158 (BC_4, TS, input, X), " &
"159 (BC_2, BB, output3, X, 155, 0, Z), " & -- 155 = io.1
--num cell port function safe ccell dsval rslt
"160 (BC_4, BB, input, X), " &
"161 (BC_2, TIP, output3, X, 155, 0, Z), " & -- 155 = io.1
"162 (BC_2, PST(3), output2, X), " &
"163 (BC_2, PST(2), output2, X), " &
"164 (BC_2, PST(1), output2, X), " &
"165 (BC_2, PST(0), output2, X), " &
"166 (BC_2, TA, output3, X, 154, 0, Z), " & -- 154 = io.2
"167 (BC_4, TA, input, X), " &
"168 (BC_4, TEA, input, X), " &
"169 (BC_4, BG, input, X), " &
"170 (BC_4, SC(1), input, X), " &
"171 (BC_4, SC(0), input, X), " &
"172 (BC_4, TBI, input, X), " &
"173 (BC_4, AVEC, input, X), " &
"174 (BC_4, TCI, input, X), " &
"175 (BC_4, DLE, input, X), " &
"176 (BC_4, PCLK, input, X), " &
"177 (BC_4, BCLK, input, X), " &
"178 (BC_4, IPL(0), input, X), " &
"179 (BC_4, IPL(1), input, X), " &
--num cell port function safe ccell dsval rslt
"180 (BC_4, IPL(2), input, X), " &
"181 (BC_4, RSTI, input, X), " &
"182 (BC_4, CDIS, input, X), " &
"183 (BC_4, MDIS, input, X) ";
attribute DESIGN_WARNING of MC68040: entity is
"A non-standard clocking protocol on BCLK and PCLK must be " &
"observed when entering Boundary Scan Test Mode.";
end MC68040;